Forming Or Treating Article Containing Magnetically Responsive Material Patents (Class 216/22)
  • Patent number: 11120823
    Abstract: According to one embodiment, a suspension assembly includes a support plate having a distal end portion and a base end portion, a wiring member having a gimbal portion and provided on the support plate, and a magnetic head mounted on the gimbal portion. In the gimbal portion, the wiring member includes a head mounting region where the magnetic head is mounted, and an etching region including a recess located and formed at least partially in the head mounting region. The magnetic head is bonded to the head mounting region of the wiring member by an adhesive filled in the head mounting region and the recess.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: September 14, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hirofumi Nesori, Kenichiro Aoki
  • Patent number: 11101800
    Abstract: An NAND or NOR logic device has multiple layers of ferromagnetic material separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. The anti-magnetic response in a layer below a layer magnetized with a polarity is summed in a region which is coupled to an output, the output generating at least one of a NAND, or NOR logic function on applied input magnetization.
    Type: Grant
    Filed: August 29, 2020
    Date of Patent: August 24, 2021
    Assignee: Redpine Signals, Inc.
    Inventors: Venkat Mattela, Sanghamitra Debroy, Santhosh Sivasubramani, Amit Acharyya
  • Patent number: 11088323
    Abstract: A method for forming a memory device is provided. The method including forming a memory cell stack over a lower interconnect layer over a substrate, the memory cell stack includes a data storage layer over a bottom metal. A first dielectric layer is formed over the memory cell stack. A first masking layer is formed over the first dielectric layer. The first masking layer overlies a center portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered. A first etch of the first dielectric layer is formed according to the first masking layer. An inter-metal dielectric (IMD) layer is formed over the memory cell stack. A top electrode is formed within the IMD layer over the memory cell stack. An upper interconnect layer is formed over the top electrode. The upper and lower interconnect layers comprise a different material than the top electrode.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Yen Chou
  • Patent number: 11056258
    Abstract: A production method for a magnetic material, which is expressed by a chemical structure formula Fe(Al1-xMnx)2O4, where 0<x<1, and exhibits ferromagnetism, includes: preparing a mixed aqueous solution by dissolving, in distilled water, Fe nitrate, Al nitrate, and an oxide including Mn, the Fe nitrate, the Al nitrate, and the oxide being parent materials; preparing a metal-citric acid complex by mixing citric acid and ethylene glycol with the mixed aqueous solution; obtaining a precursor by boiling the metal-citric acid complex to a gel and drying the gel; and obtaining the magnetic material by sintering the precursor.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: July 6, 2021
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., THE DOSHISHA
    Inventors: Ken Hirota, Masaki Kato, Junichi Kotani, Nobuya Matsutani
  • Patent number: 11049553
    Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 29, 2021
    Assignee: R&D 3 LLC
    Inventor: Ravindraraj Ramaraju
  • Patent number: 11037593
    Abstract: The present disclosure relates to separating parts (e.g., sliders and/or row bars) from an adhesive and carrier during the manufacture of parts to be used in a data storage device such as a hard disc drive.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 15, 2021
    Assignee: Seagate Technology LLC
    Inventors: Ruhai Tian, Gary M Singer, Peter J. Gunderson
  • Patent number: 11004872
    Abstract: A display substrate and a method of manufacturing a display substrate, the display substrate including a base substrate; a gate electrode on the base substrate; an insulation layer on the gate electrode; a source electrode and a drain electrode on the insulation layer and overlapping the gate electrode; and a pixel electrode electrically connected to the drain electrode, wherein a cavity is formed between the gate electrode and the insulation layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Nakcho Choi, Suwan Woo, Yeogeon Yoon, Dae-Young Lee, Joonggun Chong, Jonghak Hwang
  • Patent number: 10910554
    Abstract: A spin-current magnetization rotational element includes a spin orbit torque wiring extending in a first direction and a first ferromagnetic layer disposed in a second direction intersecting the first direction of the spin orbit torque wiring, the spin orbit torque wiring having a first surface positioned on the side where the first ferromagnetic layer is disposed, and a second surface opposite to the first surface, and the spin orbit torque wiring has a second region on the first surface outside a first region in which the first ferromagnetic layer is disposed, the second region being recessed from the first region to the second surface side.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 2, 2021
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Yohei Shiokawa
  • Patent number: 10910008
    Abstract: The magnetic recording medium includes a non-magnetic support; a non-magnetic layer including a non-magnetic powder and a binding agent on the non-magnetic support; and a magnetic layer including a ferromagnetic powder, a binding agent, and a non-magnetic powder on the non-magnetic layer, in which a skewness Rsk obtained using an atomic force microscope in a measurement region of a surface of the magnetic layer having a size of 5 ?m×5 ?m is greater than 0, a maximum peak height Rmax is equal to or smaller than 30.0 nm, and the number of projections having a height equal to or greater than 10 nm is equal to or greater than 10, and a magnetic recording and reproducing device including: this magnetic recording medium; and a magnetic head.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 2, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Masahiko Mori, Yoshihiro Sawayashiki
  • Patent number: 10866527
    Abstract: A method for monitoring a lithographic process, and associated lithographic apparatus. The method includes obtaining height variation data relating to a substrate supported by a substrate support and fitting a regression through the height variation data, the regression approximating the shape of the substrate; residual data between the height variation data and the regression is determined; and variation of the residual data is monitored over time. The residual data may be deconvolved based on known features of the substrate support.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 15, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Emil Peter Schmitt-Weaver, Kaustuve Bhattacharyya, Wim Tjibbo Tel, Frank Staals, Leon Martin Levasier
  • Patent number: 10847715
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 10840436
    Abstract: A Magnetic Tunnel Junction (MTJ) device can include a free magnetic layer having a predetermined smoothness. An etching process for smoothing the free magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 17, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Bartlomiej Kardasz, Jorge Vasquez, Mustafa Pinarbasi
  • Patent number: 10811036
    Abstract: A magnetic head, according to one embodiment, includes a rowbar substrate having a tape support surface and a gap surface at a substrate edge. A closure is positioned opposite the gap surface of the rowbar substrate, the closure forming a portion of the tape support surface. A recessed gap region is interposed between the gap surface of the rowbar substrate and the closure, the recessed gap region having a recessed gap profile that extends between the gap surface of the rowbar substrate and the closure, the recessed gap region having a transducer row with at least one magnetic sensor on the gap surface of the rowbar substrate. An insulation layer is positioned over the recessed gap profile of the recessed gap region.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Biskeborn, Icko E. T. Iben, Jason Liang
  • Patent number: 10734014
    Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a main pole at a media facing surface (MFS), a trailing shield at the MFS, and a heavy metal layer disposed between the main pole and the trailing shield at the MFS. Spin-orbit torque (SOT) is generated from the heavy metal layer and transferred to a surface of the main pole as a current passes through the heavy metal layer in a cross-track direction. The SOT executes a torque on the surface magnetization of the main pole, which reduces the magnetic flux shunting from the main pole to the trailing shield. With the reduced magnetic flux shunting from the main pole to the trailing shield, write-ability is improved.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Suping Song, Zhanjie Li, Michael Kuok San Ho, Quang Le, Alexander M. Zeltser
  • Patent number: 10651372
    Abstract: A process and device is disclosed for etching a magnetroresistive random access memory device which includes at least one magnetic tunnel junction stack structure which includes an insulating layer disposed between first and second magnetic layers. The process includes the step of contacting a substrate with a chlorine containing plasma at a temperature no greater than 30 degrees Centigrade under conditions effective to convert at least a portion of the first and second magnetic layers and the insulating layer into metal chlorides. Next, the resulting product of the contacting step is treated with an organic solvent under conditions effective to remove the metal chlorides. The treatment can include rinsing away the metal chlorides either by dissolving the metal chlorides, or by reacting the metal chlorides with a reactive organic solvent, or both.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 12, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Qingyun Yang
  • Patent number: 10649058
    Abstract: A method for recording a magnetic resonance data set relating to a region that is moved at least partly and periodically includes prompting a trigger signal. The method also includes emitting a saturation pulse to at least partially saturate magnetization of an examination region as a function of the trigger signal.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Siemens Healthcare GmbH
    Inventors: Ralf Kartäusch, Dominik Paul
  • Patent number: 10593355
    Abstract: A recording head that includes a bearing surface and a write pole having a front surface that forms a portion of the bearing surface. The recording head also includes a side shield for the write pole. The side shield includes a low saturation magnetization cap layer having a front surface that forms a portion of the bearing surface. The side shield also includes a main side shield layer having a saturation magnetization that is higher than a saturation magnetization value of the low saturation magnetization cap layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 17, 2020
    Assignee: Seagate Technology LLC
    Inventors: Swaraj Basu, Prim Gangmei, Angela Moore, Mark Anthony Gubbins, Beverley R. McConnell
  • Patent number: 10593356
    Abstract: A magnetoresistive (MR) sensor shield shields against both down track and cross-track interference and is formed in a single deposition step. A “tail” portion of the shield is eliminated by including a non-magnetic material adjacent to opposite sides of a middle portion of the sensor stack.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 17, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Xin Cao, Frances Paula McElhinney, Jiansheng Xu, Marcus Winston Ormston
  • Patent number: 10586559
    Abstract: A method includes forming a write pole layer having a front surface, a leading surface, a trailing surface and side surfaces connecting the leading surface to the trailing surface. The method also includes forming side shield layers proximate to the side surfaces of the write pole layer. A patterned sacrificial layer is deposited over the side shield layers, and a trailing surface bevel is formed on the write pole layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 10, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jia Sun, Dong Lin, Shen Zhe, Jianhua Xue, Wei Tian, Joe Mundenar
  • Patent number: 10553241
    Abstract: A method and system provides a near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) transducer. The method and system include forming the disk of the NFT and forming the pin of the NFT. The disk is formed from a first material. The pin is formed from a second material different from the first material. The pin contacts the disk. At least a portion of the pin is between the disk and an air-bearing surface (ABS) location.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: February 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kris Vossough, Xiaokai Zhang, Armen Kirakosian, Jinwen Wang, Tsung Yuan Chen, Yufeng Hu
  • Patent number: 10522749
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dongna Shen, Yu-Jen Wang, Ru-Ying Tong, Vignesh Sundar, Sahil Patel
  • Patent number: 10515777
    Abstract: This ion milling device is provided with a vacuum chamber (105), an exhaust device (101) for evacuating the interior of the vacuum chamber, a sample stage (103) for supporting a sample (102) to be irradiated inside the vacuum chamber, a heater (107) for heating the interior of the vacuum chamber, a gas source (106) for introducing into the vacuum chamber a gas serving as a heating medium, and a controller (110) for controlling the gas source, the controller controlling the gas source so that the vacuum chamber internal pressure is in a predetermined state during heating by the heater. This enables the control in a short time of the temperature for suppressing condensation, or the like, occurring at atmospheric release after cooling and ion milling a sample.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 24, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Atsushi Kamino, Hisayuki Takasu, Hirobumi Muto
  • Patent number: 10490248
    Abstract: The present disclosure provides a magnetic random access memory structure, including an array region, and a logic region adjacent to the array region. The logic region includes a bottom electrode via, a magnetic tunneling junction layer over the bottom electrode via, a top electrode over the MTJ, a conformable oxide layer over the MTJ and the top electrode, and a silicon oxide layer over the conformable oxide layer. The conformable oxide layer and the silicon oxide layer extend from the array region to the logic region.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Chang Chen
  • Patent number: 10483460
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: November 19, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Wenchin Lin, Sarin A. Deshpande, Jijun Sun, Sanjeev Aggarwal, Chaitanya Mudivarthi
  • Patent number: 10461145
    Abstract: A method for fabricating a magnetic core includes depositing a magnetic layer on a dielectric layer, forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer, etching the magnetic layer through the patterned first photoresist layer, in which a first section of the magnetic layer exposed by the first photoresist layer remains on the dielectric layer after the magnetic layer is etched, removing the patterned first photoresist layer, forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer, etching the magnetic layer through the patterned second photoresist layer, and removing the second photoresist layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 10446209
    Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 15, 2019
    Assignee: Samsung Semiconductor Inc.
    Inventors: Steven M. Watts, Zhitao Diao, Xueti Tang, Kiseok Moon, Mohamad Towfik Krounbi
  • Patent number: 10396279
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 27, 2019
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 10366880
    Abstract: A second protective film is formed by applying high-viscosity resin by an inkjet method, in two patterns that extend parallel to and along a boundary between a first protective film and a plating film, the boundary being sandwiched between the two patterns. A low-viscosity resin is applied between these first and second patterns of the second protective film by the inkjet method. The low-viscosity resin has a viscosity that is lower than that of the high-viscosity resin for forming the second protective film, and a fluidity that is higher than that of the high-viscosity resin and thus, leaks and spreads into a gap between the first protective film and the plating film. The third protective film adheres to the first and second patterns, is formed across the boundary between the first protective film and the plating film, and is embedded in the gap whereby the gap is plugged.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichi Kawano
  • Patent number: 10345520
    Abstract: An optical device and a method of manufacturing an optical device, including a ridge waveguide second, and a strip-loaded ridge waveguide section, comprises applying two different protective layers and two separate etches at two different depths. The protective layers overlap to protect the same section of the optical device, and to limit the surfaces of optical device to exposure to multiple etches, except at edges where the protective layers overlap.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Wetteland Baehr-Jones, Ruizhi Shi
  • Patent number: 10266950
    Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Yousong Zhang, Mark Jenson
  • Patent number: 10269637
    Abstract: A semiconductor structure includes a substrate, a hole which includes a top hole and a bottom hole in communication with each other in the substrate, and a filler in the top hole and the bottom hole, wherein the top hole tapers toward the bottom hole, and a side surface of the top hole and a side surface of the bottom hole form an obtuse angle.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lee-Chuan Tseng, Lung-Yuan Pan, Chung-Yen Chou
  • Patent number: 10261371
    Abstract: A method for manufacturing a glass substrate comprises a surface processing step of performing surface processing for forming unevenness on a glass surface. In the surface processing step, protruded portions having a height of 1nm or more from an average line of a roughness curve are dispersedly formed on the glass surface. In the surface processing step, the surface processing is performed such that a protruded portion area ratio is 0.5 to 10%. The protruded portion area ratio is a ratio of an area of the protruded portions with respect to an area of any rectangular region. The rectangular region has a square shape with a side length of 1 ?m. In the surface processing step, in a case where the rectangular region is equally divided into at least one hundred divided regions having a square shape, the surface processing is performed such that a protruded portion content ratio is 80% or more.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 16, 2019
    Assignee: AvanStrate Inc.
    Inventor: Young Tae Park
  • Patent number: 10224211
    Abstract: There is provided an etching method for etching an antireflection film including silicon according to a pattern of a resist film by using plasma processing with respect to a processing object, the processing object including an etching object film, the antireflection film including silicon laminated on the etching object film, and the resist film laminated on the antireflection film including silicon. The method includes generating plasma of a processing gas containing a fluorocarbon gas in a processing chamber, the processing object being disposed in the processing chamber, and generating plasma of a processing gas containing an inactive gas in the processing chamber, the processing object being disposed in the processing chamber. A set of the first generating and the second generating are repeatedly performed.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 5, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Hikaru Watanabe, Akihiro Tsuji
  • Patent number: 10211395
    Abstract: A method for manufacturing a magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in a second area of the chip. For example, the first set of magnetic random access memory elements can have performance characteristics that match or exceed those of a non-volatile memory, whereas the second set of magnetic random access memory elements can have performance characteristic that match or exceed those of a static random access memory element.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz, Thomas D. Boone
  • Patent number: 10204670
    Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-kyung Kim, Dong-seok Kang, Hye-jin Kim, Chul-woo Park, Dong-hyun Sohn, Yun-sang Lee, Sang-beom Kang, Hyung-rock Oh, Soo-ho Cha
  • Patent number: 10187986
    Abstract: A wiring substrate includes a first wiring layer on a surface of a first insulating layer; a via interconnect including a first portion connected to the first wiring layer and a second portion formed monolithically with the first portion and extending from an end of the first portion in a direction away from the first wiring layer; a second insulating layer on the first insulating layer; and a second wiring layer on the second insulating layer, contacting a first surface of the second portion. The area of a cross section of the first portion, parallel to the surface of the first insulating layer, increases as the position of the cross section approaches the first wiring layer from the second portion. The second portion includes a second surface that is opposite from its first surface and extends horizontally from the end of the first portion to overhang the first portion.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: January 22, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Satoshi Sunohara
  • Patent number: 10186283
    Abstract: A method of forming a peg of a NFT, the peg having a tapered portion, the method including depositing a layer of dielectric material; forming a three dimensional shape from at least a portion of the dielectric material the three dimensional shape having two side surfaces and two end surfaces; and depositing plasmonic material on at least one side surface of the three dimensional shape of dielectric material, wherein the plasmonic material deposited on the at least one side surface forms the tapered portion of the peg.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: January 22, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sridhar Dubbaka, YongJun Zhao, David Michael Grundman
  • Patent number: 10049689
    Abstract: Methods that include depositing a first layer over the entire surface of a structure, the structure having a magnetic reader and a magnetic writer, wherein the magnetic reader and the magnetic writer are positioned adjacent to each other on a substrate and the magnetic writer includes a near field transducer (NFT); depositing a second layer over the entire surface of the first layer; depositing a photoresist material layer over the entire surface of the second layer, the photoresist material layer having a bottom surface in contact with the second layer and an opposing top surface; exposing the photoresist material layer to radiation through the bottom surface of the photoresist material layer via the NFT to form a first exposed region; and exposing the photoresist material layer to radiation through the top surface of the photoresist material layer to form a second exposed region.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventors: Joseph Michael Stephan, Douglas H. Cole, Daniel Richard Buettner
  • Patent number: 10020512
    Abstract: Polymers for use as protective layers and other components in electrochemical cells are provided. In some embodiments, the electrochemical cell is a lithium-based electrochemical cell.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 10, 2018
    Assignees: Sion Power Corporation, BASF SE
    Inventors: Oliver Gronwald, Igor P. Kovalev, Ashley H. Bulldis, Yuriy V. Mikhaylik
  • Patent number: 9978563
    Abstract: Provided is a method of patterning a layer on a substrate using an integration scheme, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material; performing a first treatment process using a first process gas mixture to form a first pattern, the first process gas comprising a mixture of CxHyFz and argon; performing a second treatment process using a second process gas mixture to form a second pattern, the second process gas comprising a mixture of low oxygen-containing gas and argon; concurrently controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 22, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Luong, Akiteru Ko
  • Patent number: 9972345
    Abstract: A method includes depositing a layer of pole material on a substrate. The layer of pole material has a bottom surface that is adjacent to the substrate and a top surface that is opposite the bottom surface. A masking material is deposited over a portion of the top surface. Material from the pole material unprotected by the masking material is removed to form a write pole having first and second side walls. At least a portion of a trench formed by removal of the material from the layer of pole material is filled with a sacrificial material. The mask and a portion of the write pole at the top surface are removed to form a beveled trailing edge surface. The sacrificial material is then removed. Front shield gap material is deposited over the beveled trailing edge surface and over portions of the side walls.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 15, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Wei Tian, Hauqing Yin, Lei Lu, Yong Luo, Joseph Mundenar
  • Patent number: 9966096
    Abstract: In one embodiment, a structure includes: a substrate; and a monolayer of nanoparticles positioned above the substrate, where the nanoparticles are each grafted to one or more oligomers and/or polymers, and where each of the polymers and/or oligomers includes at least a first functional group configured to bind to the nanoparticles. In another embodiment, a structure includes: a substrate; a structured layer positioned above the substrate, the structured layer comprising a plurality of nucleation regions and a plurality of non-nucleation regions; and a crystalline layer positioned above the structured layer, where the plurality of nucleation regions have a pitch in a range between about 5 nm to about 20 nm.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 8, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Chen, Nicholas R. Conley, Bruce A. Gurney, Ricardo Ruiz, Lei Wan, Qing Zhu
  • Patent number: 9966271
    Abstract: Methods for forming semiconductor devices, such as FinFET devices, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets and a bottom surface including two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed by an isotropic plasma etch process. The isotropic plasma etch process may be performed at a pressure ranging from about 5 mTorr to about 200 mTorr in order to maximize the amount of radicals while minimizing the amount of ions in the plasma. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 8, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Hua Chung, Xuebin Li, Yuxiang Lu
  • Patent number: 9958441
    Abstract: A biosensing FET device, comprising a plurality of nanostructured SOI channels, that is adapted to operate in solutions having a high ionic strength and provides improves sensitivity and detection. Generally, the biosensing device comprises an underlying substrate layer, an insulator and a semiconductor layer and a plurality of channels in the semiconductor layer comprising a plurality of whole or partially formed nanopores in the channels.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 1, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: An-Ping Zhang, Anthony John Murray, Rui Chen
  • Patent number: 9905259
    Abstract: Provided herein is a method, including forming a first template including a first pattern, wherein forming the first template includes self-assembly of diblock copolymers guided by an initial pattern; forming a second template including a second pattern, wherein the second pattern corresponds to a servo pattern; and forming a master template from the first template, wherein the master template includes one or more portions of the first pattern combined with the second pattern.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 27, 2018
    Assignee: Seagate Technology LLC
    Inventors: Sundeep Chauhan, Alexander Kantorov, Kim Yang Lee, David Kuo, Rene Johannes Marinus Van de Veerdonk, Barmeshwar Vikaramaditya
  • Patent number: 9865508
    Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9840781
    Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Yousong Zhang, Mark Jenson
  • Patent number: 9830935
    Abstract: An apparatus that includes a read sensor having a bearing surface and first and second free layers that are separated by an intermediate structure. The first FL includes multiple segments, with each segment having a width at the bearing surface. A sum of the widths of different ones of the multiple segments is a first width of the first FL. The second FL is unsegmented and has a second width at the bearing surface that is different from the first width of the first FL. The read sensor also includes a first terminal connected to a first one of the multiple segments of the first FL, and a second terminal connected to a second one of the multiple segments of the first FL. A third terminal is connected to the second FL. Control circuitry applies a bias current from either the first or second terminal to the third terminal.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 28, 2017
    Assignee: Seagate Technology LLC
    Inventors: Kaizhong Gao, Wenzhong Zhu, Edward Gage
  • Patent number: 9768377
    Abstract: A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a tantalum portion, and a ruthenium portion overlying the platinum portion. The magnetic cell structure comprises a magnetic region overlying the seed material, an insulating material overlying the magnetic region, and another magnetic region overlying the insulating material. Semiconductor devices including the magnetic cell structure, methods of forming the magnetic cell structure and the semiconductor devices are also disclosed.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Jonathan D. Harms, Sunil Murthy
  • Patent number: 9761252
    Abstract: An apparatus has a main pole layer of magnetic material, a second layer of magnetic material, a first gap layer of non-magnetic material between the main pole layer and the second layer of magnetic material, and a second gap layer of non-magnetic material disposed between the main pole layer and the second layer of magnetic material. The second gap layer of non-magnetic material can be directly adjacent to the second layer of magnetic material. In accordance with one embodiment, this allows the gap to serve as a non-magnetic seed for the second layer of magnetic material. A method of manufacturing such a device is also described.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 12, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Wei Tian, Venkateswara Rao Inturi, Dong Lin, Huaqing Yin, Jiaoming Qiu