Etching And Coating Occur In The Same Processing Chamber Patents (Class 216/37)
  • Patent number: 10566212
    Abstract: Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 18, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Keren Jacobs Kanarik
  • Patent number: 10526206
    Abstract: Yield of products of increased purity from a fluidized bed reactor where silicon is produced or consumed is enhanced by purging with inert gas, purging with hydrogen gas, and purging with a chlorosilane-containing gas. The purging with hydrogen is conducted at an elevated temperature.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 7, 2020
    Assignee: WACKER CHEMIE AG
    Inventor: Dirk Weckesser
  • Patent number: 10510883
    Abstract: The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Peng Wang
  • Patent number: 10438775
    Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 8, 2019
    Assignee: Lam Research Corporation
    Inventor: Arthur Sato
  • Patent number: 10347499
    Abstract: In a method of an embodiment, radicals, which are generated from a processing gas, is adsorbed to a layer to be etched without applying a high-frequency bias to a lower electrode, in an adsorption step. In the subsequent etching step, ions, which are generated from the processing gas, are drawn into the layer to be etched by applying a high-frequency bias to the lower electrode. The adsorption step and the etching step are alternately repeated. In the adsorption step, a density of radicals is 200 or greater times a density of ions. In the etching step, RF energy having a power density of 0.07 W/cm2 or less is supplied to the lower electrode or a high-frequency bias having a power density of 0.14 W/cm2 or less is supplied to the lower electrode for a period of 0.5 seconds or less.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Maruyama, Akira Koshiishi, Toshio Haga, Masato Horiguchi, Makoto Kato
  • Patent number: 10347463
    Abstract: Method and system for enhanced charged particle beam processes for carbon removal. With the method and system for enhancing carbon removal, associated method and system for decreasing levels of carbon impurity in depositions, also using a precursor gas in charged particle beam processes (and particularly focused ion beam methodologies), are provided. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 9, 2019
    Assignee: FEI Company
    Inventors: Chad Rue, Joe Christian, Kenny Mani, Noel Thomas Franco
  • Patent number: 10336609
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Watanabe, Shuntaro Machida, Katsuya Miura, Aki Takei, Tetsufumi Kawamura, Nobuyuki Sugii, Daisuke Ryuzaki
  • Patent number: 10265671
    Abstract: A fluidized bed reactor includes a gas distributor, a tapered section above the gas distributor, and an expanded head above the tapered section. The gas distributor defines a plurality of inlets surrounding a product withdrawal tube, which extends away from the fluidized bed reactor. The fluidized bed reactor is useful in a process for fluidizing relatively large particles, such as Geldart Group B particles and/or Geldart Group D particles, where said particles are in a bubbling fluidized bed residing, in whole or in part, in the tapered section. The fluidized bed reactor and process may be used for manufacturing polycrystalline silicon.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 23, 2019
    Assignee: HEMLOCK SEMICONDUCTOR OPERATIONS LLC
    Inventors: John V. Bucci, Raymond Anthony Cocco, Max E. Dehtiar, Patrick J. Harder, S. B. Reddy Karri, Ted M. Knowlton, Michael J. Molnar
  • Patent number: 10262839
    Abstract: In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75° C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Chien Chiu, Bing-Hung Chen, Keith Kuang-Kuo Koai
  • Patent number: 10240230
    Abstract: The invention relates to the use of thionyl chloride and related materials for dry etching of internal surfaces of metalorganic vapor phase epitaxy (MOVPE) reactors to remove deposits. The method is also useful for the dry etching of process substrates within such reactors for cleaning and processing of those substrates. The invention may be particularly adaptable to chemical vapor deposition reactors used in the manufacture of high brightness LED's based on III-V semiconductors such as GaN and related materials. Features of the process include thermal, UV, and plasma activated dry cleaning, and the use of etchant gases such as COCl2, COBr2, COl2, SOl2, SOCl2, SOBr2, SO2Cl2, SO2Br2, NOCI, NOBr, NOl, S2Cl2, S2Br2, SCI2, SBr2, SOClBr, SOClF and SOFBr, either formed from neat materials or combinations of constituent gases such as CO, SO, SO2 or NO with halogens, to achieve the desired effect.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 26, 2019
    Assignee: SEASTAR CHEMICALS INC.
    Inventor: Rajesh Odedra
  • Patent number: 10184184
    Abstract: The invention concerns a method of forming a graphene layer involving: heating a support layer in a reaction chamber; and forming the graphene layer on a surface of the support layer by: a) during a first time period, introducing into the reaction chamber an organic compound gas to cause a formation of carbon atoms on the surface; b) during a second time period after the first time period, reducing a rate of introduction of the organic compound gas into the reaction chamber and introducing into the reaction chamber a further gas, wherein the further gas is a carbon etching gas; and repeating a) and b) one or more times.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 22, 2019
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Vincent Bouchiat, Johann Coraux, Zheng Han
  • Patent number: 10170336
    Abstract: Embodiments of the present technology may include a method of etching. The method may include flowing a gas through a plasma to form plasma effluents. The method may also include reacting plasma effluents with a first layer defining a first feature. The first feature may include a first sidewall, a second sidewall, and a bottom. The first sidewall, the second sidewall, and the bottom may include the first layer. The first layer may be characterized by a first thickness on the sidewall. The method may further include forming a second layer from the reaction of the plasma effluents with the first layer. The first layer may be replaced by the second layer. The second layer may be characterized by a second thickness. The second thickness may be greater than or equal to the first thickness. The method may also include removing the second layer to expose a third layer.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 1, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zihui Li, Chia-Ling Kao, Anchuan Wang, Nitin K. Ingle
  • Patent number: 10170324
    Abstract: Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Nikhil Dole, Eric A. Hudson, George Matamis
  • Patent number: 10096499
    Abstract: A substrate processing method of the present disclosure includes forming a film on a workpiece using a processing gas in a processing chamber with a setting temperature profile including increase or decrease of a temperature; and etching the film. An etching rate of the film in the etching depends on a film formation temperature in the forming. The setting temperature profile is determined based on a first temperature dependence of the etching rate in the etching on the film formation temperature, and a second temperature dependence of a film formation amount in the forming on the film formation temperature.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: October 9, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Yuichi Takenaga, Syuji Nozawa
  • Patent number: 10096487
    Abstract: Provided herein are methods of atomic layer etching (ALE) of metals including tungsten (W) and cobalt (Co). The methods disclosed herein provide precise etch control down to the atomic level, with etching a low as 1 ? to 10 ? per cycle in some embodiments. In some embodiments, directional control is provided without damage to the surface of interest. The methods may include cycles of a modification operation to form a reactive layer, followed by a removal operation to etch only this modified layer. The modification is performed without spontaneously etching the surface of the metal.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 9, 2018
    Assignee: Lam Research Corporation
    Inventors: Wenbing Yang, Samantha Tan, Keren Jacobs Kanarik, Jeffrey Marks, Taeseung Kim, Meihua Shen, Thorsten Lill
  • Patent number: 10043658
    Abstract: A full fill trench structure is described, including a microelectronic device substrate having a high aspect ratio trench therein and filled with silicon dioxide of a substantially void-free character and substantially uniform density throughout its bulk mass. A method of manufacturing a semiconductor product also is described, involving use of specific silicon precursor compositions for forming substantially void-free and substantially uniform density silicon dioxide material in the trench. The precursor fill composition may include silicon and germanium, to produce a microelectronic device structure including a GeO2/SiO2 trench fill material. A suppressor component may be employed in the precursor fill composition, to eliminate or minimize seam formation in the cured trench fill material.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 7, 2018
    Assignee: Entegris, Inc.
    Inventors: William Hunks, Chongying Xu, Bryan C. Hendrix, Jeffrey F. Roeder, Steven M. Bilodeau, Weimin Li
  • Patent number: 10043639
    Abstract: A substrate processing method includes an etching step of mounting a substrate on a surface of a rotatory table arranged in a vacuum chamber and supplying an etching gas into the vacuum chamber while rotating the rotary table to etch a film formed on a surface of the substrate. The etching step includes supplying the etching gas to the surface of the rotary table and supplying a purge gas from a plurality of purge gas supply units that are provided near a region where the etching gas is supplied, and controlling an etching amount of etching the film by independently varying a flow rate of the purge gas that is supplied from each of the plurality of purge gas supply units.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 7, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Shigehiro Miura
  • Patent number: 10010500
    Abstract: Implantable compositions providing release of bioactive agents according to a predetermined release profile and methods for their use. Such compositions include at least one ceramic substrate; a bioactive substance loaded on a surface of the ceramic substrate forming a loaded surface zone operable to release said bioactive substance according to a release profile under physiological conditions; and a biodegradable polymer having an in vivo degradation period, forming a continuous or discontinuous coating on an area of the ceramic substrate.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: July 3, 2018
    Assignee: Biomet Manufacturing, LLC
    Inventor: Mukesh Kumar
  • Patent number: 10008388
    Abstract: The present disclosure generally relates to methods of removing oxides and oxide-containing layers from the surfaces of substrates. In one aspect, a method of processing a substrate comprises positioning a substrate in a process chamber, the substrate having an oxide layer thereon; introducing one or more process gases to an interior of the process chamber; ionizing the one or more process gases; exposing the oxide layer to the one or more ionized process gases, wherein the process chamber is maintained at a pressure less than about 50 mTorr during the exposing, and the substrate is maintained at a temperature within a range of about zero degrees Celsius to about 30 degrees Celsius during the exposing; and removing the oxide layer from the surface of the substrate.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 26, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ping Han Hsieh, Teng-fang Kuo, Shi Wei Toh, Avgerinos V. Gelatos
  • Patent number: 9978586
    Abstract: A method and apparatus for material deposition onto a sample to form a protective layer composed of at least two materials that have been formulated and arranged according to the material properties of the sample.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 22, 2018
    Assignee: FEI Company
    Inventors: Brian Roberts Routh, Jr., Thomas G. Miller, Chad Rue, Noel Thomas Franco
  • Patent number: 9865484
    Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Bhargav Citla, Chentsau Ying, Srinivas Nemani, Viachslav Babayan, Michael Stowell
  • Patent number: 9852924
    Abstract: A method for reducing sidewall roughness in an etch layer below a first mask with sidewall roughness in a processing chamber is provided. Sidewalls of the first mask are smoothed, comprising, flowing a processing gas into the processing chamber and forming the processing gas into an in situ plasma in the processing chamber with sufficient energy to sputter and smooth sidewall roughness of the first patterned mask. The etch layer is etched through the first patterned mask.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Hua Xiang, Yiting Zhang, Qian Fu, Qing Xu
  • Patent number: 9818640
    Abstract: A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jason Eugene Stephens, Guillaume Bouche
  • Patent number: 9793136
    Abstract: A plasma etching method can form a hole having a required opening diameter in a silicon nitride layer, while suppressing a tip end portion of the hole from being narrowed. The plasma etching method includes a first process of supplying a processing gas containing oxygen and fluorocarbon into a plasma processing apparatus; and a second process of etching a silicon nitride layer 106a of a processing target object with a first mask 106 by exciting the processing gas into plasma. Further, the second process is performed in a state where an organic film ad generated from the processing gas is formed on an inner wall of an opening of the first mask 106 by gradually reducing a temperature of the processing target object from a first temperature T1 (80° C.) to a second temperature T2 (40° C.).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 17, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kosei Ueda, Yoshinobu Hayakawa
  • Patent number: 9786503
    Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 10, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique D. Raley, Nihar Mohanty, Akiteru Ko
  • Patent number: 9768033
    Abstract: This disclosure relates to a plasma processing system and methods for high precision etching of microelectronic substrates. The system may include a combination of microwave and radio frequency (RF) power sources that may generate plasma conditions to remove monolayer(s). The system may generation a first plasma to form a thin adsorption layer on the surface of the microelectronic substrate. The adsorbed layer may be removed when the system transition to a second plasma. The differences between the first and second plasma may be include the ion energy proximate to the substrate. For example, the first plasma may have an ion energy of less than 20 eV and the second plasma may have an ion energy greater than 20 eV.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: September 19, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Mingmei Wang, Peter L. G. Ventzek
  • Patent number: 9767991
    Abstract: For a first period of time, a higher radiofrequency power is applied to generate a plasma in exposure to a substrate, while applying low bias voltage at the substrate level. For a second period of time, a lower radiofrequency power is applied to generate the plasma, while applying high bias voltage at the substrate level. The first and second periods of time are repeated in an alternating and successive manner for an overall period of time necessary to produce a desired effect on the substrate. In some embodiments, the first period of time is shorter than the second period of time such that on a time-averaged basis the plasma has a greater ion density than radical density. In some embodiments, the first period of time is greater than the second period of time such that on a time-averaged basis the plasma has a lower ion density than radical density.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: September 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu
  • Patent number: 9728421
    Abstract: A method of etching a pattern into a dielectric layer is provided. An organic planarization layer having a pattern is provided atop a dielectric layer. A cyclic fluorocarbon deposition step and plasma step is performed to etch the pattern into the dielectric layer. The energy for the plasma step is kept below the etch threshold of the dielectric layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sebastian U. Engelmann, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9679780
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying NH3 (ammonia) and NF3 (nitrogen trifluoride) or by applying BHF (buffered hydrofluoric acid). The first etching process is RIE (reactive ion etching) and the second etching process involves applying NF3 and H2 (hydrogen gas).
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Nicolas J. Loubet
  • Patent number: 9662625
    Abstract: The present invention provides a reactor and a method for the production of high purity silicon granules. The reactor includes a reactor chamber; and the reaction chamber is equipped with a solid feeding port, auxiliary gas inlet, raw material gas inlet, and exhaust gas export. The reaction chamber is also equipped with an internal gas distributor; a heating unit; an external exhaust gas processing unit connected between a preheating unit and a gas inlet. The reaction chamber is further equipped with a surface finishing unit, a heating unit and a dynamics generating unit. The reaction is through decomposition of silicon-containing gas in densely stacked high purity granular silicon layer reaction bed in relative motion, and to use remaining heat of exhaust gas for reheating. The present invention achieves a large scale, efficient, energy saving, continuous, low cost production of high purity silicon granules.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: May 30, 2017
    Inventor: Xi Chu
  • Patent number: 9663862
    Abstract: A method of smoothing a solid surface with a gas cluster ion beam includes irradiating the solid surface with the gas cluster ion beam. The irradiating includes, when scratches which can be likened to a line-and-space pattern structure with widths and heights on the order of a submicrometer to micrometer are present on the solid surface, a process of emitting the gas cluster ion beam so as to expose substances, which remain on side-walls of the scratches due to lateral transferal caused by collisions with gas clusters, to other gas clusters, and the gas cluster ion beam diverges non-concentrically and/or non-uniformly.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 30, 2017
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Akinobu Sato, Akiko Suzuki, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki
  • Patent number: 9583339
    Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: February 28, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS-Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc.
    Inventors: Nicolas Posseme, Thibaut David, Olivier Joubert, Thorsten Lill, Srinivas Nemani, Laurent Vallier
  • Patent number: 9570306
    Abstract: The present application aims to provide a surface treatment method that is able to accurately control the rate of etching a single crystal SiC substrate and thereby enables correct understanding of the amount of etching. In the surface treatment method, the single crystal SiC substrate is etched by a heat treatment performed under Si vapor pressure. At a time of the etching, inert gas pressure in an atmosphere around the single crystal SiC substrate is adjusted to control the rate of etching. Accordingly, correct understanding of the amount of etching is obtained.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 14, 2017
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Satoshi Torimi, Norihito Yabuki, Satoru Nogami
  • Patent number: 9558928
    Abstract: Method and apparatus for cleaning a substrate having a plurality of high-aspect ratio openings are disclosed. A substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures having alternating layers of oxide and nitride or alternating layers of oxide and polysilicon. The substrate can include a silicon oxide layer over a damaged or amorphous silicon layer in the high-aspect ratio openings. To remove the silicon oxide layer, a bias power can be applied in the plasma processing chamber at a low pressure, and a fluorine-based species can be used to etch the silicon oxide layer. To remove the underlying damaged or amorphous silicon layer, a source power and a bias power can be applied in the plasma processing chamber, and a hydrogen-based species can be used to etch the damaged or amorphous silicon layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: January 31, 2017
    Assignee: Lam Research Corporation
    Inventors: Bayu Thedjoisworo, Helen Zhu, Linda Marquez, Joon Park
  • Patent number: 9548185
    Abstract: A cross section processing method and a cross section processing apparatus are provided in which it is possible to form a flat cross section in a sample composed of a plurality of substances having different hardness by a focused ion beam. The etching of a processing area is performed while variably controlling the irradiation interval, the irradiation time, or the like of a focused ion beam based on cross section information of an SEM image obtained by the observation of a cross section. In this way, even if a sample is composed of a plurality of substances having different hardness, it is possible to form a flat observation surface with a uniform etching rate.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 17, 2017
    Assignee: HITACHI HIGH-TECH SCIENCE CORPORATION
    Inventors: Hidekazu Suzuki, Tatsuya Asahata, Atsushi Uemoto
  • Patent number: 9449840
    Abstract: A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends fro
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 20, 2016
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Jong Cheon Park, Jung Gun Heo, Hong Ik Kim, Cheol Kyu Bok
  • Patent number: 9378970
    Abstract: A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one reactive gas to form a reactive gas plasma, which forms, together with the layer to be etched, a reactive layer which goes into the layer to be etched during etching of said layer to be etched, wherein the reactive layer reaches a steady state thickness upon completion of a determined duration of said injection; said injection being interrupted before said determined duration has elapsed so that, upon completion of the forming of the reactive layer, the thickness of the reactive layer is smaller than said steady state thickness; and removing the reactive layer by injection of at least one inert gas to form an inert gas plasma, which makes it possible to remove only the reactive layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 28, 2016
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS Centre National de la Recherche Scientifique
    Inventors: Olivier Joubert, Gilles Cunge, Emilie Despiau-Pujo, Erwine Pargon, Nicolas Posseme
  • Patent number: 9362131
    Abstract: An etch process gas is provided to a main process chamber having an electron beam plasma source, and during periodic passivation operations a remote plasma source provides passivation species to the main process chamber while ion energy is limited below an etch ion energy threshold. During periodic etch operations, flow from the remote plasma source is halted and ion energy is set above the etch threshold.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 7, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ankur Agarwal, Shahid Rauf, Kartik Ramaswamy
  • Patent number: 9259758
    Abstract: A substrate treatment method is provided, which includes: a liquid film forming step of forming a liquid film of a treatment liquid on a front surface of a substrate; a hydrophobization liquid supplying step of supplying a hydrophobization liquid to a center portion of the front surface of the substrate for hydrophobizing the front surface of the substrate, while rotating the substrate; an inactivation suppressing step of suppressing inactivation of the supplied hydrophobization liquid on a peripheral edge portion of the front surface of the substrate simultaneously with the hydrophobization liquid supplying step; and a drying step of drying the substrate to which the hydrophobization liquid has been supplied.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 16, 2016
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Tetsuya Emoto, Manabu Okutani
  • Patent number: 9228259
    Abstract: A method for treating a deposition reactor is disclosed. The method removes or mitigates formation of residue in a gas-phase reactor used to deposit doped metal films, such as aluminum-doped titanium carbide films or aluminum-doped tantalum carbide films. The method includes a step of exposing a reaction chamber to a treatment reactant that mitigates formation of species that lead to residue formation.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 5, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi Haukka, Eric James Shero, Fred Alokozai, Dong Li, Jereld Lee Winkler, Xichong Chen
  • Patent number: 9196460
    Abstract: A ratio between gas conductances of a main gas passage and a plurality of branch gas passages is increased. A plasma processing apparatus is an apparatus for plasma-processing an object to be processed by exciting gas, and includes a processing container; a gas supply source for supplying a desired gas; a main gas passage distributing the gas supplied from the gas supply source; a plurality of branch gas passages connected to a lower stream side of the main gas passage; a plurality of throttle portions formed on the plurality of branch gas passages to narrow the branch gas passages; and one, two, or more gas discharging holes per each of the branch gas passages, for discharging the gas that has passed through the plurality of throttle portions formed on the plurality of branch gas passages into the processing container.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 24, 2015
    Assignees: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Masaki Hirayama, Tadahiro Ohmi
  • Patent number: 9184044
    Abstract: A method for manufacturing a semiconductor device is provided with filling a trench by supplying trichlorosilane gas to a substrate where the trench is formed. A relation between a gas concentration of trichlorosilane gas and a film formation speed includes a concentration countergradient condition in which the film formation speed decreases as the gas concentration increases. The filling of the trench is performed under the concentration countergradient condition.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: November 10, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takayuki Koyama, Takanori Yamamoto, Kenji Nakashima, Takahiro Kozawa
  • Patent number: 9053987
    Abstract: A manufacturing method of a display device includes: forming a thin film transistor on a substrate, forming a pixel electrode connected to the thin film transistor, and forming a common electrode insulated from the pixel electrode. At least one of forming the pixel electrode and forming the common electrode includes: forming an electrode layer on the substrate, coating a photoresist on the electrode layer to form a first electrode sub-layer on which the photoresist is coated and a second electrode sub-layer on which the photoresist is not coated, generating etching vapor by heating an etching solution in a double boiler, and etching the second electrode sub-layer by using the etching vapor.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 9, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hongsick Park, Seon-il Kim
  • Patent number: 9054340
    Abstract: A flexible display device includes: a display panel including a display substrate, an organic light emitting element formed on the display substrate, and a thin film encapsulation layer covering the organic light emitting element; a first insulation layer formed under the display panel; a lower protection film formed under the first insulation layer; and a reinforcement layer formed under the lower protection film, between the lower protection film and the first insulation layer, or on the display panel, wherein the reinforcement layer is configured to prevent damage to the display panel due to bending stress.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 9, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyun-Chel Kim
  • Publication number: 20150147523
    Abstract: A hydrophobic surface comprises a surface texture and a coating disposed on the surface texture, wherein the coating comprises an amorphous diamond like carbon material doped with 10 to 35 atomic percent of Si, O, F, or a combination comprising at least one of the foregoing, or a low surface energy material selected from fluoropolymer, silicone, ceramic, fluoropolymer composite, or a combination comprising at least one of the foregoing; and wherein the surface texture comprises a micro texture, a micro-nano texture, or a combination of a micro texture and a micro-nano texture.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: BAKER HUGHES INCORPORATED
    Inventors: Deepak Kumar, Zhiyue Xu
  • Publication number: 20150136732
    Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: Xianmin TANG, Ludovic GODET, Guojun LIU, Jing TANG, Phillip STOUT, Rong TAO
  • Publication number: 20150132212
    Abstract: Methods of forming carbon films, structures and devices including the carbon films, and systems for forming the carbon films are disclosed. A method includes depositing a metal carbide film using atomic layer deposition (ALD). Metal from the metal carbide film is removed from the metal carbide film to form a carbon film. Because the films are formed using ALD, the films can be relatively conformal and can have relatively uniform thickness over the surface of a substrate.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: ASM IP Holding B.V.
    Inventor: Jereld Lee Winkler
  • Patent number: 9029264
    Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9023734
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Ching-Mei Hsu, Seung Park, Anchuan Wang, Nitin K. Ingle
  • Patent number: RE47650
    Abstract: A method for etching a tungsten containing layer in an etch chamber is provided. A substrate is placed with a tungsten containing layer in the etch chamber. A plurality of cycles is provided. Each cycle comprises a passivation phase for forming a passivation layer on sidewalls and bottoms of features in the tungsten containing layer. Additionally, each cycle comprises an etch phase for etching features in the tungsten containing layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Lam Research Corporation
    Inventors: Ramkumar Subramanian, Anne Le Gouil, Yoko Yamaguchi