Etching And Coating Occur In The Same Processing Chamber Patents (Class 216/37)
  • Patent number: 8916479
    Abstract: Provided are methods for processing semiconductor substrates having titanium nitride (TiN) structures as well as aluminum (Al) structures and, in some embodiments, other structures, such as silicon germanium (SiGe), tantalum nitride (TaN), hafnium oxide (HfOx), silicon nitride (SiN), and/or silicon oxide (SiO2) structures. Etching solutions and processing conditions described herein provide high etching selectivity of titanium nitride relative to these other materials. As such, the titanium nitride structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching rate of titanium nitride is at least about 200 Angstroms per minute and even at least about 350 Angstroms per minute, while the etching rate of aluminum and/or other materials is less than 15 Angstroms per minute. An etching solution may be kept at 40° C. to 65° C. and may include ammonium hydroxide and hydrogen peroxide (between 1:600 and 1:3,000 by weight).
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 23, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Gregory Nowling
  • Patent number: 8916477
    Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 23, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
  • Patent number: 8904628
    Abstract: Disclosed herein is a method of manufacturing a noise removing filter, including preparing at least one conductive pattern, an insulating layer for covering the at least one conductive pattern, and a lower magnetic body including input/output stud terminals for electrically inputting and outputting electricity to and from the at least one conductive pattern; disposing a recognizable portion on upper surfaces of the input/output stud terminals; disposing an upper magnetic body on the recognizable portion and the insulating layer; polishing the upper magnetic body; and removing the recognizable portion such that a level of an upper surface of the upper magnetic body is higher than levels of the upper surfaces of the input/output stud terminals.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Moon Lee, Sung Kwon Wi, Jeong Bok Kwak, Won Chul Sim, Young Seuck Yoo, Yong Suk Kim
  • Patent number: 8906246
    Abstract: A film deposition method includes steps of transferring a substrate having a pattern including a concave part into a vacuum chamber; supplying a first reaction gas to the substrate from a first reaction gas supplying part, thereby allowing the first reaction gas to be adsorbed on the substrate; supplying a second reaction gas that reacts with the first reaction gas to the substrate from a second reaction gas supplying part, thereby allowing the first reaction gas adsorbed on the substrate to react with the second reaction gas and forming a reaction product of the first and the second reaction gases on the substrate; supplying an alteration gas to the substrate through an activated gas supplying part capable of activating the alteration gas; and supplying an etching gas to the substrate chamber through the activated gas supplying part under an environment where the reaction product is not formed.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: December 9, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Takeshi Kumagai
  • Patent number: 8900471
    Abstract: Methods and apparatus for in-situ plasma cleaning of a deposition chamber are provided. In one embodiment a method for plasma cleaning a deposition chamber without breaking vacuum is provided. The method comprises positioning a substrate on a susceptor disposed in the chamber and circumscribed by an electrically floating deposition ring, depositing a metal film on the substrate and the deposition ring in the chamber, grounding the metal film deposited on the deposition ring without breaking vacuum, and removing contaminants from the chamber with a plasma formed in the chamber without resputtering the metal film on the grounded deposition ring and without breaking vacuum.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Richard J. Green, Cheng-hsiung Tsai, Shambhu N. Roy, Puneet Bajaj, David H. Loo
  • Publication number: 20140347661
    Abstract: An apparatus for filtering species in a fluid includes a body having a first side and a second side, a first set of nano-fingers positioned on the body near the first side, a second set of nano-fingers positioned on the body closer to the second side than the first set of nano-fingers, wherein the nano-fingers in the second set of nano-fingers are arranged on the body at a relatively more densely than the nano-fingers in the first set of nano-fingers, and a cover positioned over the first set of nano-fingers and the second set of nano-fingers to form a channel with the body within which the first and second sets of nano-fingers are positioned.
    Type: Application
    Filed: October 27, 2011
    Publication date: November 27, 2014
    Inventors: Ansoon Kim, Zhiyong Li, Wei Wu
  • Patent number: 8895444
    Abstract: An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Michael D. Wedlake
  • Publication number: 20140342441
    Abstract: The present invention provides, among others, apparatus for detecting a disease, comprising a system delivery biological subject and a probing and detecting device, wherein the probing and detecting device includes a first micro-device and a first substrate supporting the first micro-device, the first micro-device contacts a biologic material to be detected and is capable of measuring at the microscopic level an electric, magnetic, electromagnetic, thermal, optical, acoustical, biological, chemical, physical, or mechanical property of the biologic material.
    Type: Application
    Filed: April 4, 2013
    Publication date: November 20, 2014
    Applicant: ANPAC BIO-MEDICAL SCIENCE CO., LTD.
    Inventors: Chris C. Yu, Xuedong Du, He Yu
  • Patent number: 8889022
    Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hans-Peter Moll, Joachim Patzer
  • Patent number: 8889025
    Abstract: This disclosure relates to a method for manufacturing a semiconductor device. The method includes etching a metal film on a semiconductor substrate with an etching composition; and rinsing the etched metal film with a rinse solvent. The etching composition includes at least one acid; at least one compound containing a halide anion, the halide anion being chloride or bromide; at least one compound containing a nitrate or nitrosyl ion; and water.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 18, 2014
    Assignees: Fujifilm Electronic Materials U.S.A., Inc., FujiFilm Corporation
    Inventors: Tomonori Takahashi, Tadashi Inaba, Atsushi Mizutani, Bing Du, William A. Wojtczak, Kazutaka Takahashi, Tetsuya Kamimura
  • Patent number: 8883023
    Abstract: A method for forming a pattern includes providing a composition to form a resist underlayer film on a surface of a substrate to be processed. The composition contains a calixarene based compound having a group represented by a following formula (i) bound to at least a part of an aromatic ring or at least a part of a heteroaromatic ring of the calixarene based compound. The resist underlayer film on the surface of the substrate is treated with heat or an acid. A resist pattern is formed on a surface of the resist underlayer film. The resist underlayer film and the substrate are etched using the resist pattern as a mask to form the pattern on the substrate. The dry-etched resist underlayer film is removed from the substrate with a basic solution.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 11, 2014
    Assignee: JSR Corporation
    Inventors: Goji Wakamatsu, Hayato Namai, Syun Aoki
  • Patent number: 8883022
    Abstract: Provided is a mask blank which is used for manufacturing an imprinting mold and which may form a fine mold pattern with high pattern accuracy. A mask blank (10) includes a transparent substrate (1) and a thin film (2) contacted with a surface of the substrate. The thin film (2) includes a laminated film including an upper layer (4) which is composed of a material containing silicon (Si) or a material containing tantalum (Ta), and a lower layer (3) which is composed of a material containing at least one of hafnium (Hf) and zirconium (Zr) and containing substantially no oxygen.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: November 11, 2014
    Assignee: Hoya Corporation
    Inventors: Osamu Nozawa, Masahiro Hashimoto
  • Patent number: 8883026
    Abstract: A substrate processing method includes a water removing step of removing water from a substrate, a silylating step of supplying a silylating agent to the substrate after the water removing step, and an etching step of supplying an etching agent to the substrate after the silylating step. The substrate may have a surface on which a nitride film and an oxide film are exposed and in this case, the etching step may be a selective etching step of selectively etching the nitride film by the etching agent. The etching agent may be supplied in a form of a vapor having an etching component.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 11, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takashi Ota, Yuya Akanishi, Akio Hashizume
  • Patent number: 8883642
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakana Kai, Tomonori Aoyama
  • Publication number: 20140326700
    Abstract: The invention concerns a method of forming a graphene layer involving: heating a support layer in a reaction chamber; and forming the graphene layer on a surface of the support layer by: a) during a first time period, introducing into the reaction chamber an organic compound gas to cause a formation of carbon atoms on the surface; b) during a second time period after the first time period, reducing a rate of introduction of the organic compound gas into the reaction chamber and introducing into the reaction chamber a further gas, wherein the further gas is a carbon etching gas; and repeating a) and b) one or more times.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTFIQUE
    Inventors: Vincent BOUCHIAT, Johann CORAUX, Zheng HAN
  • Patent number: 8877641
    Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 4, 2014
    Assignee: Spansion LLC
    Inventor: Calvin T Gabriel
  • Patent number: 8877650
    Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 4, 2014
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: O Seo Park, Wai-Kin Li
  • Patent number: 8877000
    Abstract: A plasma-processing chamber including pulsed gas injection orifices/nozzles utilized in combination with continuous flow shower head injection orifices is described. The continuous flow shower head injection orifices introduce a continuous flow of gas while the pulsed gas injection orifices/nozzles cyclically inject a high-pressure gas into the chamber. In one embodiment, a central computer may monitor and control pressure measurement devices and utilize the measurements to adjust processing parameters (e.g. pulse duration, pulse repetition rate, and the pulse mass flow rate of processing gases).
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: November 4, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Eric J. Strang
  • Patent number: 8877082
    Abstract: Disclosed is a processing method which can achieve a high processing rate, and is capable of making a surface smooth. In order to achieve this an SiC substrate is arranged in a potassium hydroxide solution containing hydrogen peroxide, and ultraviolent radiation is irradiated on the surface of the SiC substrate. An SiO2 layer is formed on the surface of the SiC substrate due to the irradiation of ultraviolet radiation, and this SiO2 layer is chemically removed by means of the potassium hydroxide solution, and also removed by a synthetic quartz surface plate.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 4, 2014
    Assignee: National University Corporation Kumamoto University
    Inventors: Akihisa Kubota, Mutsumi Touge
  • Patent number: 8871650
    Abstract: Post etch treatments (PETs) of low-k dielectric films are described. For example, a method of patterning a low-k dielectric film includes etching a low-k dielectric layer disposed above a substrate with a first plasma process. The etching involves forming a fluorocarbon polymer on the low-k dielectric layer. The low-k dielectric layer is surface-conditioned with a second plasma process. The surface-conditioning removes the fluorocarbon polymer and forms an Si—O-containing protecting layer on the low-k dielectric layer. The Si—O-containing protecting layer is removed with a third plasma process.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Nicolas J. Bright, Thorsten B. Lill, Yifeng Zhou, Jamie Saephan, Ellie Yieh
  • Patent number: 8858812
    Abstract: Provided is a processing method for an ink jet head substrate, including: forming a barrier layer on a substrate and forming a seed layer on the barrier layer; forming a resist film on the seed layer and patterning the resist film so that the patterned resist film corresponds to a pad portion for electrically connecting an ink jet head to an outside of the ink jet head; forming the pad portion in an opening of the patterned resist film; removing the resist film; subjecting the substrate to anisotropic etching to form an ink supply port; removing the barrier layer and the seed layer; and performing laser processing from a surface of the substrate.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenta Furusawa, Keiji Matsumoto, Keisuke Kishimoto, Kazuhiro Asai, Shuji Koyama
  • Patent number: 8858813
    Abstract: A patterning process comprises (a) providing at least one substrate having at least one major surface; (b) providing at least one patterning composition comprising at least one functionalizing molecule that is a perfluoropolyether organosulfur compound; (c) applying the patterning composition to the major surface of the substrate in a manner so as to form at least one functionalized region and at least one unfunctionalized region of the major surface; and (d) etching at least a portion of the unfunctionalized region.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: October 14, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Lijun Zu, Matthew H. Frey, Suresh S. Iyer
  • Patent number: 8858819
    Abstract: The titled method affords low dishing levels in the polished substrate while simultaneously affording high metal removal rates. The method utilizes an associated polishing composition. Components in the composition include a poly(alkyleneimine) such as polyethyleneimine, an abrasive, an acid, and an oxidizing agent, such as a per-compound.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Rachel Dianne McConnell, Ann Marie Hurst, Xiaobo Shi
  • Patent number: 8859434
    Abstract: The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C, SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 14, 2014
    Assignee: SPP Technologies Co., Ltd.
    Inventors: Akimitsu Oishi, Shoichi Murakami
  • Patent number: 8853081
    Abstract: Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Olov Karlsson, Sven Metzger
  • Publication number: 20140295128
    Abstract: A hard, wear resistant coating and a method of forming the coating on a substrate to be exposed to hydrocarbons is provided. A substrate is provided in a chamber. A film is deposited onto the substrate by physical vapor deposition (PVD), where the film includes a bulk layer and an outer termination layer. The deposition of the termination layer is mitigated. The termination layer is removed from the film, leaving the remaining bulk layer disposed over the substrate. And when the substrate is exposed to hydrocarbons in an environment having wear additives, friction modifiers, or naturally occurring compounds, a durable tribological layer is formed on an outer surface of the bulk layer to create a coating having low friction and anti-wear properties.
    Type: Application
    Filed: December 8, 2010
    Publication date: October 2, 2014
    Applicant: GALLEON INTERNATIONAL CORPORATION
    Inventors: Frank Sykora, Ali Erdemir, Mustafa Urgen, Osman Levent Eryilmaz
  • Publication number: 20140291286
    Abstract: A shower head includes a gas injection plate and a gas supply unit. The gas supply unit has a first gas supply path provided in a region along the axis and a second gas supply path provided in a region surrounding the region where the first gas supply path is provided. The first gas supply path has a first gas diffusion space connected to a first gas line of the gas supply unit, second gas lines, a second gas diffusion space, third gas lines and a third gas diffusion space which are connected in that order. The second gas supply path has a fourth gas diffusion space connected to a fourth gas line of the gas supply unit, fifth gas lines, a fifth gas diffusion space, sixth gas lines, and a sixth gas diffusion space which are connected in that order.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Nobuyuki OKAYAMA, Koichi KAZAMA, Shuichiro UDA, Satoshi YAMADA, Shinji FUCHIGAMI
  • Patent number: 8845915
    Abstract: A polishing agent which comprises a composition containing an inorganic acid, an amino acid, a protective film-forming agent, an abrasive, an oxidizing agent, an organic acid and water, adjusted to a pH of 1.5-4, wherein the amount of potassium hydroxide required to raise the pH of the composition without the organic acid to 4 is at least 0.10 mol with respect to 1 kg of the composition without the organic acid, and the organic acid contains at least two carboxyl groups, wherein the logarithm of the inverse of the first acid dissociation constant (pKa1) is no greater than 3.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: September 30, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Hiroshi Ono, Takashi Shinoda, Yuuhei Okada
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Publication number: 20140263169
    Abstract: In some embodiments, a method for processing a substrate in a process chamber having a substrate support configured to move in a direction perpendicular to a top surface of a cover ring of a process kit may include positioning the substrate support in a first position such that a top surface of the substrate is positioned about 3 mm above to about 10 mm below a top surface of a cover ring of a process kit disposed about the periphery of the substrate support; performing a plasma deposition process while the substrate support is in the first position; moving the substrate support to a second position such that the top surface of the substrate is disposed about 3 mm below to about 15 mm above the top surface of the cover ring; and performing a plasma etch process while the substrate support is in the second position.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: JOUNG JOO LEE, WILLIAM JOHANSON, KEITH A. MILLER, ALAN A. RITCHIE
  • Patent number: 8835320
    Abstract: An etching method can prevent adverse effects of oxygen plasma from arising under an insulating film when etching the insulating film formed on a substrate. The etching method includes: a first etching step for exposing the insulating film to processing gas that has been turned into a plasma to etch the insulating film to a portion in the thickness direction; a deposition material removing step for exposing the insulating film remaining after completion of the first etching to oxygen plasma to remove deposition material deposited on the surface of the remaining insulating film; and a second etching of exposing the remaining insulating film to processing gas that has been turned into a plasma to etch the remaining insulating film.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: September 16, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Toshihisa Ozu
  • Patent number: 8828254
    Abstract: A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 9, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yoshiharu Inoue, Tetsuo Ono, Michikazu Morimoto, Masaki Fujii, Masakazu Miyaji
  • Patent number: 8828259
    Abstract: A method for automatically performing power matching using a mechanical RF match during substrate processing is provided. The method includes providing a plurality of parameters for the substrate processing wherein the plurality of parameters including at least a predefined number of learning cycles. The method also includes setting the mechanical RF match to operate in a mechanical tuning mode. The method further includes providing a first set of instructions to the substrate processing to ignore a predefined number of cycles of Rapid Alternating Process RAP steps. The method yet also includes operating the mechanical RF match in the mechanical tuning mode for the predefined number of learning cycles. The method yet further includes determining a set of optimal capacitor values. The method moreover includes providing a second set of instructions to a power generator to operate in a frequency tuning mode.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventor: Arthur H. Sato
  • Patent number: 8821746
    Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryota Kojima
  • Patent number: 8821752
    Abstract: The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 2, 2014
    Assignees: SK Hynix Inc., Soulbrain Co., Ltd.
    Inventors: Sung-Hyuk Cho, Kwon Hong, Hyung-Soon Park, Gyu-Hyun Kim, Ji-Hye Han, Jung-Hun Lim, Jin-Uk Lee, Jae-Wan Park, Chan-Keun Jung
  • Patent number: 8821682
    Abstract: Systems and methods of imaging and repairing defects on and below the surface of an integrated circuit (IC) are described. The method may be used in areas as small as one micron in diameter, and may remove the topmost material in the small spot, repeating with various layers, until a desired depth is obtained. An energetic beam, such as an electron beam, is directed at a selected surface location. The surface has an added layer of a solid, fluid or gaseous reactive material, such as a directed stream of a fluorocarbon, and the energetic beam disassociates the reactive material in the region of the beam into radicals that chemically attack the surface. After the defect location is exposed, the method uses the energetic beam to etch undesired materials, and deposit various appropriate materials to fill gaps, and restore the IC to an operational condition.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark J. Williamson, Gurtej S. Sandhu, Justin R. Arrington
  • Patent number: 8821741
    Abstract: A preprocess step for supplying an inert gas into an enclosed space in which a substrate is disposed, while exhausting gas by sucking out of the enclosed space. And then, an etching step for supplying a process vapor into the enclosed space while exhausting gas out of the enclosed space at an rate lower than a rate in the preprocess step. And then a post-process step for supplying an inert gas into the enclosed space while exhausting gas by sucking out of the enclosed space at a rate higher than the rate in the etching step.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Takashi Ota, Akio Hashizume, Takahiro Yamaguchi, Yuya Akanishi
  • Patent number: 8815102
    Abstract: A method for fabricating a patterned dichroic film is provided, wherein the method comprises steps as follows: A patterned material layer comprising at least one inorganic layer is firstly provided on a substrate. A film deposition process is then performed to form a dichroic film on the patterned material layer and the substrate. The patterned material layer is subsequently removed, whereby a portion of the dichroic film disposed on the patterned material layer can be removed simultaneously.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corporation
    Inventor: Yi-Tyng Wu
  • Patent number: 8808564
    Abstract: Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, a method for removing native oxides from a substrate is provided. The method includes transferring a substrate having an oxide layer disposed thereon into a first processing chamber, exposing the substrate to a plasma generated from a cleaning gas mixture, wherein the cleaning gas mixture comprises a hydrogen-containing gas and a fluorine-containing gas, heating the substrate to a temperature sufficient to remove the oxide layer from the substrate, transferring the substrate from the first processing chamber to a second processing chamber without breaking vacuum, and flowing a plasma containing substantially nitrogen-containing radicals into the second processing chamber to expose the substrate to nitrogen containing radicals.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Matthew S. Rogers, Christopher S. Olsen
  • Patent number: 8801943
    Abstract: The present disclosure describes a method for manufacturing a full wraparound shield damascene write head through the implementation of a three layered (tri-layered) hard mask. According to an embodiment of the invention, the various layers of hard mask are used for different purposes during the formation of a write head. The wraparound shield head of the present invention exhibits improved physical characteristics that further result in improved performance characteristics. Use of the hard mask layers according to the present invention allows for use of manufacturing processes that can be more closely controlled than those processes used in other processes. For example, smaller dimension lithographic techniques can be used. Also, reliance on certain CMP processes is not necessary where the use of CMP processes is not as well-controlled as deposition or lithographic techniques as is possible using the present invention.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: August 12, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Shiwen Huang, Fenglin Liu, Qiping Zhong, Kyusik Shin, Yingjian Chen
  • Patent number: 8801951
    Abstract: In a plasma processing method for conducting etching on an object to be processed by generating plasma from depositional gas introduced into a processing chamber and exposing the object to be processed to the plasma in a state in which radio frequency power is applied, the object to be processed is etched under etching conditions that a deposit film on an inner wall of the processing chamber becomes amorphous by repeating a first period during which the object to be processed is exposed to plasma and a second period during which the object to be processed is exposed to plasma and an etching rate is lower as compared with the first period. Consequently, particles due to increase in the number of processed sheets of the object to be processed can be suppressed.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yoshiharu Inoue, Michikazu Morimoto, Tsuyoshi Matsumoto, Tetsuo Ono, Tadamitsu Kanekiyo, Mamoru Yakushiji, Masakazu Miyaji
  • Patent number: 8795539
    Abstract: A method of forming patterns includes forming a layer composed of a ketene based random copolymer on a substrate, forming a block copolymer on the ketene based random copolymer layer and patterning the ketene based random copolymer layer by removing a part of the block copolymer and a portion of the ketene based random copolymer layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 5, 2014
    Assignees: Samsung Display Co., Ltd., Korea University Research and Business Foundation
    Inventors: Su Mi Lee, Mio Hyuck Kang, Eun-Ae Kwak, Moon Gyu Lee, Bong-Jin Moon, Joona Bang, Hyun Jung Jung
  • Patent number: 8790536
    Abstract: Disclosed is a metal etching method, a metal etching control method and a control device thereof. The metal etching control method is employed in a metal wet etching machine and comprises steps below: performing etching to a metal film and acquiring an etching end time of the metal film; multiplying the etching end time with a constant ratio to acquire the over etching time of the metal film; and performing etching to the metal film with the over etching time to complete the etching to the metal film. The present invention can precisely judge a total real etching time needed for each of a batch of metal films as performing metal etching to the metal films to reduce the issue of unstable etching qualities as the metal film thicknesses are not regular.
    Type: Grant
    Filed: August 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Chin-wen Wang, Chengming He
  • Patent number: 8784676
    Abstract: A method for reducing contamination in an etch chamber is provided. A substrate with a metal containing layer is placed in the etch chamber. The metal containing layer is etched, producing nonvolatile metal residue deposits on surfaces of the etch chamber, wherein some of the metal residue of the metal residue deposits is in a first state. The substrate is removed from the etch chamber. The chamber is conditioned by converting metal residue in the first state to metal residue in a second state, where metal residue in the second state has stronger adhesion to surfaces of the etch chamber than metal residue in the first state.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sanket Sant, Butsurin Jinnai
  • Patent number: 8784673
    Abstract: Methods for fabricating templates for nanoelement assembly and methods for fluid-guided assembly of nanoelements are provided. Templates are fabricated by plasma modification of surface hydrophilicity and production of a network of hydrophobic trenches having a hydrophilic bottom surface. Single-walled carbon nanotubes (SWNT) can be assembled into stable films, ribbons, and wires of nanoscale thickness and nanoscale or microscale width and length. The nanofilm assemblies prepared according to the invention are highly conductive and can be used in the fabrication of a wide variety of microscale and nanoscale electronic devices.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: July 22, 2014
    Assignee: Northeastern University
    Inventors: Xugang Xiong, Laila Jaberansari, Ahmed Busnaina, Yung Joon Jung, Sivasubramanian Somu, Moneesh Upmanyu
  • Publication number: 20140196933
    Abstract: Fabrication of thin sheets of glass or other substrate material for use in devices such as touch sensor panels is disclosed. A pair of thick glass sheets, typically with thicknesses of 0.5 mm or greater each, may each be patterned with thin film on a surface, sealed together to form a sandwich with the patterned surfaces facing each other and spaced apart by removable spacers, either or both thinned on their outside surfaces to thicknesses of less than 0.5 mm each, and separated into two thin glass sheets. A single thick glass sheet, typically with a thickness of 0.5 mm or greater, may be patterned, covered with a protective layer over the pattern, thinned on its outside surface to a thickness of less than 0.5 mm, and the protective layer removed. This thinness of less than 0.5 mm may be accomplished using standard LCD equipment, despite the equipment having a sheet minimum thickness requirement of 0.5 mm.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: Apple Inc.
    Inventors: Casey J. Feinstein, John Z. Zhong, Steve Porter Hotelling, Shih Chang Chang
  • Publication number: 20140193743
    Abstract: A ceramic layer, especially for use in solid oxide cell (SOC) technology, is densified in a method comprising (a) providing a multilayer system by depositing the porous ceramic layer, which is to be densified, onto the selected system of ceramic layers on a support, (b) pre-sintering the resulting multilayer system at a temperature T1 to consolidate a sintered, but porous layer, (c) impregnating a solution or suspension of one or more sintering aids directly into the layer to be densified, (d) evaporating the solution or suspension of step (c) to obtain a homogeneous dispersion of the sintering aid(s) in the porous layer surface and (e) performing a thermal treatment at a temperature T2, where T2>T1, to obtain densification of and grain growth in the porous layer formed in step (b). The method makes it possible to obtain dense ceramic layers at temperatures, which are compatible with the other materials present in a ceramic multilayer system.
    Type: Application
    Filed: July 20, 2012
    Publication date: July 10, 2014
    Applicant: DANMARKS TEKNISKE UNIVERSITET
    Inventor: Vincenzo Esposito
  • Publication number: 20140190934
    Abstract: A method and apparatus is provided for preparing samples for observation in a charged particle beam system in a manner that reduces or prevents artifacts. Material is deposited onto the sample using charged particle beam deposition just before or during the final milling, which results in an artifact-free surface. Embodiments are useful for preparing cross sections for SEM observation of samples having layers of materials of different hardnesses. Embodiments are useful for preparation of thin TEM samples.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 10, 2014
    Inventors: Michael Schmidt, Jeffrey Blackwood, Stacey Stone, Sang Hoon Lee, Ronald Kelley
  • Patent number: 8772172
    Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8770143
    Abstract: The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: July 8, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Rick Endo, Kurt Weiner, Indranil De, James Tsung, Maosheng Zhao