Etching And Coating Occur In The Same Processing Chamber Patents (Class 216/37)
  • Patent number: 9818640
    Abstract: A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jason Eugene Stephens, Guillaume Bouche
  • Patent number: 9793136
    Abstract: A plasma etching method can form a hole having a required opening diameter in a silicon nitride layer, while suppressing a tip end portion of the hole from being narrowed. The plasma etching method includes a first process of supplying a processing gas containing oxygen and fluorocarbon into a plasma processing apparatus; and a second process of etching a silicon nitride layer 106a of a processing target object with a first mask 106 by exciting the processing gas into plasma. Further, the second process is performed in a state where an organic film ad generated from the processing gas is formed on an inner wall of an opening of the first mask 106 by gradually reducing a temperature of the processing target object from a first temperature T1 (80° C.) to a second temperature T2 (40° C.).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 17, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kosei Ueda, Yoshinobu Hayakawa
  • Patent number: 9786503
    Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 10, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique D. Raley, Nihar Mohanty, Akiteru Ko
  • Patent number: 9767991
    Abstract: For a first period of time, a higher radiofrequency power is applied to generate a plasma in exposure to a substrate, while applying low bias voltage at the substrate level. For a second period of time, a lower radiofrequency power is applied to generate the plasma, while applying high bias voltage at the substrate level. The first and second periods of time are repeated in an alternating and successive manner for an overall period of time necessary to produce a desired effect on the substrate. In some embodiments, the first period of time is shorter than the second period of time such that on a time-averaged basis the plasma has a greater ion density than radical density. In some embodiments, the first period of time is greater than the second period of time such that on a time-averaged basis the plasma has a lower ion density than radical density.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: September 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu
  • Patent number: 9768033
    Abstract: This disclosure relates to a plasma processing system and methods for high precision etching of microelectronic substrates. The system may include a combination of microwave and radio frequency (RF) power sources that may generate plasma conditions to remove monolayer(s). The system may generation a first plasma to form a thin adsorption layer on the surface of the microelectronic substrate. The adsorbed layer may be removed when the system transition to a second plasma. The differences between the first and second plasma may be include the ion energy proximate to the substrate. For example, the first plasma may have an ion energy of less than 20 eV and the second plasma may have an ion energy greater than 20 eV.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: September 19, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Mingmei Wang, Peter L. G. Ventzek
  • Patent number: 9728421
    Abstract: A method of etching a pattern into a dielectric layer is provided. An organic planarization layer having a pattern is provided atop a dielectric layer. A cyclic fluorocarbon deposition step and plasma step is performed to etch the pattern into the dielectric layer. The energy for the plasma step is kept below the etch threshold of the dielectric layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sebastian U. Engelmann, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9679780
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying NH3 (ammonia) and NF3 (nitrogen trifluoride) or by applying BHF (buffered hydrofluoric acid). The first etching process is RIE (reactive ion etching) and the second etching process involves applying NF3 and H2 (hydrogen gas).
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Nicolas J. Loubet
  • Patent number: 9662625
    Abstract: The present invention provides a reactor and a method for the production of high purity silicon granules. The reactor includes a reactor chamber; and the reaction chamber is equipped with a solid feeding port, auxiliary gas inlet, raw material gas inlet, and exhaust gas export. The reaction chamber is also equipped with an internal gas distributor; a heating unit; an external exhaust gas processing unit connected between a preheating unit and a gas inlet. The reaction chamber is further equipped with a surface finishing unit, a heating unit and a dynamics generating unit. The reaction is through decomposition of silicon-containing gas in densely stacked high purity granular silicon layer reaction bed in relative motion, and to use remaining heat of exhaust gas for reheating. The present invention achieves a large scale, efficient, energy saving, continuous, low cost production of high purity silicon granules.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: May 30, 2017
    Inventor: Xi Chu
  • Patent number: 9663862
    Abstract: A method of smoothing a solid surface with a gas cluster ion beam includes irradiating the solid surface with the gas cluster ion beam. The irradiating includes, when scratches which can be likened to a line-and-space pattern structure with widths and heights on the order of a submicrometer to micrometer are present on the solid surface, a process of emitting the gas cluster ion beam so as to expose substances, which remain on side-walls of the scratches due to lateral transferal caused by collisions with gas clusters, to other gas clusters, and the gas cluster ion beam diverges non-concentrically and/or non-uniformly.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 30, 2017
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Akinobu Sato, Akiko Suzuki, Emmanuel Bourelle, Jiro Matsuo, Toshio Seki
  • Patent number: 9583339
    Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: February 28, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS-Centre National de la Recherche Scientifique, APPLIED MATERIALS, Inc.
    Inventors: Nicolas Posseme, Thibaut David, Olivier Joubert, Thorsten Lill, Srinivas Nemani, Laurent Vallier
  • Patent number: 9570306
    Abstract: The present application aims to provide a surface treatment method that is able to accurately control the rate of etching a single crystal SiC substrate and thereby enables correct understanding of the amount of etching. In the surface treatment method, the single crystal SiC substrate is etched by a heat treatment performed under Si vapor pressure. At a time of the etching, inert gas pressure in an atmosphere around the single crystal SiC substrate is adjusted to control the rate of etching. Accordingly, correct understanding of the amount of etching is obtained.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 14, 2017
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Satoshi Torimi, Norihito Yabuki, Satoru Nogami
  • Patent number: 9558928
    Abstract: Method and apparatus for cleaning a substrate having a plurality of high-aspect ratio openings are disclosed. A substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures having alternating layers of oxide and nitride or alternating layers of oxide and polysilicon. The substrate can include a silicon oxide layer over a damaged or amorphous silicon layer in the high-aspect ratio openings. To remove the silicon oxide layer, a bias power can be applied in the plasma processing chamber at a low pressure, and a fluorine-based species can be used to etch the silicon oxide layer. To remove the underlying damaged or amorphous silicon layer, a source power and a bias power can be applied in the plasma processing chamber, and a hydrogen-based species can be used to etch the damaged or amorphous silicon layer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: January 31, 2017
    Assignee: Lam Research Corporation
    Inventors: Bayu Thedjoisworo, Helen Zhu, Linda Marquez, Joon Park
  • Patent number: 9548185
    Abstract: A cross section processing method and a cross section processing apparatus are provided in which it is possible to form a flat cross section in a sample composed of a plurality of substances having different hardness by a focused ion beam. The etching of a processing area is performed while variably controlling the irradiation interval, the irradiation time, or the like of a focused ion beam based on cross section information of an SEM image obtained by the observation of a cross section. In this way, even if a sample is composed of a plurality of substances having different hardness, it is possible to form a flat observation surface with a uniform etching rate.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 17, 2017
    Assignee: HITACHI HIGH-TECH SCIENCE CORPORATION
    Inventors: Hidekazu Suzuki, Tatsuya Asahata, Atsushi Uemoto
  • Patent number: 9449840
    Abstract: A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends fro
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 20, 2016
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Jong Cheon Park, Jung Gun Heo, Hong Ik Kim, Cheol Kyu Bok
  • Patent number: 9378970
    Abstract: A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one reactive gas to form a reactive gas plasma, which forms, together with the layer to be etched, a reactive layer which goes into the layer to be etched during etching of said layer to be etched, wherein the reactive layer reaches a steady state thickness upon completion of a determined duration of said injection; said injection being interrupted before said determined duration has elapsed so that, upon completion of the forming of the reactive layer, the thickness of the reactive layer is smaller than said steady state thickness; and removing the reactive layer by injection of at least one inert gas to form an inert gas plasma, which makes it possible to remove only the reactive layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 28, 2016
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS Centre National de la Recherche Scientifique
    Inventors: Olivier Joubert, Gilles Cunge, Emilie Despiau-Pujo, Erwine Pargon, Nicolas Posseme
  • Patent number: 9362131
    Abstract: An etch process gas is provided to a main process chamber having an electron beam plasma source, and during periodic passivation operations a remote plasma source provides passivation species to the main process chamber while ion energy is limited below an etch ion energy threshold. During periodic etch operations, flow from the remote plasma source is halted and ion energy is set above the etch threshold.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 7, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ankur Agarwal, Shahid Rauf, Kartik Ramaswamy
  • Patent number: 9259758
    Abstract: A substrate treatment method is provided, which includes: a liquid film forming step of forming a liquid film of a treatment liquid on a front surface of a substrate; a hydrophobization liquid supplying step of supplying a hydrophobization liquid to a center portion of the front surface of the substrate for hydrophobizing the front surface of the substrate, while rotating the substrate; an inactivation suppressing step of suppressing inactivation of the supplied hydrophobization liquid on a peripheral edge portion of the front surface of the substrate simultaneously with the hydrophobization liquid supplying step; and a drying step of drying the substrate to which the hydrophobization liquid has been supplied.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 16, 2016
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Tetsuya Emoto, Manabu Okutani
  • Patent number: 9228259
    Abstract: A method for treating a deposition reactor is disclosed. The method removes or mitigates formation of residue in a gas-phase reactor used to deposit doped metal films, such as aluminum-doped titanium carbide films or aluminum-doped tantalum carbide films. The method includes a step of exposing a reaction chamber to a treatment reactant that mitigates formation of species that lead to residue formation.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 5, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi Haukka, Eric James Shero, Fred Alokozai, Dong Li, Jereld Lee Winkler, Xichong Chen
  • Patent number: 9196460
    Abstract: A ratio between gas conductances of a main gas passage and a plurality of branch gas passages is increased. A plasma processing apparatus is an apparatus for plasma-processing an object to be processed by exciting gas, and includes a processing container; a gas supply source for supplying a desired gas; a main gas passage distributing the gas supplied from the gas supply source; a plurality of branch gas passages connected to a lower stream side of the main gas passage; a plurality of throttle portions formed on the plurality of branch gas passages to narrow the branch gas passages; and one, two, or more gas discharging holes per each of the branch gas passages, for discharging the gas that has passed through the plurality of throttle portions formed on the plurality of branch gas passages into the processing container.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 24, 2015
    Assignees: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Masaki Hirayama, Tadahiro Ohmi
  • Patent number: 9184044
    Abstract: A method for manufacturing a semiconductor device is provided with filling a trench by supplying trichlorosilane gas to a substrate where the trench is formed. A relation between a gas concentration of trichlorosilane gas and a film formation speed includes a concentration countergradient condition in which the film formation speed decreases as the gas concentration increases. The filling of the trench is performed under the concentration countergradient condition.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: November 10, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takayuki Koyama, Takanori Yamamoto, Kenji Nakashima, Takahiro Kozawa
  • Patent number: 9054340
    Abstract: A flexible display device includes: a display panel including a display substrate, an organic light emitting element formed on the display substrate, and a thin film encapsulation layer covering the organic light emitting element; a first insulation layer formed under the display panel; a lower protection film formed under the first insulation layer; and a reinforcement layer formed under the lower protection film, between the lower protection film and the first insulation layer, or on the display panel, wherein the reinforcement layer is configured to prevent damage to the display panel due to bending stress.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 9, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyun-Chel Kim
  • Patent number: 9053987
    Abstract: A manufacturing method of a display device includes: forming a thin film transistor on a substrate, forming a pixel electrode connected to the thin film transistor, and forming a common electrode insulated from the pixel electrode. At least one of forming the pixel electrode and forming the common electrode includes: forming an electrode layer on the substrate, coating a photoresist on the electrode layer to form a first electrode sub-layer on which the photoresist is coated and a second electrode sub-layer on which the photoresist is not coated, generating etching vapor by heating an etching solution in a double boiler, and etching the second electrode sub-layer by using the etching vapor.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 9, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hongsick Park, Seon-il Kim
  • Publication number: 20150147523
    Abstract: A hydrophobic surface comprises a surface texture and a coating disposed on the surface texture, wherein the coating comprises an amorphous diamond like carbon material doped with 10 to 35 atomic percent of Si, O, F, or a combination comprising at least one of the foregoing, or a low surface energy material selected from fluoropolymer, silicone, ceramic, fluoropolymer composite, or a combination comprising at least one of the foregoing; and wherein the surface texture comprises a micro texture, a micro-nano texture, or a combination of a micro texture and a micro-nano texture.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: BAKER HUGHES INCORPORATED
    Inventors: Deepak Kumar, Zhiyue Xu
  • Publication number: 20150136732
    Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: Xianmin TANG, Ludovic GODET, Guojun LIU, Jing TANG, Phillip STOUT, Rong TAO
  • Publication number: 20150132212
    Abstract: Methods of forming carbon films, structures and devices including the carbon films, and systems for forming the carbon films are disclosed. A method includes depositing a metal carbide film using atomic layer deposition (ALD). Metal from the metal carbide film is removed from the metal carbide film to form a carbon film. Because the films are formed using ALD, the films can be relatively conformal and can have relatively uniform thickness over the surface of a substrate.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: ASM IP Holding B.V.
    Inventor: Jereld Lee Winkler
  • Patent number: 9029264
    Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9023734
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Ching-Mei Hsu, Seung Park, Anchuan Wang, Nitin K. Ingle
  • Publication number: 20150102009
    Abstract: A method and apparatus for preparing thin TEM samples in a manner that reduces or prevents bending and curtaining is realized. Embodiments of the present invention deposit material onto the face of a TEM sample during the process of preparing the sample. In some embodiments, the material can be deposited on a sample face that has already been thinned before the opposite face is thinned, which can serve to reinforce the structural integrity of the sample and refill areas that have been over-thinned due to a curtaining phenomena. In other embodiments, material can also be deposited onto the face being milled, which can serve to reduce or eliminate curtaining on the sample face.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 16, 2015
    Applicant: FEI Company
    Inventors: Michael Moriarty, Stacey Stone, Jeffrey Blackwood
  • Publication number: 20150104648
    Abstract: The presently claimed invention provides a metal-free and low stress thick film of diamond-like carbon (DLC). The diamond-like carbon layer of the present invention has a wide range of applications such as automotive coating, hydrophobic-hydrophilic tuning, solar photovoltaic, decorative coating, protective coating and bio-compatible coating. The presently claimed invention further provides a method and an apparatus to grow a metal-free and low stress thick film of diamond-like carbon by performing deposition and plasma etching to stack more than one diamond-like carbon layers together in the same chamber.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 16, 2015
    Inventor: Zhonghui Alex WANG
  • Patent number: 9005462
    Abstract: In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 14, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventor: Jun-ichi Ohno
  • Patent number: 9005459
    Abstract: A disclosed film deposition method includes steps of loading plural substrates each of which includes a pattern including a concave part in a reaction chamber in the form of shelves; depositing a silicon oxide film on the plural substrates by supplying a silicon-containing gas and an oxygen-containing gas to the reaction chamber; etching the silicon oxide film deposited on the plural substrates in the step of depositing by supplying a fluorine-containing gas and an ammonia gas to the reaction chamber; and alternately repeating the step of depositing and the step of etching.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 14, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Toshiyuki Ikeuchi, Katsuhiko Komori, Kazuhide Hasebe
  • Patent number: 8993445
    Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dae-Han Choi, Dae Geun Yang, Chang Ho Maeng, Wontae Hwang
  • Patent number: 8992788
    Abstract: In conjunction with a photomask blank comprising a transparent substrate, a pattern-forming film, and an etch mask film, a set of etching conditions for the pattern-forming film is evaluated by measuring a first etching clear time (C1) taken when the etch mask film is etched under the etching conditions to be applied to the pattern-forming film, measuring a second etching clear time (C2) taken when the pattern-forming film is etched under the etching conditions, and computing a ratio (C1/C2) of the first to second etching clear time.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shinichi Igarashi, Hiroki Yoshikawa, Yukio Inazuki, Hideo Kaneko
  • Patent number: 8986493
    Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Tahara, Masaru Nishino
  • Patent number: 8980750
    Abstract: A chemical mechanical polishing (CMP) composition (Q) comprising (A) Inorganic particles, organic particles, or a mixture or composite thereof, wherein the particles are cocoon-shaped (B) a non-ionic surfactant, (C) a carbonate or hydrogen carbonate salt, (D) an alcohol, and (M) an aqueous medium.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 17, 2015
    Assignee: BASF SE
    Inventors: Robert Reichardt, Yuzhuo Li, Michael Lauter, Wei Lan William Chiu
  • Patent number: 8980763
    Abstract: Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Ching-Mei Hsu, Nitin K. Ingle, Zihui Li, Anchuan Wang
  • Patent number: 8980109
    Abstract: A method fabricates a magnetic transducer having a nonmagnetic layer and an ABS location corresponding to an ABS. A pole trench is provided in the nonmagnetic layer. The pole trench has a pole tip region and a yoke region. At least one pole material is provided. The pole material(s) have an external protrusion that is above and external to the pole trench. A hard mask that covers at least the external protrusion is provided. A portion of the nonmagnetic layer adjacent to the pole trench is removed to form a side shield trench. At least one side shield material is provided. A portion of the side shield material(s) are adjacent to the hard mask and fill at least a portion of the side shield trench. The side shield material(s) and the pole material(s) are planarized to form at least one side shield and a main pole.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Ronghui Zhou, Lily Yao, Ming Jiang, Lien-Chang Wang
  • Patent number: 8969212
    Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Jang-Gyoo Yang, Jonghoon Baek, Anchuan Wang, Soonam Park, Saurabh Garg, Xinglong Chen, Nitin K. Ingle
  • Publication number: 20150056412
    Abstract: Article comprising an interpenetrating phase. Embodiments of the articles are useful, for example, for optical and optoelectronic devices, displays, solar, light sensors, eye wear, camera lens, and glazing.
    Type: Application
    Filed: March 11, 2013
    Publication date: February 26, 2015
    Inventors: Ta-Hua Yu, Moses M. David, Albert I. Everaerts, William Blake Kolb, Shunsuke Suzuki
  • Patent number: 8962489
    Abstract: Disclosed is a method for etching a film contains cobalt and palladium is provided. A hard mask is provided on the film. The method film includes a process “a” of etching the film by ion sputter etching, a process “b” of exposing a workpiece to plasma of a first gas containing halogen elements after the process “a” of etching of the film, a process “c” of exposing the workpiece to plasma of a second gas containing carbons after the process “b” of exposing the workpiece to the plasma of the first gas, and a process “d” of exposing the workpiece to plasma of a third gas containing a noble gas after the process “c” of exposing the workpiece to the plasma of the second gas. In the method, a temperature of a placement table on which the workpiece is placed is set to a first temperature of 10° C. or less in the process “a”, process “b” and process “c”.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Masato Kushibiki
  • Publication number: 20150048049
    Abstract: A method for causing a first polymer and a second polymer of a block copolymer to be self-assembled on an underlayer film and forming a periodic pattern in a guide layer is provided. The method includes a first etching process of etching the second polymer by plasma generated from a first gas, a first film deposition process of depositing a first protective film on surfaces of the first polymer and the guide layer except for an etched portion of the second polymer by plasma generated from a second gas after the first etching process, and a second etching process of further etching the second polymer by the plasma generated from the first gas after the first film deposition process.
    Type: Application
    Filed: March 21, 2013
    Publication date: February 19, 2015
    Inventors: Eiichi Nishimura, Fumiko Yamashita, Satoko Niitsuma
  • Publication number: 20150048050
    Abstract: An inkjet-based process for programmable deposition of thin films of a user-defined profile. Drops of a pre-cursor liquid organic material are dispensed at various locations on a substrate by a multi-jet. A superstrate that has been bowed due to a backside pressure is brought down such that a first contact of the drops is made by a front side of the superstrate thereby initiating a liquid front that spreads outward merging with the drops to form a contiguous film captured between the substrate and the superstrate. A non-equilibrium transient state of the superstrate, the contiguous film and the substrate then occurs after a duration of time. The contiguous film is then cured to crosslink it into a polymer. The superstrate is then separated from the polymer thereby leaving a polymer film on the substrate. In such a manner, non-uniform films can be formed without significant material wastage in an inexpensive manner.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 19, 2015
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal
  • Patent number: 8956546
    Abstract: A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 17, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hajime Ugajin, Shigeki Tozawa
  • Publication number: 20150041430
    Abstract: Provided is a method for treating the inner surface of a chlorine trifluoride supply passage that enables reliable prevention of the reduction in the concentration of ClF3 in a reaction chamber during process operation. The method includes: integrally connecting a gas supply passage (2) and a gas discharge passage (3) to a processing chamber (1) of a processing apparatus in which chlorine trifluoride is used as an etching gas; and applying chlorine trifluoride gas having a concentration equal to or higher than the concentration of chlorine trifluoride gas supplied during etching process operation on inner surfaces of at least the processing chamber (1) and the gas supply passage (2) among the processing chamber (1), the gas supply passage (2), and the gas discharge passage (3), which are integrally formed, to coat the inner surfaces of at least the processing chamber (1) and the gas supply passage (2) with a fluoride film.
    Type: Application
    Filed: February 8, 2012
    Publication date: February 12, 2015
    Applicant: IWATANI CORPORATION
    Inventors: Yu Yoshino, Kunihiko Koike, Manabu Saeda, Toshiki Manabe
  • Patent number: 8945403
    Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Christina Papagianni, Gianpaolo Spadini, Jong Won Lee
  • Publication number: 20150011088
    Abstract: Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (Tgr) of the processing chamber for the step.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 8, 2015
    Inventors: Mark Edward McNie, Michael Joseph Cooke, Leslie Michael Lea
  • Patent number: 8927431
    Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Gen P. Lauer, Isaac Lauer, Joseph S. Newbury
  • Publication number: 20150001176
    Abstract: A method and apparatus for altering the orientation of a charged particle beam sample is presented. Embodiments of the method includes providing a first work piece on a sample stage having a sample stage plane, the first work piece including a lamella plane in a first orientation. A sample is milled from the first work piece using an ion beam so that the sample is substantially free from the first work piece. A probe is attached to the sample, the probe including a shaft having a shaft axis, the shaft axis oriented at a shaft angle in relation to the sample stage plane, the shaft angle being non-normal to the sample stage plane. The probe is rotated about the shaft axis through a rotational angle so that the lamella plane is in a second orientation. The sample is attached to or placed on the sample on either the first work piece, the first work piece being the work piece from which the sample was milled, or on a second work piece, the second work piece being a work piece from which the sample was not milled.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventor: Richard J. Young
  • Publication number: 20150001177
    Abstract: The present invention relates to a process for metallizing electrically nonconductive plastic surfaces of articles. During the process, the rack to which the said articles are fastened is subjected to a treatment for protection against metallization. Subsequently, the articles are metallized by means of known processes, wherein the racks remain free of metal.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 1, 2015
    Inventor: Hermann Middeke
  • Patent number: 8921229
    Abstract: A method of polishing copper wiring surfaces of in ultra large scale integrated circuit, the method including: a) preparing a polishing solution including between 35 and 80 w. % of a nano SiO2 abrasive, between 12 and 60 w. % of deionized water, between 1 and 3 w. % of an oxidant, between 1 and 4 w. % of an active agent, and between 0.5 and 1.5 w. % of a chelating agent; and b) polishing using the polishing solution under following conditions: between 2 and 5 kPa pressure; between 20 and 50° C.; between 120 and 250 mL/min slurry flow rate; and at between 30 and 60 rpm/min rotational speed.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 30, 2014
    Inventors: Yuling Liu, Xiaoyan Liu, Jun Tian