Abstract: A substrate processing apparatus includes a first processing chamber and a second processing chamber, a first substrate holding unit that holds a substrate in the first processing chamber, a chemical solution supply unit that supplies a chemical solution containing an etching component and a thickening agent to the substrate held by the first substrate holding unit, a substrate transfer unit that transfers the substrate from the first processing chamber to the second processing chamber in a state in which the chemical solution is held on the substrate, and a second substrate holding unit that holds a plurality of substrates on each of which the chemical solution is held in the second processing chamber.

Abstract: A method of making a porous SiOC membrane is provided. The method comprises disposing a SiOC layer on a porous substrate, and etching the SiOC layer to form through pores in the SiOC layer. A porous SiOC membrane having a network of pores extending through a thickness of the membrane is provided.

Abstract: An article having a nanostructured surface and a method of making the same are described. The article can include a substrate and a nanostructured layer bonded to the substrate. The nanostructured layer can include a plurality of spaced apart nanostructured features comprising a contiguous, protrusive material and the nanostructured features can be sufficiently small that the nanostructured layer is optically transparent. A surface of the nanostructured features can be coated with a continuous hydrophobic coating. The method can include providing a substrate; depositing a film on the substrate; decomposing the film to form a decomposed film; and etching the decomposed film to form the nanostructured layer.

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract: A method and apparatus is provided for preparing samples for observation in a charged particle beam system in a manner that reduces or prevents artifacts. Material is deposited onto the sample using charged particle beam deposition just before or during the final milling, which results in an artifact-free surface. Embodiments are useful for preparing cross sections for SEM observation of samples having layers of materials of different hardnesses. Embodiments are useful for preparation of thin TEM samples.

Abstract: A method for the production of a separation microcolumn made in silicon wafer (11), for a chromatographic or gas-chromatographic system, is described. According to the method, a micro-trench (14) is first made in the silicon wafer. The micro-trench extends in depth in the silicon wafer (11) and along the entire path of the microcolumn. Then, a perfectly circular micro-channel (20), tangent to the upper surface of the silicon wafer (11), is obtained by an in-depth isotropic etching with reactive ions in the micro-trench (14). The microcolumn is functionalized by applying a stationary phase (SP) to the inner wall and finally, another wafer or a layer (17) of silicon or silicon oxide or polymeric material, that acts as a cap or cover, is applied onto the silicon wafer, thus closing the micro-channel. According to a variation, the functionalization is carried out after the micro-channel closure.

Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.

Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.

Abstract: A method for processing a substrate includes arranging a substrate including masked portions and unmasked portions in a process chamber; creating plasma in a process chamber; supplying a passivation gas mixture that includes nitrogen or carbon to create a plasma passivation gas mixture; exposing a substrate to the plasma passivation gas mixture to create a passivation layer on the unmasked portions of the substrate; supplying a stripping gas mixture that includes oxygen to the plasma to create a plasma stripping gas mixture; exposing the substrate to the plasma stripping gas mixture to strip at least part of the masked portions and at least part of the unmasked portions; and repeating creating the passivation layer and the stripping to remove a predetermined amount of the masked portions.

Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

Abstract: Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass transition temperature (Tg,O) and a degradation temperature (Td). A temperature window may be defined to correspond to temperatures (T) within the range of Tg,O?T?Td. While the block copolymer is in the upper half of the temperature window, solvent may be dispersed into the block copolymer to a process volume fraction that induces self-assembly of the block copolymer into a pattern. A defect specification may be defined, and the process volume fraction of solvent may be at level that achieves self-assembly within the defect specification. In some embodiments, the solvent may be removed from within the block copolymer while maintaining the defect specification.

Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.

Abstract: A nozzle plate containing multiple micro-orifices for the cascade impactor and a method for manufacturing the same are disclosed. The nozzle plate is formed by a series of semiconductor processes, including lithography, etching and electroplating. The nozzle plate comprises a plate body and a plurality of micro-orifices formed on the plate body. The orifice has a diameter which gradually expands in the direction away from the bottom of the plate body to achieve a smooth inner surface, allowing particles to pass therethrough smoothly without being clogged in the nozzle plate.

Abstract: A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of materials whose selectivity is increased using this technique include silicon nitride and silicon. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-oxygen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including a nitrogen-containing precursor and a hydrogen-containing precursor. The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

Abstract: A method of forming a metal pattern is disclosed. In the method, a metal layer is formed on a base substrate. A photoresist composition is coated on the metal layer to form a coating layer. The photoresist composition includes a binder resin, a photo-sensitizer, a mercaptopropionic acid compound and a solvent. The coating layer is exposed to a light. The coating layer is partially removed to form a photoresist pattern. The metal layer is patterned by using the photoresist pattern as a mask.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.

Abstract: In production of a mold having a deposited film on the surface thereof as a mold release layer, a quartz substrate plasma etched employing an etching gas that includes a sedimentary gas to form a pattern of protrusions and recesses having a desired shape in a structure constituted by the quartz substrate and a mask layer, while a deposited film constituted by sediment of the sedimentary gas is formed along the pattern of protrusions and recesses. The deposited film becomes the mold release layer. Thereby, throughput of mold production is improved in the production of molds having deposited films as mold release layers on the surfaces thereof.

Abstract: A method for manufacturing a printed circuit board enables a metal residue between wirings to be removed inexpensively without side etching of a copper layer while having sufficient insulation reliability for micro wiring working. The method includes forming a base metal layer directly at least on one face of an insulator film without an adhesive, and a copper coat layer formed on the base metal layer to form adhesiveless copper clad laminates, then forming a pattern on the adhesiveless copper clad laminates by an etching method. The etching method includes a process of etching treatment for the adhesiveless copper clad laminates with an iron (III) chloride solution or a copper (II) chloride solution containing hydrochloric acid and then, a process of treatment with an acid oxidant containing potassium permanganate.

Abstract: High quantum yield InP nanocrystals are used in the bio-technology, bio-medical, and photovoltaic, specifically IV, III-V and III-VI nanocrystal technological applications. InP nanocrystals typically require post-generation HF treatment. Combining microwave methodologies with the presence of a fluorinated ionic liquid allows Fluorine ion etching without the hazards accompanying HF. Growing the InP nanocrystals in the presence of the ionic liquid allows in-situ etching to be achieved. The optimization of the PL QY is achieved by balancing growth and etching rates in the reaction.

Abstract: A method of manufacturing a magnetic recording medium, includes, in the order recited, the steps of forming a mask protective film composed of carbon on a magnetic layer; forming a resist with a predetermined pattern on the mask protective film; forming a protective mask by etching the mask protective film using the resist as a mask; forming protrusions and recesses on a magnetic layer by etching the magnetic layer using the resist and the protective mask as masks; removing the protective mask, including removing the mask protective film comprised of carbon, using ultraviolet light with a principal wavelength not longer than 340 nm; and forming a protective layer on the magnetic layer having the protrusions and recesses formed thereon.

Abstract: Methods for removing residue from interior surfaces of process chambers are provided herein. In some embodiments, a method of conditioning interior surfaces of a process chamber may include maintaining a process chamber at a first pressure and at a first temperature of less than about 800 degrees Celsius; providing a process gas to the process chamber at the first pressure and the first temperature, wherein the process gas comprises chlorine and nitrogen to remove residue disposed on interior surfaces of the process chamber; and increasing the pressure in the process chamber from the first pressure to a second pressure while continuing to provide the process gas to the process chamber.

Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Abstract: Example embodiments are directed to an electronic device and a method for manufacturing the same. The electronic device includes a polymer thin film and an electrode. The polymer thin film includes nanoparticles. The electrode is formed by attaching a graphene thin film of a sheet shape formed through graphene deposition using a vapor carbon supply source to the polymer thin film. In the method, a graphene thin film of a sheet shape is formed through graphene deposition using a vapor carbon supply source. A polymer solution with distributed nanoparticles is prepared. The polymer solution with distributed nanoparticles is spin-coated on a substrate. A polymer thin film comprising the nanoparticles is formed by drying the spin-coated polymer solution. An electrode is formed by attaching the graphene thin film onto the polymer thin film.

Abstract: A nozzle plate containing multiple micro-orifices for the cascade impactor and a method for manufacturing the same are disclosed. The nozzle plate is formed by a series of semiconductor processes, including lithography, etching and electroplating. The nozzle plate comprises a plate body and a plurality of micro-orifices formed on the plate body. The orifice has a diameter which gradually expands in the direction away from the bottom of the plate body to achieve a smooth inner surface, allowing particles to pass therethrough smoothly without being clogged in the nozzle plate.

Abstract: There is disclosed a minute structure including a sulfur compound and a silicon oxide. There is also disclosed a write-once information recording medium including a substrate and a recording layer formed of a mixed inorganic material and deposited on the substrate, wherein the mixed inorganic material contains a sulfur compound and a silicon oxide.

Abstract: An article of manufacture includes a substrate having an outer surface clad with a metal construct including one or more continuous metal layers, at least one of which is an amorphous layer or a microcrystalline layer having a grain size below 5000 nm. A bonding layer is provided between the substrate and the layered metallic construct so that the bonding layer is in direct contact with the substrate and with the layered metallic construct. The bonding layer is made of a substantially fully cured resin including at least 10% of a rubber. The layered metallic construct has peel strength greater than 10N/cm. Also provided is a process for making the article including coating an article outer surface with a bonding layer and a layered metallic construct. The bonding layer is substantially fully cured before the layered metal construct is bonded to the article. The coated article is annealed.

Abstract: A method for inspecting semiconductor wafers patterned by a photomask includes loading a first wafer and scanning a first image of the first wafer, loading a second wafer and scanning a second image of the second wafer, comparing the first and second images, and classifying a difference detected between the first and second images as a potential defect on the photomask. The potential defect includes a haze defect on the photomask.

Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

Abstract: A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.

Abstract: A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process.

Abstract: A substrate table comprising a base and a plurality of burls that project from the base, wherein an upper surface of the burls is provided with a multilayer coating.

Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.

Abstract: A substrate processing method uses a substrate processing apparatus including a chamber for accommodating a substrate, a lower electrode to mount the substrate, a first RF power applying unit for applying an RF power for plasma generation into the chamber, and a second RF power applying unit for applying an RF power for bias to the lower electrode. The RF power for plasma generation is controlled to be intermittently changed by changing an output of the first RF power applying unit at a predetermined timing. If no plasma state or an afterglow state exists in the chamber by a control of the first RF power applying unit, an output of the second RF power applying unit is controlled to be in an OFF state or decreased below an output of the second RF power applying unit when the output of the first RF power applying unit is a set output.

Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.

Abstract: An in situ manufacturing process monitoring system of extreme smooth thin film and method thereof, comprising a coating device for coating a thin film on at least one substrate during a coating process, an ion figuring device for processing a surface polishing process on the thin film, a control device electrically coupled to the coating device and the ion figuring device respectively for controlling the coating device and the ion figuring device processing the coating process and surface polishing process by adjusting at least one device parameter of the coating device and the ion figuring device, and an in situ monitoring device electrically coupled to the control device for in situ monitoring at least one optical parameter of the thin film.

Abstract: High quantum yield InP nanocrystals are used in the bio-technology, bio-medical, and photovoltaic, specifically IV, III-V and III-VI nanocrystal technological applications. InP nanocrystals typically require post-generation HF treatment. Combining microwave methodologies with the presence of a fluorinated ionic liquid allows Fluorine ion etching without the hazards accompanying HF. Growing the InP nanocrystals in the presence of the ionic liquid allows in-situ etching to be achieved. The optimization of the PL QY is achieved by balancing growth and etching rates in the reaction.

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

Abstract: A printed circuit board manufacturing system and a manufacturing method thereof are disclosed. A method of manufacturing printed circuit board, comprising: providing a substrate that comprises a pad and an insulation layer covering the pad; acquiring an image of the substrate; acquiring location information of the pad by analyzing the image of the substrate; forming a via hole by removing a part of the insulation layer that corresponds the location information of the pad; and forming a via by filling the via hole with a conductive material, provides improved process conformity, even if the substrate has partial or nonlinear deformation, by considering the location information of the pad in the via hole forming. The improved conformity may allow more flexibility to substrate design and more integrity for circuitries on printed circuit board.

Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

Abstract: The present invention relates to a plasma etching method in which a special area for detecting an end point needs not to be set and an equipment therefor. At an etching step of forming SF6 gas into plasma to etch an etching ground on a Si film, the step is configured by two steps of: a large-amount supply step of supplying a large amount of SF6 gas; and a small-amount supply step of supplying a small amount of SF6 gas. An end-point detecting processor 34 measures an emission intensity of Si or SiFx in the plasma at the small-amount supply step, and determines that an etching end point is reached when the measured emission intensity becomes equal to or less than a previously set reference value.

Abstract: A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma.

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: A method of patterning a substrate in accordance with an embodiment of the invention includes forming a plurality of openings within at least one of photoresist and amorphous carbon. The openings are of common outermost cross sectional shape relative one another. Individual of the openings have at least one lateral open dimension having a degree of variability among the plurality. The photoresist with the plurality of openings is exposed to/treated with a plasma effective to both increase the lateral open size of the openings and at least reduce the degree of variability of said at least one open dimension among the openings. Other aspects and implementations are contemplated.

Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.