Planarizing A Nonplanar Surface Patents (Class 216/38)
  • Patent number: 10676818
    Abstract: A method for producing a material based on silicon nanowires is provided. The method includes the steps of: i) bringing into contact, in an inert atmosphere, a sacrificial support based on a halogenide, a carbonate, a sulfate or a nitrate of an alkali metal, an alkaline earth metal or a transition metal having metal nanoparticles, with the pyrolysis vapours of a silicon source having a silane compound, by which silicon nanowires are deposited on the sacrificial support; and optionally ii) eliminating the sacrificial support and recovering the silicon nanowires produced in step ii).
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 9, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pascale Chenevier, Peter Reiss, Olga Burchak
  • Patent number: 10643824
    Abstract: A plasma generating apparatus according to the present disclosure includes: a high frequency power supply that generates a high frequency power; a plasma generation electrode connected to the high frequency power supply and formed by a hollow tube in which cooling water is distributed; a conductivity meter that measures conductivity of the cooling water inside the plasma generation electrode; and a controller that controls output of the high frequency power supply based on the conductivity of the cooling water measured by the conductivity meter.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 5, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Takeshi Kobayashi
  • Patent number: 10553501
    Abstract: An apparatus can include a logic element configured to generate information corresponding to an adaptive layer to be formed over a current substrate based at least in part on a difference in flatness profiles associated with a first substrate chuck and a second substrate chuck. In another aspect, a method can include obtaining a difference in thickness profiles for the first and second chucks using a prior substrate, and forming an adaptive layer over a previously formed patterned layer of a current substrate and before forming a patterned resist layer aligned to the previously formed patterned layer. In an embodiment, the thickness profile of the adaptive layer is a function of the inverse of the difference in flatness profiles of the substrate chucks. The adaptive layer can help to reduce overlay error associated with different flatness profiles of substrate chucks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 4, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Anshuman Cherala, Mario J. Meissl
  • Patent number: 10535558
    Abstract: A method of forming a semiconductor device fabrication is described that includes forming a material layer over a substrate, forming a first trench in the material layer, forming a first dielectric capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer disposed along sidewalls of the first trench, forming a second dielectric capping layer along sidewalls of the second trench and along the sidewalls of the first trench and forming a conductive feature within the second trench and the first trench.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10324354
    Abstract: A first electro-optic display comprises first and second substrates, and an adhesive layer and a layer of electro-optic material disposed between the first and second substrates, the adhesive layer comprising a mixture of a polymeric adhesive material and a hydroxyl containing polymer having a number average molecular weight not greater than about 5000. A second electro-optic display is similar to the first but has an adhesive layer comprising a thermally-activated cross-linking agent to reduce void growth when the display is subjected to temperature changes. A third electro-optic display, intended for writing with a stylus or similar instrument, is produced by forming a layer of an electro-optic material on an electrode; depositing a substantially solvent-free polymerizable liquid material over the electro-optic material; and polymerizing the polymerizable liquid material.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 18, 2019
    Assignee: E Ink Corporation
    Inventors: Richard J. Paolini, Jr., Michael D. McCreary, Charles Howie Honeyman, Bin Wu
  • Patent number: 10297279
    Abstract: Methods of planarizing materials, such as where surface topographies are created as part of a thin film device fabrication process are described. These methods find particular application in the creation of nano-sized devices, where surface topographical features can be effectively planarized without adversely creating other surface topographies and/or causing deleterious effects a material junctions. Methods include the step of depositing a sacrificial layer overlying at least a portion of a first material layer and at least a portion of a backfilled second material at a junction between the first and second materials. The sacrificial layer substantially retains the surface topography of the microelectronic device. Chemical-mechanical planarization is performed on a surface of the sacrificial layer but leaving a remainder portion of the thickness of the sacrificial layer.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 21, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhiguo Ge, Shaun E. Mckinlay, Stacey C. Wakeham
  • Patent number: 10236226
    Abstract: Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: March 19, 2019
    Assignee: Raytheon Company
    Inventors: Sean P. Kilcoyne, Robert M. Emerson, Michael V. Liguori
  • Patent number: 10227517
    Abstract: Provided is a method for polishing a material having a Vickers hardness of 1500 Hv or higher. The polishing method comprises a step of carrying out preliminary polishing using a preliminary polishing composition that comprises an abrasive APRE and a step of carrying out final polishing using a final polishing composition that comprises an abrasive AFIN lower in hardness than the abrasive APRE.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 12, 2019
    Assignee: Fujimi Incorporated
    Inventors: Shuhei Takahashi, Masatoshi Tomatsu
  • Patent number: 10211151
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo, Nicole A. Saulnier
  • Patent number: 9972515
    Abstract: In a substrate processing apparatus, a temperature of an anti-static liquid having electrical resistivity which gradually decreases as a liquid temperature increases is adjusted by a temperature adjustment part and the electrical resistivity of the anti-static liquid is higher than the electrical resistivity of a processing liquid (SPM liquid). After that, a plurality of substrates are immersed in the anti-static liquid inside the anti-static liquid storage part and both main surfaces of each substrate entirely conic into contact with the anti-static liquid. This gradually removes static electricity from the substrate. Then, the SPM liquid is supplied onto an upper surface of the substrate to thereby perform an SPM process. In the SPM process, it is thereby possible to prevent a large amount of electric charges from sharply moving from the substrate to the SPM liquid and prevent any damage to the substrate.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 15, 2018
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Masahiro Miyagi, Kenichiro Arai
  • Patent number: 9934958
    Abstract: The substrate treatment apparatus includes a first nozzle, a second nozzle, a detector, and a controller. The first nozzle supplies an organic sublimable material-containing liquid capable of displacing a rinsing liquid, to a surface of a substrate treated with the rinsing liquid. The second nozzle supplies vapor of a solvent in which the organic sublimable material is capable of dissolving, to the surface of the substrate. The detector detects a first physical amount of the vapor on the surface of the substrate. The controller controls a second physical amount of the vapor according to the first physical amount.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiro Sato, Junichi Igarashi
  • Patent number: 9928994
    Abstract: A method for depositing an amorphous carbon hardmask film includes arranging a substrate in a processing chamber, supplying a carrier gas to the processing chamber, supplying a hydrocarbon precursor to the processing chamber, supplying fluorine precursor from a group consisting of WFa, NFb, SFc, and F2 to the processing chamber, one of supplying plasma to the processing chamber or creating plasma in the processing chamber, and depositing an amorphous carbon hardmask film on the substrate. Fluorine from the fluorine precursor combines with hydrogen from the hydrocarbon precursor in gas phase reactions.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 27, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Fayaz Shaikh, Sirish Reddy
  • Patent number: 9886026
    Abstract: In one aspect, a method of polishing includes polishing a substrate, and receiving an identification of a selected spectral feature and a characteristic of the selected spectral feature to monitor during polishing. The method includes measuring a sequence of spectra of light reflected from the substrate while the substrate is being polished, where at least some of the spectra of the sequence differ due to material being removed during the polishing. The method of polishing includes determining a value of a characteristic of the selected spectral feature for each of the spectra in the sequence of spectra to generate a sequence of values for the characteristic, fitting a function to the sequence of values, and determining either a polishing endpoint or an adjustment for a polishing rate based on the function.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: February 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Harry Q. Lee, Dominic J. Benvegnu, Boguslaw A. Swedek
  • Patent number: 9768024
    Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen, Tien-I Bao
  • Patent number: 9746772
    Abstract: A method for producing a semiconductor device, which includes forming an underlayer film on a semiconductor substrate with a resist underlayer film forming composition that contains a solvent, and a polymer containing a unit structure of Formula (2): O—Ar2—O—Ar3-T-Ar4??Formula (2) where Ar2, Ar3, and Ar4 are individually a C6-50 arylene group or an organic group containing a heterocyclic group; at least one of Ar3 and Ar4 is a phenylene group; and T is a carbonyl group. The resist underlayer film forming composition has a solid content of 0.1 to 70 mass % of a total mass of the composition.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 29, 2017
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Hiroaki Okuyama, Yasunobu Someya, Masakazu Kato, Tetsuya Shinjo, Keisuke Hashimoto
  • Patent number: 9627246
    Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 18, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Hiroki Sato, Gregory Allen Stom
  • Patent number: 9535329
    Abstract: A method for making patterns on a substrate, includes forming an assembly guide on first and second areas of the substrate, the assembly guide having, compared to a reference surface, openings with an opening ratio in the first area greater than that of the second area; depositing a block copolymer layer on the substrate to entirely fill the assembly guide and form an over-thickness on the reference surface; assembling the block copolymer, resulting in an organised portion of the block copolymer layer inside the openings; thinning uniformly the block copolymer layer, until a thickness corresponding to the organised portion of the block copolymer layer is reached; eliminating one of the phases of the assembled block copolymer, resulting in a plurality of initial patterns extending into the layer of block copolymer; and transferring the initial patterns of the block copolymer layer into the substrate to form the final patterns.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: January 3, 2017
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Patricia Pimenta Barros, Raluca Tiron, Xavier Chevalier, Ahmed Gharbi
  • Patent number: 9368366
    Abstract: A method of forming a plurality of regularly spaced lithography features, the method including providing a self-assemblable block copolymer having first and second blocks in a plurality of trenches on a substrate, each trench including opposing side-walls and a base, with the side-walls having a width therebetween, wherein a first trench has a greater width than a second trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in each trench, the layer having a first domain of the first block alternating with a second domain of the second block, wherein the first and second trenches have the same number of each respective domain; and selectively removing the first domain to form regularly spaced rows of lithography features having the second domain along each trench, wherein the pitch of the features in the first trench is greater than the pitch of the features in the second trench.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 14, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Sander Frederik Wuister, Tamara Druzhinina, Mircea Dusa
  • Patent number: 9365933
    Abstract: A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 14, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Ha Son, Su-Bin Bae, Yu-Gwang Jeong, Lei Xie, Yun-Jong Yeo, Joo-Hyung Lee
  • Patent number: 9293678
    Abstract: Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: March 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Scott D. Schellhammer, Scott E. Sills, Casey Kurth
  • Patent number: 9245860
    Abstract: In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: January 26, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Patent number: 9053736
    Abstract: A method for manufacturing an aluminosilicate glass substrate for a hard disk of the present invention includes polishing an aluminosilicate glass substrate to be polished with a polishing composition that includes silica particles, a polymer having a sulfonic acid group, and water, wherein an adsorption constant of the polymer having the sulfonic acid group on aluminosilicate glass is 1.5 to 5.0 L/g. The polymer having the sulfonic acid group is preferably a polymer having an aromatic ring. The weight average molecular weight of the polymer having the sulfonic acid group is 3000 to 100000.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: June 9, 2015
    Assignee: Kao Corporation
    Inventors: Haruhiko Doi, Yosuke Uchino, Kazuhiko Nishimoto
  • Publication number: 20150129543
    Abstract: Provided are a method for etching a metal or metal oxide without using a reagent, etc., that affects the environment, a method for smoothing a surface of a metal or metal oxide on an atomic level, and a method for patterning on an atomic level. Etching of a metal or metal oxide, or smoothing of a surface of a metal or metal oxide is possible using ozone water in which only ozone is dissolved. Patterning can also be performed by providing a metal that does not dissolve in the ozone water as a resist on a metal or metal oxide that can be etched by ozone water in which only ozone is dissolved, and etching using the ozone water.
    Type: Application
    Filed: April 25, 2013
    Publication date: May 14, 2015
    Applicant: Japan Science and Technology Agency
    Inventors: Takatoki Yamamoto, Ryuji Hatsuki
  • Patent number: 9023224
    Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 5, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Patent number: 9018100
    Abstract: Damascene processes using physical vapor deposition (PVD) sputter carbon film as a chemical mechanical planarization (CMP) stop layer for forming a magnetic recording head are provided. In one embodiment, one such process includes providing an insulator, removing a portion of the insulator to form a trench within the insulator, depositing a carbon material on first portions of the insulator using a physical vapor deposition process, disposing at least one ferromagnetic material on second portions of the insulator to form a pole including a portion of the ferromagnetic material within the trench, and performing a chemical mechanical planarization on the at least one ferromagnetic material using at least a portion of the carbon material as a stop for the chemical mechanical planarization.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 28, 2015
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yanfeng Chen, Yunjun Tang, Yana Qian, Ming M. Yang, Yunfei Li, Paul E. Anderson
  • Publication number: 20150083689
    Abstract: The invention provides a chemical-mechanical polishing composition and a method of chemically-mechanically polishing a substrate with the chemical-mechanical polishing composition. The polishing composition comprises (a) abrasive particles that comprise ceria, zirconia, silica, alumina, or a combination thereof, (b) a metal ion that is a Lewis Acid, (c) a ligand that is an aromatic carboxylic acid, an aromatic sulfonic acid, an aromatic acid amide, an amino acid, or a hydroxy-substituted N-heterocycle, and (d) an aqueous carrier, wherein the pH of the chemical-mechanical polishing composition is in the range of about 1 to about 4.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Inventors: Sudeep PALLIKKARA KUTTIATOOR, Renhe Jia, Jeffrey Dysard
  • Patent number: 8980110
    Abstract: A liquid ejection head includes a substrate having an ejection energy generating element formed at a first surface side thereof, a common liquid chamber formed at a second surface of the substrate, and a liquid supply port extending from the bottom of the common liquid chamber to the first surface. The liquid ejection head is manufactured by preparing a substrate having the common liquid chamber formed at the second surface side, then arranging a material to be filled in the common liquid chamber, subsequently forming an aperture in the filled material as corresponding to the liquid supply port to be formed, and thereafter forming the liquid supply port by reactive ion etching, using at least the filled material as a mask.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahisa Watanabe, Kazuhiro Hayakawa, Toshiyasu Sakai
  • Patent number: 8974680
    Abstract: A pattern forming method includes forming a coating film containing a hydrophilic first homopolymer having a first bonding group and a hydrophobic second homopolymer having a second bonding group capable of bonding with the first bonding group, forming a bond between the first and second bonding group to produce a block copolymer of the first and second homopolymers, and heating the coating film to microphase-separating the copolymer into a hydrophilic domain and a hydrophobic domain. The hydrophilic and hydrophobic domains are arranged alternately. The bond is broken, then selectively dissolving-removing either domain by a solvent to provide a polymer pattern of a remainder domain.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Tanaka, Ryosuke Yamamoto, Naoko Kihara
  • Publication number: 20150060401
    Abstract: A method of edge coating a batch of glass articles includes printing masks on surfaces of a glass sheet, where at least one of the masks is a patterned mask defining a network of separation paths. The glass sheet with the printed masks is divided into multiple glass articles along the separation paths. For at least a batch of the glass articles, the edges of the glass articles in the batch are finished to reduce roughness at the edges. Each finished edge is then etched with an etching medium to reduce and/or blunt flaws in the finished edge. A curable coating is simultaneously applied to the etched edges. The curable coatings are pre-cured. Then, the printed masks are removed from the glass articles with the curable coatings. After removing the printed masks, the pre-cured curable coatings are post-cured.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Inventors: Shih-Min Chang, Cheng-Ta Chen, UeiJie Lin, Hsien Li Lu
  • Publication number: 20150060400
    Abstract: The present invention provides a polishing composition that can suppress generation of bumps due to etching on a surface of an object to be polished having a germanium material-containing part during the polishing of the object. The polishing composition of the present invention contains abrasive grains, an oxidant and a water-soluble polymer. The water-soluble polymer may be a water-soluble polymer such that 5,000 or more molecules are adsorbed per 1 ?m2 of the surface area of the abrasive grains. Alternatively, the water-soluble polymer may be a compound that reduces the water contact angle of the germanium material-containing part of the object to be polished after the object has been polished by using the polishing composition.
    Type: Application
    Filed: April 9, 2013
    Publication date: March 5, 2015
    Applicant: FUJIMI INCORPORATED
    Inventor: Shuichi Tamada
  • Patent number: 8968583
    Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mary Beth Rothwell, Roy Rongqing Yu
  • Publication number: 20150053642
    Abstract: A method of polishing a sapphire substrate is provided, comprising: providing a substrate having an exposed sapphire surface; providing a chemical mechanical polishing slurry, wherein the chemical mechanical polishing slurry comprises, as initial components: colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm; optionally, a biocide; optionally, a nonionic defoaming agent; and, optionally, a pH adjuster. A chemical mechanical polishing composition for polishing an exposed sapphire surface is also provided.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: NITTA HAAS INCORPORATED
    Inventors: Allen S. Bulick, Hideaki Nishizawa, Kazuki Moriyama, Koichi Yoshida, Shunji Ezawa, Selvanathan Arumugam
  • Publication number: 20150037897
    Abstract: A method of removing material from a sapphire article is described. In particular, the method comprises the step of providing an initial sapphire layer and reducing the thickness of the layer while not significantly increasing the surface roughness of the layer, Cover plates for electronic device and methods of preparing them are also disclosed, along with a method of analyzing a sapphire article produced by the present method.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 5, 2015
    Inventors: Gopal Prabhu, Venkatesan Murali, Daniel Squiller
  • Publication number: 20150037537
    Abstract: A method of removing material from a sapphire article is described. In particular, the method comprises the step of providing an initial sapphire layer and reducing the thickness of the layer while not significantly increasing the surface roughness of the layer. Cover plates for electronic device and methods of preparing them are also disclosed, along with a method of analyzing a sapphire article produced by the present method.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 5, 2015
    Inventors: Gopal Prabhu, Venkatesan Murali
  • Publication number: 20150027981
    Abstract: A method of chemical mechanical polishing (CMP) a diamond containing surface includes providing a slurry including a plurality of particles, at least one oxidizer, and at least one acid, wherein the slurry has a pH?3 or pH greater than 11. At least an outer surface of the plurality of particles is softer than the diamond surface or the particles are diamond particles averaging less than (<) 2 ?m in size. The diamond surface is pressed with respect to a polishing pad providing a Shore D Hardness less than 99 having the slurry in between while rotating the polishing pad relative to the diamond surface to form a smooth diamond surface having a root mean square (rms) surface roughness less than 15 nm.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 29, 2015
    Inventors: RAJIV K. SINGH, DEEPIKA SINGH, ARUL CHAKKARAVARTHI ARJUNAN
  • Publication number: 20150021292
    Abstract: Disclosed is a polishing agent for synthetic quartz glass substrates, which is characterized by containing a colloidal solution of a colloidal silica or the like having a colloid concentration of 20-50% by mass, and a polycarboxylic acid polymer, an acidic amino acid, a phenol or a glycosaminoglycan.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Daijitsu HARADA, Masaki TAKEUCHI, Yukio SHIBANO, Shuhei UEDA, Atsushi WATABE
  • Patent number: 8936729
    Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akifumi Gawase, Yukiteru Matsui
  • Publication number: 20150018261
    Abstract: A post chemical-mechanical-polishing (post-CMP) cleaning composition comprising: (A) at least one compound comprising at least one thiol (—SH), thioether (—SR1) or thiocarbonyl (>C?S) group, wherein R1 is alkyl, aryl, alkylaryl or arylalkyl, (B) at least one sugar alcohol which contains at least three hydroxyl (—OH) groups and does not comprise any carboxylic acid (—COOH) or carboxylate (—COO—) groups, and (C) an aqueous medium.
    Type: Application
    Filed: January 24, 2013
    Publication date: January 15, 2015
    Applicant: BASF SE
    Inventors: Yuzhuo Li, Shyam Sundar Venkataraman, Mingjie Zhong
  • Publication number: 20150009571
    Abstract: A method of manufacturing nanostructures on a surface of a metal substrate is provided. The method includes forming the nanostructures by a forming step, which includes subsequently performing at least once the steps of anodizing the surface at a second voltage for forming at the surface a second oxidized metal layer comprising second pores, and performing an etching step on the surface for modifying the dimensions of the second pores. Prior to the forming step, the method comprises a substrate preparation step for enabling the forming a mix of different sized nanostructures during the forming step, the preparation step including the steps of anodizing the surface at a first voltage for forming at the surface an first oxidized metal layer comprising first pores, selectively etching the surface for extending the first pores into the metal underneath the first oxidized metal layer, and removing the first oxidized metal layer.
    Type: Application
    Filed: February 7, 2013
    Publication date: January 8, 2015
    Inventor: Patrick Chin
  • Patent number: 8921230
    Abstract: An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent by weight to about 20 percent by weight of acetic acid, about 5 percent by weight to about 10 percent by weight of a nitrate, about 6 percent by weight to about 15 percent by weight of a sulfonic acid, about 1 percent by weight to about 5 percent by weight of an amine compound including a carboxyl group, about 0.1 percent by weight to about 1 percent by weight of a water-soluble amino acid, about 0.01 percent by weight to about 1 percent by weight of an azole compound, and water.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong-Sick Park, Young-Jun Kim, Young-Woo Park, Wang-Woo Lee, Won-Guk Seo, Sam-Young Cho, Seung-Yeon Han, Gyu-Po Kim, Hyun-Cheol Shin, Ki-Beom Lee
  • Publication number: 20140374378
    Abstract: Methods for removing, reducing or treating the trace metal contaminants and the smaller fine sized cerium oxide particles from cerium oxide particles, cerium oxide slurry or chemical mechanical polishing (CMP) compositions for Shallow Trench Isolation (STI) process are applied. The treated chemical mechanical polishing (CMP) compositions, or the CMP polishing compositions prepared by using the treated cerium oxide particles or the treated cerium oxide slurry are used to polish substrate that contains at lease a surface comprising silicon dioxide film for STI (Shallow trench isolation) processing and applications. The reduced nano-sized particle related defects have been observed due to the reduced trace metal ion contaminants and reduced very smaller fine cerium oxide particles in the Shallow Trench Isolation (STI) CMP polishing.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Xiaobo Shi, John Edward Quincy Hughes, Hongjun Zhou, Daniel Hernandez Castillo, II, Jae Ouk Choo, James Allen Schlueter, Jo-Ann Theresa Schwartz, Laura Ledenbach, Steven Charles Winchester, Saifi Usmani, John Anthony Marsella, Martin Kamau Ngigi Mungai
  • Publication number: 20140360021
    Abstract: This invention relates to a novel application of liquid-infused surface materials (LISM) to at least a portion of one or more surfaces of razor components (e.g., frame, housing, clips, blade supports, blade body, blade edge, lubricating bodies, guard, handle, grip, button). If applied to a skin contacting surface of a component, the one or more LISM layers may generally be abrasion-resistant, long-lasting or non-erodible, desirably elevating shaving performance, such as glide, comfort, rinsing, and cleanliness, while also simplifying the manufacturing process.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 11, 2014
    Applicant: The Gillette Company
    Inventors: Neville Sonnenberg, Alison Fiona Stephens, Joia Kirin Spooner-Wyman
  • Publication number: 20140346140
    Abstract: The invention provides a chemical-mechanical polishing composition containing a ceria abrasive, an ionic polymer of formula I: wherein X1 and X2, Z1 and Z2, R2, R3, and R4, and n are as defined herein, and water, wherein the polishing composition has a pH of about 1 to about 4.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Inventors: Kevin P. Dockery, Renhe Jia, Jeffrey Dysard
  • Patent number: 8883020
    Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Xunyuan Zhang, Xiuyu Cai
  • Patent number: 8877075
    Abstract: In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: November 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Johann Kosub
  • Patent number: 8869362
    Abstract: A method of forming an array of piezoelectric actuators on a membrane (18) which includes the steps of preparing a piezoelectric comb-like structure having an array of islands that are integrally connected by a continuous top portion and that form piezoelectric layers of the actuators, the islands having an electrode at a bottom side, attaching the comb-like structure with its bottom electrode to a surface of the membrane, removing the continuous top portion of the comb-like structure to thereby separate the actuators from one another, and forming top electrodes on the top surfaces of the piezoelectric layers of the actuators.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 28, 2014
    Assignee: Oce-Technology B.V.
    Inventors: David D. L. Wijngaards, Hans Reinten, Hendrik J. Stolk, Alex N. Westland
  • Patent number: 8871644
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO2, planarizing the surface of the to-be-processed film, and etching the planarized surface of the to-be-processed film.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Akifumi Gawase, Gaku Minamihaba
  • Patent number: 8871103
    Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Brett Busch, Gowri Damarla, Anurag Jindal, Chia-Yen Ho, Thy Tran
  • Publication number: 20140305901
    Abstract: The present invention relates to an additive mixture comprising a polyacrylate salt, an acid ester, and a defoamer agent. A polishing composition and a polishing method used for polishing a glass substrate are also provided.
    Type: Application
    Filed: November 9, 2011
    Publication date: October 16, 2014
    Applicant: RHODIA OPERATIONS
    Inventors: Qiang Gong, Aimin Huang
  • Publication number: 20140308155
    Abstract: An efficient polishing method for polishing an alloy material to have an excellent mirror surface is provided. The alloy material contains a main component and 0.1% by mass or more of an element that has a Vickers hardness (HV) different from the Vickers hardness of the main component by 5 or more. A polishing composition used in the polishing method contains abrasive grains and an oxidant. The alloy material is preferably an aluminum alloy, a titanium alloy, a stainless steel, a nickel alloy, or a copper alloy. It is also preferable that the alloy material is subjected to preliminary polishing before being subjected to polishing in which the polishing composition is used.
    Type: Application
    Filed: November 19, 2012
    Publication date: October 16, 2014
    Inventors: Hitoshi Morinaga, Hiroshi Asano, Maiko Asai, Shogo Tsubota, Kazusei Tamai