Forming Groove Or Hole In A Substrate Which Is Subsequently Filled Or Coated Patents (Class 216/39)
  • Publication number: 20140360974
    Abstract: A method of making an aluminum alloy-resin composite and an aluminum alloy-resin composite obtained by the same are provided. The method may comprise: S1: anodizing a surface of an aluminum alloy substrate to form an oxide layer on the surface, in which the oxide layer includes nanopores; S2: immersing the resulting aluminum alloy substrate obtained at step S1 in an alkaline solution having a pH of about 10 to about 13, to form corrosion pores on an outer surface of the oxide layer, wherein the alkaline solution is an aqueous solution including at least one selected from a soluble carbonates, a soluble alkali, a soluble phosphate, a soluble sulfate, and a soluble borate; S3: injection molding a resin onto the surface of the resulting aluminum alloy substrate in step S2 in a mold to obtain the aluminum alloy-resin composite.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Jian SUN, Yanqing WU, Yunxia ZHANG
  • Publication number: 20140339192
    Abstract: A three-dimensional object fabrication method and apparatus to fabricate a three-dimensional object from a foamed material are provided. The method includes applying a solvent to dissolve the foamed material; dissolving and contracting the foamed material; and molding a three-dimensional object. The solvent is applied to a surface of the foamed material, thereby dissolving and contracting of the foamed material in a depth direction, or otherwise, the solvent is applied to an interior portion of the foamed material, thereby releasing air contained inside the foamed material and starting contraction of the foamed material itself. The method further includes adjusting an amount of the solvent depending on a thickness of the three-dimensional object, filling in a recess or a concavity formed in the foamed material with a molding material; solidifying the molding material as a mold; and transferring a shape of the recess or the concavity to the molding material.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 20, 2014
    Applicant: RICOH COMPANY, LTD.
    Inventor: Satoshi Kitaoka
  • Patent number: 8881375
    Abstract: A method for manufacturing a disk drive head suspension having a plated load point dimple. An aperture is etched into the spring metal member. A photoresist mask having an opening with load point-defining side walls and a load point diameter is formed over a portion of a spring metal member including the aperture. Metal is plated onto the spring metal member and into the aperture in the opening to form a load point having the load point diameter on the spring metal member.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 11, 2014
    Assignee: Hutchinson Technology Incorporated
    Inventors: Zachary A. Pokornowski, Michael W. Davis
  • Patent number: 8883021
    Abstract: A method of forming of MEMS nanostructures includes a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A light reflecting layer is deposited over the substrate thereby covering the top surface and the sidewall surface of each mesa. A protection layer is formed over the light reflecting layer. An ARC layer is formed over the protection layer. An opening in a photo resist layer is formed over the ARC layer over each mesa. A portion of the ARC layer, the protection layer and the light reflecting layer are removed through the opening to expose the top surface of each mesa. The photo resist layer and the ARC layer over the top surface of each mesa are removed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Yi-Shao Liu, Allen Timothy Chang, Ching-Ray Chen, Yeh-Tseng Li, Wen-Hsiang Lin
  • Patent number: 8852448
    Abstract: A method for fabricating a 3D (three-dimensional) structure is disclosed to provide hydrophobicity to a surface of a 3D structure by using a dipping method in which a predetermined-shaped structure is immersed in a molten metal solution. The method includes: immersing a predetermined-shaped structure in a molten metal solution to coat a molten metal material on the surface of the predetermined-shaped structure; anodizing a metal base coated with the molten metal material; coating a polymer material on an outer surface of the metal-coated base to form a negative replica structure; covering an outer surface of the negative replica structure with an outer formation material; and removing the metal-coated base from the negative replica structure and the outer formation material.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 7, 2014
    Assignee: Postech Academy-Industry Foundation
    Inventors: Dong-Seob Kim, Kun-Hong Lee, Woon-Bong Hwang, Geun-Bae Lim, Hyun-Chul Park, Byeong-Joo Lee, Sang-Min Lee, Joon-Won Kim
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8840797
    Abstract: A unique and cost-effective method for producing a multilayer ceramic structure by using a first green film that contains a ceramic material, and the multilayer ceramic structure produced thereby. The method including the steps of: (a) producing at least one porous region in the first green film, the at least one porous region extending from the surface of the first green film; (b) applying a first layer, in sections, to the surface of the first green film, wherein one section of the first layer is located above the at least one porous region produced in step (a); (c) positioning at least one additional green film on the surface of the first green film, to which the first layer has been applied; (d) laminating the first green film and the at least one additional green film to form a green film composite; and (e) sintering the green film composite.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 23, 2014
    Assignees: Micro Systems Engineering GmbH, Technische Universitaet Wien
    Inventors: Thomas Haas, Dieter Schwanke, Achim Bittner, Ulrich Schmid
  • Publication number: 20140266484
    Abstract: Embodiments relate to MEMS resonator structures and methods that enable application of a maximum available on-chip voltage. In an embodiment, a MEMS resonator comprises a connection between a ground potential and the gap electrode of the resonator. Embodiments also relate to manufacturing systems and methods that are less complex and enable production of MEMS resonators of reduced dimensions.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Thoralf Kautzsch, Heiko Froehlich, Mirko Vogt, Maik Stegemann, Thomas Santa, Markus Burian
  • Patent number: 8828251
    Abstract: A method for finishing an exterior surface of an injection-molded product is provided, in which a metal layer is formed on the exterior surface of the injection-molded product, a photoresist layer is formed on the metal layer, a photomask is placed on the photoresist layer, light is projected onto the photomask, and remaining parts of the metal layer and the photoresist layer except for parts corresponding to a pattern formed on the photomask are removed by etching.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Bae Park, Pil-Woo Lee, Jong-Hwa Kim, Hak-Ju Kim, Jung-Won Cho
  • Patent number: 8828247
    Abstract: Provided is a method of manufacturing a circuit which includes: (a) providing a substrate made of a conductive material; (b) etching a first surface of the substrate excluding a region in which at least one via is to be formed; (c) etching a region of the etched first surface of the substrate in which an insulated portion of a first circuit is to be formed; (d) stacking a first insulation layer in spaces formed by the etching performed in operations (b) and (c); and (e) grinding a second surface of the substrate to expose the first insulation layer outward along with the first circuit, thereby forming a circuit board.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 9, 2014
    Assignee: MDS Co., Ltd.
    Inventors: Soon Chul Kwon, Sang Min Lee
  • Publication number: 20140247269
    Abstract: This disclosure provides systems, methods and apparatus for three-dimensional (3-D) through-glass via inductors. In one aspect, the through-glass via inductor includes a glass substrate with a first cavity, a second cavity, and at least two through-glass vias. The through-glass vias include metal bars that are connected by a metal trace. The metal bars and the metal trace define the inductor, and each cavity is at least partially filled with magnetic material. The magnetic material can include a plurality of particles having an average diameter of less than about 20 nm. The first cavity can be inside the inductor and the second cavity can be outside inductor. In some implementations, the first and the second cavity can be vias that extend only partially through the glass substrate.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 4, 2014
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventor: QUALCOMM MEMS Technologies, Inc.
  • Publication number: 20140234466
    Abstract: A method for making an imprint mold uses sidewall spacer line doubling, but without the need to transfer the sidewall spacer patterns into the mold substrate. A base layer is deposited on the mold substrate, followed by deposition and patterning of a mandrel layer into stripes with tops and sidewalls. A layer of spacer material is deposited on the tops and sidewalls of the mandrel stripes and on the base layer between the mandrel stripes. The spacer material on the tops of the mandrel stripes and on the base layer between the mandrel stripes is then removed. The mandrel stripes are then etched away, leaving stripes of sidewall spacer material on the base layer. The resulting mold is a substrate with pillars of sidewall spacer material patterned as stripes and extending from the substrate, with the sidewall spacers serving as the mold features for imprinting.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: HGST NETHERLANDS B.V.
    Inventors: He Gao, Jeffrey S. Lille, Lei Wan
  • Patent number: 8790520
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes punching a plurality of segments out of at least one sheet of substrate material to form a plurality of layers of the Z-directed component. A channel is formed through the substrate material either before or after the segments are punched. At least one of the formed layers includes at least a portion of the channel. A conductive material is applied to at least one surface of at least one of the formed layers. A stack of the formed layers is combined to form the Z-directed component.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 29, 2014
    Assignee: Lexmark International, Inc.
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 8778195
    Abstract: A method to fabricate an imprint mould in three dimensions including at least: a) forming at least one trench, of width W and depth h, in a substrate, thereby forming three surfaces including, a bottom of the at least one trench, sidewalls of the at least one trench, and a remaining surface of the substrate, called top of the substrate; b) forming alternate layers in the at least one trench, each having at least one portion perpendicular to the substrate, in a first material and in a second material which can be selectively etched relative to the first material; and c) selectively etching said portions of the layers perpendicular to the substrate.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 15, 2014
    Assignee: Commissariat a l' Energie Atomique
    Inventor: Stéfan Landis
  • Patent number: 8776336
    Abstract: A first metal film is formed on a piezoelectric substrate surface. A pattern of openings forming a first resist mask is formed in the first metal film. Portions of the metal film are removed by etching. The substrate is brought into contact with a first etching solution to remove substrate material to shape an outer surface. After, openings in the first metal film are filled in with a second metal film. The substrate is shaped into a first plurality of piezoelectric resonators using a second etching solution. Rough frequency adjustment is conducted by etching side surfaces of the substrate in increments and cutting a piezoelectric resonator from the substrate. The rough frequency adjustment continues until a measured oscillation frequency is within a predetermined frequency range. Electrode patterns then are formed for each one of the second plurality of piezoelectric resonators.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: July 15, 2014
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Takehiro Takahashi
  • Patent number: 8778196
    Abstract: Capsules and similar objects are made from materials having diamond (sp3) lattice structures, including diamond materials in synthetic crystalline, polycrystalline (ordered or disordered), nanocrystalline and amorphous forms. The capsules generally include a hollow shell made of a diamond material that defines an interior region that may be empty or that may contain a fluid or solid material. Some of the capsules include access ports that can be used to fill the capsule with a fluid. Capsules and similar structures can be manufactured by growing diamond on suitably shaped substrates. In some of these methods, diamond shell sections are grown on substrates, then joined together. In other methods, a nearly complete diamond shell is grown around a form substrate, and the substrate can be removed through a relatively small opening in the shell.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: July 15, 2014
    Assignee: Sunshell LLC
    Inventor: Victor B. Kley
  • Patent number: 8753526
    Abstract: The present application relates to a porous thin film having holes, wherein the holes are formed in the top part and/or the bottom part of the thin film and the holes are linked to the pores of the thin film; and the present invention also relates to a production method for a porous thin film having holes, comprising the use of a particle alignment layer as a mold.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: June 17, 2014
    Assignee: Industry-University Cooperation Foundation Sogang University
    Inventors: Kyung Byung Yoon, Hyun Sung Kim, Myunpyo Hong, Na Pi Ha
  • Patent number: 8748319
    Abstract: Embodiments of the invention may provide a method of printing one or more print tracks on a print support, or substrate, comprising two or more printing steps in each of which a layer of material is deposited on the print support according to a predetermined print profile. In each printing step, subsequent to the first step, each layer of material is deposited at least partially on top of the layer of material printed in the preceding printing step, so that each layer of printed material has an identical or different print profile with respect to at least a layer of material underneath. The method may further comprise depositing material in each printing step that is equivalent to or different from the material deposited in at least one of other the print layers.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Marco Galiazzo, Andrea Baccini, Giorgio Cellere, Luigi De Santi, Gianfranco Pasqualin, Tommaso Vercesi
  • Patent number: 8734656
    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 8726491
    Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: May 20, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Cheng T. Horng, Ru-Ying Tong
  • Patent number: 8721905
    Abstract: A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: May 13, 2014
    Assignees: Samsung Display Co., Ltd., SNU R & DB Fountdation
    Inventors: Se-Hwan Yu, Ji Seon Lee, Yoon Ho Khang, Kahp Yang Suh, Hyoung Sick Um, Jae Jun Chae, Sung Hun Lee
  • Patent number: 8714021
    Abstract: A catheter die is provided and includes a device layer defining a cavity and including a piezoresistive pressure sensor operably disposed proximate to the cavity and an insulator having an opening and being disposed on an upper surface of the device layer such that a portion of the piezoresistive pressure sensor is exposed through the opening. The catheter die further includes an insulation layer bonded to a lower surface of the device layer and first and second bond pads, the first bond pad being electrically coupled to the portion of the piezoresistive pressure sensor via the opening and the second bond pad being disposed on the insulation layer.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 6, 2014
    Assignee: Amphenol Thermometrics, Inc.
    Inventor: Sisira Kankanam Gamage
  • Patent number: 8709267
    Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Fei-Gwo Tsai, Kai-Wen Cheng
  • Publication number: 20140100346
    Abstract: A lithography method for forming nanoparticles includes patterning sacrificial material on a multilayer substrate. In some cases, the pattern is transferred to or into a removable layer of the multilayer substrate, and functional material is disposed on the removable layer of the multilayer substrate and solidified. At least a portion of the functional material is then removed to expose protrusions of the removable layer, and pillars of the functional material are released from the removable layer to yield nanoparticles. In other cases, the multilayer substrate includes the functional material, and the pattern is transferred to or into a removable layer of the multilayer substrate. The sacrificial layer is removed, and pillars of the functional material are released from the removable layer to yield nanoparticles.
    Type: Application
    Filed: January 31, 2011
    Publication date: April 10, 2014
    Applicant: MOLECULAR IMPRINTS, INC.
    Inventors: Frank Y. Xu, Sidlgata V. Sreenivasan
  • Publication number: 20140091057
    Abstract: A method of a forming a hollow, drug-eluting medical device includes utilizing a hollow wire having an outer member and a lumen of the outer member, and filling the lumen with a fluid to form a supported hollow wire. The supported hollow wire is shaped into a stent pattern. Openings are formed through the outer member. The supported hollow wire is processed to remove the fluid from the lumen of the outer member without adversely affecting the outer member, leaving the hollow wire shaped into a stent pattern. The lumen is filled with a biologically or pharmacologically active substance.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 3, 2014
    Applicant: Medtronic Vascular, Inc.
    Inventors: Kevin Mauch, Sean Ward, Aram Jamous
  • Patent number: 8685262
    Abstract: A nozzle plate containing multiple micro-orifices for the cascade impactor and a method for manufacturing the same are disclosed. The nozzle plate is formed by a series of semiconductor processes, including lithography, etching and electroplating. The nozzle plate comprises a plate body and a plurality of micro-orifices formed on the plate body. The orifice has a diameter which gradually expands in the direction away from the bottom of the plate body to achieve a smooth inner surface, allowing particles to pass therethrough smoothly without being clogged in the nozzle plate.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 1, 2014
    Assignee: National Chiao Tung University
    Inventors: Chuen-Jinn Tsai, Sheng-Chieh Chen, Hong-Dar Chen
  • Patent number: 8685263
    Abstract: Disclosed herein is a method of fabricating a cliché capable of preventing a printing roller from touching a bottom surface of the cliché. The method of fabricating the cliché includes forming a mask thin film pattern having a multilayer structure and a photoresist pattern on a base substrate, forming a resistant reinforcement inducing layer to cover the photoresist pattern, thereby transforming the photoresist pattern into a resistant reinforced photoresist pattern, and forming groove patterns having different depths from each other by etching the base substrate using the resistant reinforced photoresist pattern and the mask thin film pattern having the multilayer structure as masks.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 1, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jun-Hee Lee, Jeong-Hoon Lee
  • Publication number: 20140083670
    Abstract: A thermal transpiration device and method of making the same. The device includes a pair of membranes having predetermined thicknesses in order to provide the device with strength and rigidity. The thickness of a portion of each membrane is reduced in the area where thermal transpiration occurs in order to optimize the effectiveness of the thermal transpiration device without scarifying structural integrity of the device.
    Type: Application
    Filed: March 1, 2012
    Publication date: March 27, 2014
    Applicant: Game Changers, LLC
    Inventors: Andrew D. Zonenberg, Jason D. Sanchez, Piotr A. Garbuz
  • Patent number: 8673164
    Abstract: A method to fabricate nanoporous diamond membranes and a nanoporous diamond membrane are provided. A silicon substrate is provided and an optical lithography is used to produce metal dots on the silicon substrate with a predefined spacing between the dots. Selective seeding of the silicon wafer with nanodiamond solution in water is performed followed by controlled lateral diamond film growth producing the nanoporous diamond membrane. Back etching of the under laying silicon is performed to open nanopores in the produced nanoporous diamond membrane.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: March 18, 2014
    Assignee: UChicago Argonne, LLC
    Inventor: Anirudha V. Sumant
  • Patent number: 8673161
    Abstract: Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: March 18, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Christian R. Bonhôte, Jeffrey S. Lille, Ricardo Ruiz
  • Patent number: 8673788
    Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsiu Cheng, Shih-Hao Wu, Chih-Hsien Hsu, Chia-Chi Chung, Wei-Yueh Tseng
  • Patent number: 8668833
    Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 11, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of Singapore
    Inventors: Han Guan Chew, Fei Zheng, Wee Kiong Choi, Tze Haw Liew
  • Publication number: 20140061153
    Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.
    Type: Application
    Filed: August 6, 2013
    Publication date: March 6, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Yi-Li Hsiao
  • Patent number: 8664022
    Abstract: A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 4, 2014
    Assignee: Episil Technologies Inc.
    Inventors: Le-Sheng Yeh, Cheng-I Chien
  • Patent number: 8652342
    Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kyung-Woo Lee, Jin-Sung Kim, Joo-Byoung Yoon, Yeong-Cheol Lee, Sang-Jun Park, Hee-Kyeong Jeon
  • Patent number: 8647520
    Abstract: The present invention relates to a method and an arrangement for restoring strength and wear resistant of a metallic matrix ceramic (1) comprising a metallic binder (2) and ceramic filler (3) particles, which metallic matrix ceramic (1) has been exposed for long term high temperature and pressure cycling, for example in a gas exhaust nozzle (6), whereby micro cracks (4) are developed in the outer layer (5) of the metallic binder (2) According to the invention this is achieved by virtue of the fact that the outer layer (5) of the metallic binder (2), partly or fully, is removed from the MMC part (1) by a chemical operation, where after the outer layer (5) is compressed by a compression operation for achieving a dense outer layer (5), in which filler (3) particles are close to each other.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 11, 2014
    Assignee: SAAB AB
    Inventor: Håkan Strömberg
  • Publication number: 20140034132
    Abstract: Microfluidic devices having superhydrophilic bi-porous interfaces are provided, along with their methods of formation. The device can include a substrate defining a microchannel formed between a pair of side walls and a bottom surface and a plurality of nanowires extending from each of the side walls and the bottom surface. For example, the nanowires can be silicon nanowires (e.g., pure silicon, silicon oxide, silicon carbide, etc., or mixtures thereof).
    Type: Application
    Filed: March 14, 2013
    Publication date: February 6, 2014
    Applicant: UNIVERSITY OF SOUTH CAROLINA
    Inventors: Chen Li, Fanghao Yang, Xianming Dai, Yan Tong
  • Patent number: 8623228
    Abstract: The invention relates to a gear train (51, 51?) including an arbour (53, 53?) a first end of which is fitted with an integral collar (52, 52?), a first wheel set (55, 55?) made of micro-machinable material being fitted onto the second end of the arbour (53, 53?). According to the invention, the gear train (51, 51?) includes a second wheel set (57, 57?) made of micro-machinable material, which is independent of the movements of said first wheel set and which includes an aperture (58, 58?) whose wall is mounted opposite said arbour so that the second wheel set (57, 57?) is freely mounted on said first end of the arbour (53, 53?).
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: January 7, 2014
    Assignee: Nivarox-FAR S.A.
    Inventors: Pierre Cusin, Jean-Philippe Thiebaud
  • Patent number: 8617406
    Abstract: The invention relates to a device for the actively-controlled deposition of microdrops of biological solutions. The inventive device includes at least one flat silicon lever comprising a central body and an end area which forms a point, a slit or groove being disposed in said point. The invention is characterized in that it also comprises at least one metallic track which is disposed on one face of the central body and which runs alongside said slit or groove at least partially. The invention also relates to a method of producing the inventive device and a method for the active-controlled deposition and sampling of microdrops of biological solutions using said device.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: December 31, 2013
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Christian Bergaud, Matthieu Guirardel, Pascal Belaubre, Benoit Belier, Jean-Bernard Pourciel
  • Publication number: 20130342977
    Abstract: A method for processing a housing for devices such as electronic devices. A hairline is formed on an inner surface of an inmold mold. In addition, a hairline is formed on an inmold film. The inmold film is positioned inside the inmold mold and a housing representing the hairline of the inmold mold and the hairline of the inmold film together is formed using inmold injection molding.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 26, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min-Su CHANG, Soon-Ho HAN
  • Publication number: 20130343524
    Abstract: A method for producing a structure includes the steps of etching a first substrate of an integrated member including, in sequence, the first substrate, an etching stop layer, and a seed layer, from a surface of the first substrate opposite the surface adjacent to the etching stop layer to form a hole or a plurality of gaps in the first substrate in such a manner that part of a surface of the etching stop layer is exposed, partially etching the etching stop layer from the surface of the etching stop layer exposed to expose part of a surface of the seed layer, and forming a metal member by plating using the seed layer as a seed to charge a metal into at least part of the hole or the gaps.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 26, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Takayuki Teshima
  • Patent number: 8613862
    Abstract: A manufacturing method, for a liquid discharge head substrate that includes a silicon substrate in which a liquid supply port is formed, includes the steps of: preparing the silicon substrate, on one face of which a mask layer, in which an opening has been formed, is deposited; forming a first recessed portion in the silicon substrate, so that the recessed portion is extended through the opening from the one face of the silicon substrate to the other, reverse face of the silicon substrate; forming a second recessed portion by performing wet etching for the substrate, via the first recessed portion, using the mask layer; and performing dry etching for the silicon substrate in a direction from the second recessed portion to the other face.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: December 24, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuhiro Asai, Hirokazu Komuro, Satoshi Ibe, Takuya Hatsui, Shimpei Otaka, Hiroto Komiyama, Keisuke Kishimoto
  • Patent number: 8614143
    Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: December 24, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Makarand R. Kulkarni, Deepak A. Ramappa
  • Patent number: 8609221
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald Westmoreland, Gurtej Sandhu
  • Publication number: 20130330835
    Abstract: Devices and methods for gravimetric sensing are disclosed. A gravimetric sensor includes a piezoelectric resonator and an encapsulating layer formed on the surface of the resonator. The encapsulating layer defines a channel within the encapsulating layer on the surface of the resonator. The sensor is fabricated by forming a piezoelectric resonator, forming a sacrificial layer on a surface of the piezoelectric resonator, forming an encapsulating layer over the sacrificial layer on the resonator, and etching the sacrificial layer to remove the sacrificial layer and form a channel on the surface of the resonator. The sensor is used by supplying the liquid to the channel of the gravimetric sensor, operating the piezoelectric resonator, detecting a change in a resonant frequency of the resonator, and determining a presence of the analyte in the liquid from the change in resonant frequency of the resonator.
    Type: Application
    Filed: November 1, 2011
    Publication date: December 12, 2013
    Applicant: The Trustees of the University of Pennsylvania
    Inventors: Chiara Zuniga, Matteo Rinaldi, Gianluca Piazza
  • Publication number: 20130330394
    Abstract: Composites, constructs and implants comprising a non-resorbable polymer, such as polyetheretherketone (PEEK), having structure of interconnected struts, which may be coralline. Composites may comprise a first phase comprising a ceramic; and a second phase comprising a non-resorbable polymer; wherein each of the first and second phases have an interconnected strut structure and are substantially continuous through the composite. Implants may also comprise a non-porous component containing the non-resorbable polymer that is contiguous with a surface of the core, a surface of the porous layer (if present), or both. Methods are also provided comprising infusing a porous ceramic body, having a plurality of interconnected channels, with a non-resorbable polymer.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Inventors: Michael Ponticiello, Bradford J. Coale, Paul D'Antonio, Joseph M. Hernandez
  • Publication number: 20130327741
    Abstract: A method for producing an alumina template of nanorods, the alumina template, and the nanorods are provided for overcoming the problems of the conventional alumina template having anodic aluminum oxide that may be peeled off from a substrate or forming a non-conductive oxide easily, and the alumina template includes a conductive substrate composed of an active metal and an inert metal, so that the alumina template can be attached onto the active metal and inert metal at the same time, and the active metal can be used for securing the alumina template and supporting the alumina template on the inert metal, and the anodic aluminum oxide attached onto the inert metal can be used for providing a better conductivity, such that a stable and highly conductive alumina template can be produced.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 12, 2013
    Applicant: SOUTHERN TAIWAN UNIVERSITY
    Inventors: Hsyi-En CHENG, Bo-Jiun YEH
  • Publication number: 20130306595
    Abstract: A method of manufacturing a three-dimensional nanochannel device is provided. In the method, a first insulation layer is formed on a substrate, a first opening is formed in the first insulation layer, and a patterned photoresist is formed on the first insulation layer. The patterned photoresist includes at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer. Afterwards, the first insulation layer is etched and the substrate is also continued to be etched by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer. Thereafter, the patterned photoresist is removed, and a second insulation layer is formed on a surface of the substrate.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 21, 2013
    Applicant: Inndustrial Technology Research Institute
    Inventors: Liang-Ju Chien, Chi-Han Chiou
  • Patent number: 8578594
    Abstract: A process for fabricating a magnetic recording transducer for use in a data storage system comprises providing a substrate, an underlayer and a first nonmagnetic intermediate layer deposited to a first thickness on and in contact with the underlayer, performing a first scanning polishing on a first section of the first intermediate layer to planarize the first section of the first intermediate layer to a second thickness, providing a main pole in the planarized first section of the first intermediate layer, providing a first pattern of photoresist on and in contact with the first section of the first intermediate layer, the pattern comprising an aperture to define a side shield trench, performing a wet etch to remove at least a portion of the first intermediate layer thereby exposing at least one of the plurality of main pole sides, and depositing side shield material in the side shield trench.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 12, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Ming Jiang, Ronghui Zhou, Guanghong Luo, Masahiro Osugi, Danning Yang
  • Patent number: 8574444
    Abstract: A method of fabricating a multilayer printed circuit board includes forming a first circuit-forming pattern and a via-forming pattern on a first carrier, and forming a first insulation layer; repeatedly forming inner circuit patterns and inner insulation layers over the first insulation layer by forming circuit-forming patterns and imprinting, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the first circuit-forming pattern and the second circuit-forming pattern respectively into the first insulation layer and a second insulation layer; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: November 5, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Ryoichi Watanabe