Mechanically Shaping, Deforming, Or Abrading Of Substrate Patents (Class 216/52)
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Patent number: 6117347Abstract: A method of separating a wafer into individual die is disclosed. The wafer includes a substrate with organic thin-film multiple layers. A portion of the organic multiple layers is etched along a scribe line with excimer laser to form a groove to expose a portion of the substrate before sawing the substrate along the scribe line with a saw blade. Plasma etching or ion beam etching or sand blasting is an alternative to the excimer laser.Type: GrantFiled: July 10, 1997Date of Patent: September 12, 2000Assignee: NEC CorporationInventor: Hisashi Ishida
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Patent number: 6110393Abstract: A class of epoxy bond and stop etch (EBASE) microelectronic fabrication techniques is disclosed. The essence of such techniques is to grow circuit components on top of a stop etch layer grown on a first substrate. The first substrate and a host substrate are then bonded together so that the circuit components are attached to the host substrate by the bonding agent. The first substrate is then removed, e.g., by a chemical or physical etching process to which the stop etch layer is resistant. EBASE fabrication methods allow access to regions of a device structure which are usually blocked by the presence of a substrate, and are of particular utility in the fabrication of ultrafast electronic and optoelectronic devices and circuits.Type: GrantFiled: April 23, 1998Date of Patent: August 29, 2000Assignee: Sandia CorporationInventors: Jerry A. Simmons, Mark V. Weckwerth, Wes E. Baca
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Patent number: 6110391Abstract: A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, the peripheral portion of a device-fabricating substrate is ground to a predetermined thickness, and an unjoined portion at the periphery of the device-fabricating substrate is completely removed through etching. The device-fabricating substrate is then ground and/or polished in order to reduce the thickness of the device-fabricating substrate to a desired thickness. The step of grinding the peripheral portion of the device-fabricating substrate to a predetermined thickness is performed by relative and radial movement of a grinding stone from the peripheral portion of the substrate toward the center thereof.Type: GrantFiled: December 29, 1997Date of Patent: August 29, 2000Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Tokio Takei, Susumu Nakamura, Kazushi Nakazawa
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Patent number: 6083837Abstract: Metallic elements such as leads for connection to a semiconductor chip are made by embossing a metal sheet to form thin and thick regions, then etching or otherwise removing metal from the sheet in a nonselective removal process and arresting the removal process when the thin regions are removed but before the thick regions are removed. A base material may be applied to the metal sheet to form a dielectric layer before the removal step, so that the metallic leads left after the removal step are supported by the dielectric layer.Type: GrantFiled: December 12, 1997Date of Patent: July 4, 2000Assignee: Tessera, Inc.Inventor: Marcus J. Millet
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Patent number: 6066562Abstract: A method of fabricating a silicon semiconductor discrete wafer is disclosed that assures excellent finishing accuracy and productivity. The method for fabricating a discrete wafer having a double-layer structure including an impurity diffused layer at one side and an impurity non-diffused layer at the opposite side includes cutting a wafer, having one of the impurity diffused layers formed on both surfaces of the silicon semiconductor wafer and having an oxide film formed on the surface of the diffused layer, into two pieces at the center of thickness with an ID saw slicing machine. Then, both surfaces of the cutting surface are ground to a predetermined thickness with a surface grinding machine, and the grinding surfaces are lapped with abrasive grains having a count of at least #2000 and no more than #6000. The processing surface is wet-etched as the final processing.Type: GrantFiled: July 22, 1997Date of Patent: May 23, 2000Assignee: Naoetsu Electronics CompanyInventors: Hisashi Ohshima, Tsutomu Satoh
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Patent number: 6045715Abstract: Method of providing a pattern of apertures and/or cavities in, for example, a glass duct plate of a plasma-addressed liquid crystal display, in which first a mechanical treatment is performed (for example, by means of powder blasting) and then a wet-chemical etching treatment is performed to render the walls of the ducts microscopically less rough so that the optical disturbance is reduced and the glass becomes clearer again.Type: GrantFiled: November 19, 1997Date of Patent: April 4, 2000Assignee: U.S. Philips CorporationInventors: Gijsbertus A. C. M. Spierings, Poul K. Larsen, Jan B. P. H. Van der Putten, Johannes M. M. Busio, Frederik H. In 'T Veld, Lambertus Postma
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Patent number: 6042736Abstract: The present invention provides a method for preparing samples for microscopic examination that requires a glass slide to be laminated to a sample substrate by an adhesive layer for polishing in a sample polishing process. A cavity can be first formed in the surface of the substrate by a focused ion beam technique to reveal a characteristic feature which needs to be examined. A wax-based material is then used to fill the cavity and to protect the characteristic feature before an adhesive layer is applied on top of the substrate for bonding a glass slide to the substrate. After the sample is sectioned in the polishing process to reveal a new cross-section that contains the characteristic feature, the protective coating of the wax-based material can be removed by a suitable solvent such that the characteristic feature is ready for microscopic examination. A suitable wax-based material can be a wax that is similar to a candle wax which can be easily removed by acetone.Type: GrantFiled: November 17, 1997Date of Patent: March 28, 2000Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Lee Chung
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Patent number: 6033532Abstract: A method of forming an oxide film over the substrate of an electronic device. In one embodiment, a first metal oxide film layer is deposited on the substrate of the electronic device by bias sputtering. Then, a second metal oxide film layer is deposited by ion beam sputtering on the first metal oxide film layer. In another embodiment, a first metal oxide film layer is deposited on the substrate of the electronic device by ion beam sputtering. Then, a second metal oxide film layer is deposited by bias sputtering on the first metal oxide film layer. In yet another embodiment, a first metal oxide film layer having a first degree of purity is deposited on the substrate of the electronic device. Then, a second metal oxide film layer having a second degree of purity is deposited on the first metal oxide film layer. The first degree of purity is different than the second degree of purity.Type: GrantFiled: February 27, 1997Date of Patent: March 7, 2000Assignee: Read-Rite SMI CorporationInventor: Hiroaki Minami
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Patent number: 6033580Abstract: On a substrate, a lower pole is formed being embedded in a protective film on which a gap layer is formed. On this gap layer, a first upper pole is formed facing the lower pole. A protective film is formed coplanar to the upper surface of the first upper pole. On this protective film, a coil made of a plurality of coil layers is formed being embedded in an insulating film. On the insulating film, an upper core layer is formed whose tip portion constitutes a second upper pole stacked upon the first upper pole and magnetically coupled thereto. The first upper pole formed before the coil is formed and the second upper pole formed after the coil is formed, constitute an upper pole.Type: GrantFiled: December 30, 1997Date of Patent: March 7, 2000Assignee: Yamaha CorporationInventors: Shigeru Shouji, Shuichi Sawada
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Patent number: 6030514Abstract: A target for sputtering is subjected to a surface treatment process and special packaging after target manufacture for improved sputtering performance and process and yield by reducing particulates. The sputtering target is first surface treated to remove oxides, impurities and contaminants. The surface treated target is then covered with a metallic enclosure and, optionally, a passivating barrier layer. The metallic enclosure protects the target surface from direct contact with subsequently employed packaging material such as plastic bags, thereby eliminating sources of organic materials during sputtering operations. The surface treatment of the target removes deformed material, smearing, twins, or burrs and the like from the target surface, reducing "burn-in" or sputter conditioning time prior to production sputtering of thin films.Type: GrantFiled: May 2, 1997Date of Patent: February 29, 2000Assignees: Sony Corporation, Materials Research CorporationInventors: John A. Dunlop, Michael Goldstein, Gerald B. Feldewerth, Cari Shim, Stephan Schittny
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Patent number: 5980765Abstract: Using a newly developed composite ceramics material suited for balls of ball-point pens, a method of manufacturing composite ceramics balls for ball-point pens that have affinity for both oil-based ink and water-based ink is provided. In this method, the composite ceramics, whose main components are mullite (3Al.sub.2 O.sub.3 .multidot.2SiO.sub.2) and zirconia (ZrO.sub.2) at the ratio of 50-95% to 5-50% by weight, is polished into mirror-finished balls and then chemical processing or physical processing is performed on the ball surfaces to form indentations in the ball surfaces. The chemical processing is preferably an etching using hydrofluoric acid, and the degree of indentations can be controlled by changing the concentration of hydrofluoric acid and the duration of etching.Type: GrantFiled: September 30, 1997Date of Patent: November 9, 1999Assignee: Ohto Kabushiki KaishaInventors: Takao Machida, Tooru Ishijima
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Patent number: 5980764Abstract: A gas injecting gadget or wafer-mounting susceptor, made of a chemical composition comprising 59.8-69.8% by weight of nickel, 25-35% by weight of copper, a valance weight of aluminum, cobalt, manganese, titanium or the combinations thereof, and E trace amount of inevitable impurities, is produced by a method comprising the steps of: a rough cutting process in which the substance is roughly cut and surface-processed; a precise cutting process in which the roughly processed substance is precisely processed in three stages comprising rough process, finishing process and shaping process; a holing process in which a number of fine holes are formed on the precisely processed substance by a drilling process and chips are removed by a reaming process; an abrasion process in which the substance with holes are abraded by a wet abrading process and a belt polishing process; and a washing and inspecting process.Type: GrantFiled: October 10, 1996Date of Patent: November 9, 1999Inventor: Young Sei Yoon
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Patent number: 5981393Abstract: A method of forming electrode at the end surface of chip array resistors utilizes the vacuum metallization technology such as sputtering evaporating deposition or ion implanting accompanying a metal mask for forming electrode at the end surfaces of chip array resistors. A blank base can be used instead of a punch-through base which has to be used in conventional technology. The method disclosed in the present invention may greatly increase the productivity of the electrodes, and at the same time, the variation of resistance value of the chip array resistor is minimized and the product quality may be improved.Type: GrantFiled: September 29, 1997Date of Patent: November 9, 1999Assignee: Cyntec Co., Ltd.Inventors: Shih-Chang Liao, Duen-Jen Cheng
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Patent number: 5976390Abstract: A minute structure such as a cantilever 11 is formed on a silicon substrate 10 and heated by irradiating a laser beam to a part of the cantilever 11, by which the cantilever 11 is bent. The two bent cantilevers 11 are inserted into through holes 14 in a crystal substrate 10 formed in advance, and the tip end portions 15 thereof are heated. The heared tip end portions 15 become thicker and at the same time shorter, so that the crystal substrate 12 can be fixed to the silicon substrate 10 without play. By heating a part of the minute structure by such a method, plastic deformation is produced, so that bending and deforming can be performed. Thereby, a three-dimensional micromachined structure is constructed and assembled.Type: GrantFiled: December 19, 1996Date of Patent: November 2, 1999Assignee: Seiko Instruments Inc.Inventor: Hiroshi Muramatsu
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Patent number: 5961849Abstract: A miniature mounting device on which elements such as optical filters can be accurately held. The device includes a substrate having a machined groove with an enlarged opening for receiving the element, and an overlayer extends at least partially over the groove to clamp the element.Type: GrantFiled: April 6, 1998Date of Patent: October 5, 1999Assignee: Cambridge Consultants Ltd.Inventors: Roger Mark Bostock, Peter Gravesen, Robert Jones, David Frank Moore, Kasper Mayntz Paasch
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Patent number: 5954975Abstract: Novel slurries for the chemical mechanical polishing of thin films used in integrated circuit manufacturing. A tungsten slurry of the present invention comprises an oxidizing agent, such as potassium ferricyanide, an abrasive such as silica, and has a pH between two and four. The tungsten slurry of the present invention can be used in a chemical mechanical planarization process to polish back a blanket deposited tungsten film to form plugs or vias. The tungsten slurry can also be used to polish copper, tungsten silicide, and titanium nitride. A second slurry, which is a 9:1 dilution of the tungsten slurry is ideal for chemical mechanical polishing of titanium nitride films. A third slurry of the present invention comprises a fluoride salt, an abrasive such as silica and has a pH.ltoreq.8. The third slurry can be used to polish titanium films.Type: GrantFiled: February 7, 1997Date of Patent: September 21, 1999Assignee: Intel CorporationInventors: Kenneth C. Cadien, Daniel A. Feller
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Patent number: 5952243Abstract: A method for forming a gap-filled, planarization structure of dielectric materials on a substrate topography useful for forming microelectronic devices. A dielectric material is first deposited as continuous, dry dielectric layer, preferably a SOG layer. Then the dielectric layer is partially removed by chemical-mechanical polishing (CMP). The chemical and mechanical properties of the structure can be chosen by varying the composition of the SOG layer and the subsequent CMP conditions.Type: GrantFiled: June 24, 1996Date of Patent: September 14, 1999Assignee: AlliedSignal Inc.Inventors: Lynn Forester, Dong K. Choi, Reza Hosseini
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Patent number: 5935454Abstract: A method of fabricating nanometric structures on a substrate by dry etching includes setting the substrate at a temperature at which condensation of etching gas products of etching gas decomposed, recombined and reacted, or products of reactions between the etching gas and substrate material starts to occur, forming condensates at specific locations on the substrate. The condensates form an etching mask for the dry etching process.Type: GrantFiled: November 27, 1996Date of Patent: August 10, 1999Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & IndustryInventors: Tetsuya Tada, Toshihiko Kanayama
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Patent number: 5934965Abstract: Positional accuracy of apertures in nonplanar electrodes is improved with a new fabrication method. This method precedes process steps which establish a photoresist pattern that defines apertures with deformation steps which produce a nonplanar electrode. Thus, the deformation steps do not have an opportunity to spatially alter the photoresist pattern. The improved positional accuracy enhances the performance and lifetime of ion thrusters which include nonplanar electrodes that are fabricated with this process.Type: GrantFiled: April 11, 1997Date of Patent: August 10, 1999Assignee: Hughes Electronics CorporationInventor: John R. Beattie
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Patent number: 5922215Abstract: A method for making anode foil plates for use with layered electrolytic capacitors and capacitors made with such plates. A high purity aluminum foil is provided for generation of anode foil plates. Sheets of the foil are highly etched to provide a very high surface area. Following the etch process, the foil is partially cut or punched into plates from the etched sheets in the general shape of the finished capacitor housing with a portion remaining connected to the supporting foil. The supporting foil with the partially punched-out etched plates are subjected to a forming process by applying a voltage to the plates in the presence of an electrolyte to provide formed anode foil plates with edges which do not have to be reformed during capacitor aging and which do not have any particulates at cut edges. The formed anode plates are layered with cathode plates and separators in a capacitor housing with an electrolyte to provide a finished capacitor.Type: GrantFiled: October 15, 1996Date of Patent: July 13, 1999Assignee: Pacesetter, Inc.Inventors: Benjamin D. Pless, William H. Elias, Sam Parler, J. Scott McCall
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Patent number: 5919378Abstract: A process for manufacturing photopolymer blocks, which are first exposed to UVA radiation and mounted on printing cylinders to in combination form a printing sleeve for carrying out printing in flexography and in dry offset, includes a series of automated steps for manufacturing the printing sleeves. A device for implementing the process includes a series of stations, arranged in line, one after the other, including a storage magazine for receiving the exposed printing sleeves, a solvent-vapor lock, an etching device, a drying device and a storage station for receiving the completed printing sleeves.Type: GrantFiled: June 30, 1997Date of Patent: July 6, 1999Assignees: Photomeca/Egg, Du Pont De Nemours (Germany) GmbHInventor: Mario Ferrante
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Patent number: 5916738Abstract: Disclosed is a photosensitive resin composition suitable as a resist material against sandblasting for pattern-wise engraving of the surface of a body after photolithographic patterning, which comprises: (a) a urethane compound having a (meth)acrylate group at the molecular end, which is obtained from a polyether or polyester compound having a hydroxy group at the molecular chain end, a diisocyanate compound and a (meth)acrylate compound having a hydroxy group; (b) an alkali-soluble polymeric compound having an acid value in the range from 50 to 250 mg KOH/g; and (c) a photopolymerization initiator.Type: GrantFiled: February 4, 1998Date of Patent: June 29, 1999Assignees: Matsushita Electronics Corporation, Tokyo Ohka Kogyo Co., Ltd.Inventors: Hiroshi Takehana, Tetsuo Yamamoto, Hiroyuki Obiya, Ryuma Mizusawa
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Patent number: 5916456Abstract: A surface of a diamond, particularly a diamond window, is treated by depositing a layer of a carbide-forming metal such as titanium, on the surface and thereafter removing the layer. The treatment has the effect of passivating stress surface defects in the diamond such as grain boundaries, twin defects and polishing damage.Type: GrantFiled: September 9, 1996Date of Patent: June 29, 1999Assignee: Diamanx Products LimitedInventors: Christopher John Howard Wort, Charles Gerard Sweeney, Andrew John Whitehead
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Patent number: 5916655Abstract: The present invention relates to a highly smooth zirconia-containing disk substrate produced by polishing a defect-free surface with fine diamond and/or alumina.Type: GrantFiled: October 16, 1996Date of Patent: June 29, 1999Assignee: Saint-Gobain/Norton Industrial Ceramics CorporationInventor: Oh-Hun Kwon
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Patent number: 5914274Abstract: A bi-layer bump comprises a base layer composed of sprayed aluminum thick film having a thickness of about 20 .mu.m formed to cover the periphery of the passivation film formed on each pad electrode, a surface layer composed of sprayed copper thick film having a thickness of about 30 .mu.m formed on the base layer. According to the above-mentioned structure, a substrate on which bumps are formed which has an excellent electric property and connecting reliability, wherein an interlayer insulating layer, an active layer and a multi-layer wiring can be provided under the pad electrode can be obtained.Type: GrantFiled: April 1, 1998Date of Patent: June 22, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazufumi Yamaguchi, Tsutomu Mitani, Mitsuo Asabe
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Patent number: 5906753Abstract: A method of manufacturing an optical semiconductor device including forming an optical waveguide on a substrate and forming an alignment mark on the substrate simultaneously with the optical waveguide. The alignment marks do not transmit infrared light and, when the substrate is mounted on an infrared transmissive submount, precise alignment can be achieved by observing transmitted light. Thus, the optical semiconductor device including the substrate is soldered at the desired location.Type: GrantFiled: October 30, 1997Date of Patent: May 25, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshitaka Aoyagi, Yasunori Miyazaki
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Patent number: 5894373Abstract: A method for use in mass-producing, from a plane sheet of metal, a three-dimensional structure consisting of plane mirrors and plane structural members, said three-dimensional structure of a type in which each mirror or structural member has at least one edge that is collinear with an edge of another mirror or structural member, whereby said three-dimensional structure can be formed by bending the sheet of metal along various edges, the method including the steps of: producing masks bearing images defining the location of bending grooves, shallow grooves, separation grooves and holes for indexing pins, selecting a mask, applying a coating of photoresist to both sides of the sheet of metal, transferring the images on the selected mask to the coating of photoresist, removing those portions of the coating of photoresist to which the images were transferred, etching the sheet of metal where the portions of the coating of photoresist were removed, removing the remaining photoresist from the sheet of metal, and repType: GrantFiled: September 24, 1997Date of Patent: April 13, 1999Assignee: Jaesent Inc.Inventor: Jacob Y. Wong
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Patent number: 5891808Abstract: The present invention provides a method of fabricating a die seal. The die seal comprises a buffer area being adjacent to a die, a buffer space being adjacent to a scribe line, and a seal ring located between the buffer area and the buffer space. The seal ring is stacked by at least one metal layer and at least one dielectric layer. A passivation layer is formed and covers entire the die seal. The method comprises forming an amorphous silicon film on a top metal layer prior to the step of forming the passivation layer, and removing the dielectric layer on the buffer space by applying the amorphous silicon film as an etch stop layer in the step of etching the passivation layer to enhance the robustness of the die seal from damage by a lateral stress when a wafer is sawed. When the dielectric layer is made of SiO.sub.2, a plasma containing CF.sub.4 and H.sub.2. can be utilized in the step of etching the passivation layer. Because the plasma has an extremely high etching selectivity ratio, the SiO.sub.Type: GrantFiled: June 6, 1997Date of Patent: April 6, 1999Assignee: Winbond Electronics Corp.Inventors: Gene Jiing-Chiang Chang, Chun-Cho Chen
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Patent number: 5885470Abstract: Microfluidic devices are provided for the performance of chemical and biochemical analyses, syntheses and detection. The devices of the invention combine precise fluidic control systems with microfabricated polymeric substrates to provide accurate, low cost miniaturized analytical devices that have broad applications in the fields of chemistry, biochemistry, biotechnology, molecular biology and numerous other fields.Type: GrantFiled: April 14, 1997Date of Patent: March 23, 1999Assignee: Caliper Technologies CorporationInventors: John Wallace Parce, Michael R. Knapp, Calvin Y. H. Chow, Luc Bousse
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Patent number: 5885471Abstract: The present invention relates to accelerometer assemblies for implantable medical devices such as pacemakers, IPGs, PCDs, defibrillators, ICDs and the like. The accelerometer assembly of the present invention comprises a beam that deflects in response to being subjected to an externally provided force. Deflection of the beam generates a voltage in a piezoelectric material disposed in the assembly. At least one stop is provided to limit the vertical range of motion through which the beam may deflect to prevent failure, fracturing or breakage of the beam resulting from excessive deflection of the beam that might otherwise occur were the stop not present.Type: GrantFiled: July 31, 1997Date of Patent: March 23, 1999Assignee: Medtronic, Inc.Inventors: David A. Ruben, Mark E. Henschel, Larry R. Larson, Roy Inman, Louis A. Molinari, Joan A. O'Gara, Ronald F. Messer
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Patent number: 5885469Abstract: An apparatus for retaining a workpiece and a method of fabricating same. The apparatus contains an electrostatic chuck having a workpiece support surface. The workpiece support surface has protruded regions and non-protruded regions, where a total surface area of the protruded regions is less than a total surface area of the non-protruded regions. The apparatus contains a pedestal having a surface that supports a flex circuit. The topography of the chuck is formed by either machining the surface of the pedestal prior to adhering and conforming the flex circuit to the surface or sculpting the surface of an electrode within the flex circuit.Type: GrantFiled: November 5, 1996Date of Patent: March 23, 1999Assignee: Applied Materials, Inc.Inventors: Arnold Kholodenko, Alexander Veytser
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Patent number: 5882539Abstract: A wafer processing method which can polish the chamfered portion of a wafer quickly, is disclosed. The processing method comprises the steps of: chamfering a peripheral portion of a wafer obtained by slicing an ingot, by grinding; lapping the wafer; etching the chamfered or lapped wafer; thereafter honing the entirety of the chamfered peripheral portion of the wafer by using a grinding stone while applying a predetermined load to the grinding stone; and thereafter polishing the entirety of the chamfered peripheral portion and the front and rear surfaces of the wafer.Type: GrantFiled: August 14, 1996Date of Patent: March 16, 1999Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumihiko Hasegawa, Yasuyoshi Kuroda, Masayuki Yamada
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Patent number: 5875549Abstract: A method of producing numerous small passages within a turbomachinery component is disclosed. The method comprises providing a turbomachinery component substrate having grooves, filling the grooves with a filler, condensing a vapor onto the surfaces of the substrate and the filler, and removing the filler. The method enables the formation of small passages located close to the component surface without the low yield rate associated with conventional methods of turbomachinery component production. Turbomachinery components having numerous small passages for cooling are also disclosed. Such passages may diminish fluid pressure losses of a cooling medium passing therethrough.Type: GrantFiled: March 17, 1997Date of Patent: March 2, 1999Assignee: Siemens Westinghouse Power CorporationInventor: Barry Lee McKinley
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Patent number: 5863449Abstract: This invention relates to a method of making fiber optic interferometers. First, a plurality of optical fibers are bundled and placed into a sleeve. The bundle is then encased in the sleeve and the fiber ends are cut and polished. An area of cladding is stripped back from the polished fiber ends and layers of material are deposited on the fiber ends. These layers of material have varying indexes of refraction and form a grating. The bundle of optical fibers is then removed from encasing in the sleeve.Type: GrantFiled: March 29, 1996Date of Patent: January 26, 1999Assignee: The Whitaker CorporationInventor: Dimitry G. Grabbe
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Patent number: 5863708Abstract: A method of making a dielectric substrate array for conducting a plurality of reactions in parallel in a number of wells, the method comprising: forming a first passage and a second passage each extending through a dielectric substrate, the substrate having a first surface and an opposing second surface; forming a plurality of channels on said first or second surface, including a first channel, a second channel, a third channel and a fourth channel on the substrate, wherein the first channel is on the first surface and intersects with the first passage, wherein the second channel is on the second surface and intersects with both of the first passage and the second passage, wherein the third channel is on the first surface and intersects with the second passage, wherein the fourth channel is on the first surface and is located between the outlets of the first and second passage at the first surface, and wherein (a) the connected first channel, first passage, second channel, second passage and third channel defType: GrantFiled: January 27, 1997Date of Patent: January 26, 1999Assignee: Sarnoff CorporationInventors: Peter John Zanzucchi, Satyam Choudary Cherukuri, Sterling Edward McBride, Amrit Kaur Judd
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Patent number: 5858254Abstract: A multilayer circuit fabrication approach and circuitized substrate are presented wherein at least two conductive layers are formed over a substrate. The conductive layers are separated by a first dielectric layer and the structure is encapsulated with a second dielectric layer. The first dielectric layer includes open areas exposing a portion of the underlying support structure aligned to those areas where contact points are to reside in the second conductive layer. The first dielectric layer comprises a blanket dielectric layer such that recesses are defined in the upper surface thereof aligned to the open areas of the first conductive layer. The second conductive layer thus resides in two planes, both of which comprise planes other than a plane of the first conductive layer. A plurality of openings can be simultaneously formed to expose contact points in both the first and second conductive layers.Type: GrantFiled: January 28, 1997Date of Patent: January 12, 1999Assignee: International Business Machines CorporationInventors: Peter Lynn Balzer, Robert Lee Lewis, Robert David Sebesta
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Patent number: 5857257Abstract: A method of manufacturing a magnetic head suspension having a circuit wiring pattern member such that a circuit wiring pattern is formed integral with a suspension via a flexible insulating base member, comprising the steps of: preparing a laminated plate composed of a flexible insulating base member (2), a conductive layer (6 or 3) formed on one surface thereof, and an elastic metal layer (5 or 1) formed on the other surface thereof; forming a desired circuit wiring pattern (3) in the conductive layer (6) of the laminated plate and an elastic suspension (1) in the elastic metal layer (5) thereof simultaneously, in accordance with photo-fabrication method including both-side simultaneous exposure method; forming a bonding metal layer (10) on the circuit wiring pattern (3) by plating; forming a cover coat layer (11) so as to cover the bonding metal layer; further forming a metal mask (13 or 13A) by forming a surface metal layer (12) on the cover coat layer and by etching the surface metal layer (12) or else byType: GrantFiled: May 19, 1997Date of Patent: January 12, 1999Assignee: Nippon Mektron, Ltd.Inventor: Masaichi Inaba
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Patent number: 5851846Abstract: In a dielectric isolation substrate, an end point of a polishing process for selective polishing for forming an SOI layer is detected with a high precision. When polishing a wafer with a polishing pad, the temperature of a region of the polishing pad having polished the wafer at a position immediately thereafter is detected by a temperature sensor and the selective polishing process is ended by discriminating that the rate of variation in the detected temperature has changed from a positive to a negative state and then to a fixed saturated state.Type: GrantFiled: December 21, 1995Date of Patent: December 22, 1998Assignee: Nippondenso Co., Ltd.Inventors: Masaki Matsui, Masatake Nagaya, Akinari Fukaya, Hiroaki Himi
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Patent number: 5851411Abstract: A method for manufacturing a display, which includes first and second substrates, each having an inner light shielding region and an edge light shielding region, includes the steps of defining the edge light shielding region into a first portion and a second portion, and defining an area of the first substrate. The area includes the first portion of the edge light shielding region. The area including the first portion of the edge light shielding region is removed and leaves the second portion of the edge light shielding region. The first and second substrates are combined at the second portion of the edge light shielding region.Type: GrantFiled: November 1, 1996Date of Patent: December 22, 1998Assignee: LG Electronics, Inc.Inventors: Sang-Sik An, Sang-Ho Lee, Dong-Hyo Gu, Min-Choel Shin
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Patent number: 5851409Abstract: A method for removing an environmental coating on an article intended for use in a hostile environment, such as turbine, combustor and augmentor components of a gas turbine engine. The method is particularly suited for the repair of diffusion aluminide coatings covered by a protective oxide scale, which may further include a thermal insulating ceramic outer layer. Processing steps generally include peening the environmental coating at a temperature below the ductile-to-brittle transition temperature of the diffusion coating, such that cracks are formed in the diffusion coating. Thereafter, the diffusion coating is subjected to an acidic solution that penetrates the cracks and interacts with the coating diffusion zone, resulting in the diffusion coating being chemically stripped from its underlying substrate.Type: GrantFiled: December 24, 1996Date of Patent: December 22, 1998Assignee: General Electric CompanyInventors: Jon C. Schaeffer, Jeffrey A. Conner, Dennis P. Dry, Gregory J. Anselmi, David C. Zigan
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Patent number: 5840202Abstract: Apparatus for shaping a polishing pad includes a pad shaping tool and a fixture for holding the pad shaping tool free of fixed connection to the fixture. The pad shaping tool has a pad shaping surface which engages a polishing surface of the polishing pad to shape that surface. The pad shaping surface is sized for engaging the polishing surface across it entire width. The fixture constrains the tool from movement about the center of rotation of the polishing pad and constrains the center of the tool from substantial radial movement with respect to the pad. A method for shaping the polishing pad is also disclosed.Type: GrantFiled: April 26, 1996Date of Patent: November 24, 1998Assignee: MEMC Electronic Materials, Inc.Inventor: Robert J. Walsh
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Patent number: 5829116Abstract: A method of treating a metal surface is disclosed wherein a series of microcavities is formed on the surface and a coating is applied to at least part of the surface. The surface is shot blasted using small balls projected against the surface. Applications include the manufacture of culinary receptacles.Type: GrantFiled: January 24, 1997Date of Patent: November 3, 1998Assignee: SEB S.A.Inventor: Jerome Vilon
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Patent number: 5822850Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.Type: GrantFiled: December 22, 1995Date of Patent: October 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
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Patent number: 5820770Abstract: A method for pattern-etching thick alumina layers in the manufacture of thin film heads (TFH) by using compatible metallic mask layers and a wet chemical etchant. The deep alumina etching facilitates a studless TFH device where the coil and bonding pads are deposited and patterned simultaneously, and vias are later etched through the alumina overcoat layer to expose the bonding pads. The method also enables the etching of scribe-line grooves of street and alleys across the wafer for sawing and machining of sliders. These grooves eliminate most alumina chipping due to stress and damage introduced by the sawing and machining operations. Similarly, pattern-etching of the alumina undercoat facilitates the formation of precise craters for recessed structures. These can improve planarity and alleviate problems related to adverse topography and elevated features of TFH devices.Type: GrantFiled: July 13, 1995Date of Patent: October 13, 1998Assignee: Seagate Technology, Inc.Inventors: Uri Cohen, Gene Patrick Bonnie
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Patent number: 5809634Abstract: A method of manufacturing a magnetic head suspension having a circuit wiring pattern member, comprises the steps of: preparing a laminated plate composed of a flat flexible insulating base member (2), a conductive layer (9 or 3) formed on one surface thereof, and an elastic metal layer (8 or 1) formed on the other surface thereof; photo-etching the conductive layer of the laminated plate, to form a metal mask (9) of a desired flexible insulating base member shape; removing the exposed flexible insulating base member (2) to such a thickness that the elastic metal layer (8 or 1) is at least not exposed; photo-etching the formed metal mask (9), to form a desired circuit wiring pattern (3); further etching the flexible insulating base member (2), to remove a part of the flexible insulating base member (2) still remaining on the surface of the elastic metal layer (8 or 1) in the preceding step, by using the formed circuit wiring pattern (3) as a mask; forming a surface protecting layer (4) on the surface of the foType: GrantFiled: May 5, 1997Date of Patent: September 22, 1998Assignee: Nippon Mektron, Ltd.Inventor: Masaichi Inaba
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Patent number: 5804086Abstract: This process for producing a structure incorporating a substrate (2), a thin surface film (16) made from a non-conducting material joined to one face (1) of the substrate (2), said substrate (2) having cavities (10) flush with said face (1), comprises the following successive stages:etching cavities (10) in one face (1) of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film, in order to correctly secure the latter,joining a non-conducting material wafer (12) to the face (1) of the substrate (2),thinning the wafer (12) to obtain the thin surface film.Type: GrantFiled: August 1, 1996Date of Patent: September 8, 1998Assignee: Commissariat a l'Energie AtomiqueInventor: Michel Bruel
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Patent number: 5785874Abstract: An optical waveguide device including a support substrate, a glass substrate, and a thin film layer formed on at least one of the substrates, if required. The support substrate and the glass substrate are bonded through direct bonding, and the glass substrate includes an optical waveguide as a part thereof. A layer having a refractive index lower than that of the glass substrate may be formed on the glass substrate. A method for fabricating such an optical waveguide device is also provided.Type: GrantFiled: August 4, 1995Date of Patent: July 28, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuo Eda
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Patent number: 5785840Abstract: The present invention relates to a process for producing a surface structure, preferably on a cylinder, cylinder dressing, or roller of a printing machine, with a hard chromium coating which is galvanically produced and preferably ground to dimensional accuracy. The object of the invention is to develop a process which permits a surface structure to be produced on the hard chromium coating, which surface structure permits relatively high frictional forces between the contact points of the printing material and the coating of the cylinder of the printing machine. This is achieved in that the surface structure is produced in two process steps in sequence, a surface part structure being produced as a dot screen in an approximately even random distribution by means of a first material erosion process in a first process step, and the final surface structure being produced in a second process step by means of a second material erosion including the dot screen.Type: GrantFiled: April 26, 1996Date of Patent: July 28, 1998Assignee: Man Roland Druckmaschinen AGInventor: Werner Sondergeld
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Patent number: 5776355Abstract: Methods for preparing a cutting tool substrate material for diamond coating include providing a grooved pattern on selected portions of at least the top surface and preferably also the sides of the substrate material. The pattern may be a cross-hatching, a diamond-hatching, or another design. The pattern is preferably applied to the tool substrate by scribing with a laser ablation tool. The pattern is designed to optimize adhesion of CVD diamond on the portions of the tool substrate which are expected to be most challenged during a cutting process. The dimensions of the pattern (e.g. the depth and spacing of scribe lines) are selected to provide the optimum combination of mechanical bonding and diamond nucleation during the CVD coating of the tool substrate. According to preferred aspects of the invention, the pattern is applied only to the portions of the surface not immediately adjacent to the cutting edge of the tool substrate, thereby sparing the geometry of the cutting edge itself.Type: GrantFiled: January 11, 1996Date of Patent: July 7, 1998Assignee: Saint-Gobain/Norton Industrial Ceramics CorpInventor: Scott D. Martin
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Patent number: 5772905Abstract: A lithographic method and apparatus for creating ultra-fine (sub-25 nm) patterns in a thin film coated on a substrate is provided, in which a mold having at least one protruding feature is pressed into a thin film carried on a substrate. The protruding feature in the mold creates a recess of the thin film. The mold is removed from the film. The thin film then is processed such that the thin film in the recess is removed exposing the underlying substrate. Thus, the patterns in the mold is replaced in the thin film, completing the lithography. The patterns in the thin film will be, in subsequent processes, reproduced in the substrate or in another material which is added onto the substrate.Type: GrantFiled: November 15, 1995Date of Patent: June 30, 1998Assignee: Regents of the University of MinnesotaInventor: Stephen Y. Chou