Mechanically Shaping, Deforming, Or Abrading Of Substrate Patents (Class 216/52)
  • Patent number: 5771569
    Abstract: A magnetic head suspension, wherein the interconnection wiring is integrated with a spring-like metal suspension member, is manufactured by first preparing a laminated plate comprised of a flexible insulating base sandwiched between a resilient metal layer and a layer of an electrical conductor. The electrical conductor layer and resilient metal layer are respectively formed into the desired circuit wiring pattern and a suspension member, unnecessary portions of the insulating base are removed, the wiring pattern is provided with a protective layer and the suspension member is mechanically formed into a desired final configuration.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: June 30, 1998
    Assignee: Nippon Mektron, Ltd.
    Inventor: Masaichi Inaba
  • Patent number: 5764416
    Abstract: A narrow-band antireflective coating is comprised of a multilayer dielectric film formed on a dielectric substrate. The antireflective coating is initially formed so that its outer layer has a thickness greater than the thickness required for antireflection. The reflectivity is monitored while outer layer is reduced in thickness to reduce the thickness of the outer layer to reduce the reflectivity.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: June 9, 1998
    Assignee: Litton Systems, Inc.
    Inventor: John P. Rahn
  • Patent number: 5756399
    Abstract: The present invention provides a process for making a semiconductor wafer, including slicing an ingot to obtain wafers; surface-grinding both sides of each of the wafers; etching the wafers with an alkaline solution; chamfering the peripheral portion of each of the wafers; both-side polishing the wafers for mirror processing ; cleaning both sides of each of the wafers to remove the particles attached to the sides; and drying and cleaning the wafers. By employing the present process, the time for polishing the wafer can be shortened, and the semiconductor wafer can be made effectively.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: May 26, 1998
    Assignee: Komatsu Electronic Metals Co. Ltd.
    Inventors: Hirofumi Hajime, Toshiharu Yubitani
  • Patent number: 5752309
    Abstract: A method and apparatus for processing a magnetic transducer which uses gallium ion beam milling to precisely define pole tip widths of the magnetic transducer. The gallium ion beam may be defocused to improve definition of the region which is damaged by gallium ion implantation. The precision pole tip widths provide a transducer that may record correspondingly precise track widths on a magnetic storage medium, such as a rotating disk. Subsequent to the ion milling process, the invention restores the magnetically conductive properties of the pole tip region, which may be degraded as a result of the ion milling process, by means of a lapping process.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: May 19, 1998
    Assignee: Quantum Corporation
    Inventors: Charles Partee, James W. Getz
  • Patent number: 5738797
    Abstract: A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: April 14, 1998
    Assignee: Ford Global Technologies, Inc.
    Inventors: Robert E. Belke, Jr., Michael G. Todd, Andrew Z. Glovatsky, Alice D. Zitzmann
  • Patent number: 5733465
    Abstract: A cutting die is produced by a process of forming resist patterns corresponding to the shapes of low cutting edges and resist patterns corresponding to the shapes of high cutting edges on a metal plate and conducting an etching treatment on the metal plate, wherein the height of each of the cutting edges is varied by varying the width of the relevant resist pattern, varying the timing of removing the relevant resist pattern and applying or not applying sealing treatment thereto. This process enables easy production of a cutting die provided either with low cutting edges and high cutting edges or with embossing parts and high cutting edges. Further, the use of this cutting die enables simultaneous execution of full cutting and half cutting (or embossing) operations, so that labels, box development base papers and the like can be produced by a single process.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: March 31, 1998
    Assignee: Lintec Corporation
    Inventors: Yoshihito Kitamura, Yasuo Sumikawa, Ryuichi Hayashi, Shigeo Ogawa
  • Patent number: 5725787
    Abstract: A light-emitting structure (306) contains a main section (302), a pattern of ridges (314) situated along the main section, and a plurality of light-emissive regions (313) situated in spaces between the ridges. The light-emissive regions produce light of various colors upon being hit by electrons. The ridges, which extend further away from the main section than the light-emissive regions, are substantially non-emissive of light when hit by electrons. Each ridge includes a dark region. The ridges thereby form a raised black matrix that improves contrast and color purity. When the light-emitting structure is used in an optical display, the raised black matrix contacts internal supports (308) and, in so doing, protects the light-emissive regions from being damaged. The light-emitting structure can be formed according to various techniques of the invention.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: March 10, 1998
    Assignee: Candescent Technologies Corporation
    Inventors: Christopher J. Curtin, Ronald S. Nowicki, Theodore S. Fahlen, Robert M. Duboc, Jr., Paul A. Lovoi
  • Patent number: 5700382
    Abstract: A method for fabricating a silicon semiconductor substrate having an optical fiber coupled to an integrated waveguide by anisotropically etching a V-shaped groove aligned with the integrated waveguide into the substrate. The integrated waveguide is provided with a freely accessible end surface situated opposite the end of the V-shaped groove. The freely accessible end surface is formed by first producing a recess in the silicon semiconductor substrate. The recess is made by anisotropically etching a piece of the substrate from the surface opposite the surface bearing said V-shaped groove. The piece is bared down to a region surrounding said integrated waveguide but the piece remains connected to the waveguide by a V-shaped notch. Then pressure is exerted on the piece, causing it to break off at the V-shaped notch, thus forming the freely accessible end surface of the waveguide as a fracture surface. An optical fiber is inserted into the V-shaped groove and extended up to the freely accessible end surface.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: December 23, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventor: Armin Splett
  • Patent number: 5695860
    Abstract: A resonant tag has one electrode plate of a capacitor and an electric circuit, which is electrically connected to the capacitor, formed on one surface of the insulating film composing the resonant circuit. On the other surface of the insulating film, the other electrode plate of the capacitor, which is electrically connected to the electric circuit, is formed. Heat pressing is performed on the insulating film existing between the two electrode plates with a predetermined pressure and at a predetermined temperature to shorten a distance between these electrode plates, and a crystal structure of the insulating film is destroyed to form a penetrating hole which penetrates through both the electrode plates.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: December 9, 1997
    Assignee: Tokai Electronics Co., Ltd.
    Inventors: Hideaki Imaichi, Takeshi Matsumoto, Yuji Suzuki, Koichi Himura, Tadayoshi Haneda
  • Patent number: 5693182
    Abstract: A method for making large scale integrated circuits on a disklike semiconductor substrate includes grinding a disk thin enough to be able to be sawn apart into individual chips. A damage zone caused by the grinding on a back side of the wafer is removed by etching while protecting a front side of the wafer, prior to sawing. The etching is carried out in the form of a microwave or high-frequency-excited downstream plasma etching process using fluorine compounds in an etching gas.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: December 2, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventor: Josef Mathuni
  • Patent number: 5679267
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on the front side and then filled with an etch step material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch step material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5676855
    Abstract: A process for producing a metal coated substrate with an improved resistivity to cyclic temperature stress is provided. The substrate is provided with at least one insulating layer and at least one metal layer attached to at least one side of the insulating layer. The metal layer is made at least 0.2 millimeters thick, and is weakened in places by openings formed in at least one border area.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: October 14, 1997
    Inventor: Jurgen Schulz-Harder
  • Patent number: 5674408
    Abstract: A developer carrier capable of forming microfields on the surface thereof and a method of producing such a developer carrier. A great amount of sufficiently charged one-component developer is carried on the surface of the developer carrier by the microfields and transported to a developing station for developing an electrostatic latent image. The developer carrier has a simple structure and is easy and economical to produce.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: October 7, 1997
    Assignee: Ricoh Company, Ltd.
    Inventors: Koji Suzuki, Hiroshi Takashima, Shigekazu Enoki, Naoki Iwata, Yuichi Ueno
  • Patent number: 5664325
    Abstract: A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: September 9, 1997
    Assignee: Hitachi Chemical Co. Ltd.
    Inventors: Naoki Fukutomi, Hajime Nakayama, Yoshiaki Tsubomatsu, Kouichi Kaitou, Yasunobu Yoshidomi, Yoshihiro Takahashi
  • Patent number: 5662817
    Abstract: The method for forming a tip of an array optical fiber disclosed is one in which an etching resistive material such as a photoresist is applied first on an end portion of a coated material covering constituent fibers of the array optical fiber, and then the ends of the constituent fibers are etched. Due to the presence of the etching resistive material, the etching solution does not dissolve the coated material. In an alternative method, the etching resistive material such as a photoresist is applied on a side surface of a tip portion of each constituent fiber of the array optical fiber exposed from the coated material, the tip portion is cut and flattened together with the etching resistive material, and the end faces of the constituent optical fibers are etched. The presence of the etching resistive material prevents the tip diameter of the constituent optical fiber from becoming small.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: September 2, 1997
    Assignee: NEC Corporation
    Inventor: Hiroshi Honmou
  • Patent number: 5653892
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A front side optical coating (e.g. transparent metal layer 44, transparent organic layer 46 and conductive metallic layer 48) is elevated above the substrate between the ceramic islands. This allows additional material (e.g. polyimide 38) between the optical coating and the substrate above the regions where cavities are to be etched. Etching of the cavities (72) is performed from the back side of the substrate without damaging the front side optical coating. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 80) containing a massive array of sensing circuits.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5635082
    Abstract: A thin film head of the floating type includes a head slider 1 having a surface to be opposed to the signal face of a recording medium with a small space formed therebetween. At least one head element 2 is formed by thin film forming techniques on a face of the head slider 1 orthogonal to the slider surface. A protective layer 3 is formed over the head slider face and covers the head element 2. The head slider 1 has a pair of side faces orthogonal to the slider surface to be opposed to the medium and extending in parallel to each other respectively at opposite sides of the head element 2. The protective layer 3 is formed at each of its opposite side portions with a bulging-out curved face R smoothly extending from the surface of the protective layer 3 to the side face of the head slider 1.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: June 3, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tomomi Yamamoto, Naoto Matono, Hitoshi Noguchi
  • Patent number: 5624581
    Abstract: The present invention is a subambient pressure air bearing slider having a slider body with a leading edge, a trailing edge and first and second side edges. First and second side rails are positioned along the first and second side edges, respectively, with each side rail defining an air bearing surface. The cavity dam extends between the first and second side rails and is recessed from the bearing surfaces. A subambient pressure cavity extends between the first and second side rails adjacent the cavity dam. The leading edge taper is formed along the leading edge and has a surface extending from the leading edge to an intersection with the air bearing surfaces of the first and second side rails. First and second side walls are formed within the leading edge taper between the first and second side edges. The first and second side walls converge towards the leading edge from the intersection of the bearing surfaces and the leading edge taper.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: April 29, 1997
    Assignee: Seagate Technology, Inc.
    Inventors: Layne S. Ihrke, Peter Crane
  • Patent number: 5605760
    Abstract: A pad is provided for use on a machine for the polishing of silicon wafers which allows the use of optical detection of the wafer surface condition as the wafer is being polished. This accomplished by constructing the entire pad or a portion thereof out of a solid uniform polymer sheet with no intrinsic ability to absorb or transport slurry particles and which is transparent to the light beam being used to detect the wafer surface condition by optical methods. Polymers which are transparent to light having a wavelength within the range of 190 to 3500 nanometers are suitable for the construction of these pads.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: February 25, 1997
    Assignee: Rodel, Inc.
    Inventor: John V. H. Roberts
  • Patent number: 5603158
    Abstract: An adhesive is applied onto a flexible resistive film 1 and dried to form an adhesive layer 2. A metal foil 3 is contacted onto the layer 2, which is subjected to a heat and pressing treatment. The foil 3 is polished. An ultraviolet light curable ink is applied on the foil 3 and dried to form a first layer 4. A negative film is placed on or over the layer 4 and ultraviolet light is irradiated thereto through the film so that the layer 4 is cured. Uncured portions of the layer 4 is removed so that cured portions thereof remain and the foil 3 is exposed between the remaining cured portions. The metal foil 3 is subjected to an etching treatment to remove exposed portions of the foil 3 so that unexposed portions of the foil 3 remain and form conductors 3A. The cured portions of the layer 4 is removed from the conductors 3A. A metal plating film 5 is formed on each conductor 3A to form each electrical conductive circuit 9.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: February 18, 1997
    Assignee: Nippon Graphite Industries Ltd.
    Inventors: Katsuhiro Murata, Mitsumasa Shibata, Toru Hatakeyama, Tadaaki Isono
  • Patent number: 5601732
    Abstract: Upon grinding a back of a substrate, a protecting tape made of a material soluble to IPA (isopropanol), for example, a vinyl acetate thermoplastic adhesive is appended on the surface of a pattern-formed layer of a wafer, grinding the back, dipping the wafer in a cleaning vessel containing IPA, and dissolving and removing the protecting tape from the wafer, thereby giving no damages to the wafer, and reducing the number of operation steps.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: February 11, 1997
    Assignee: Sony Corporation
    Inventor: Masahiro Yoshida
  • Patent number: 5597496
    Abstract: A method of manufacturing a magnetic head suspension, wherein a wiring member for connecting a magnetic head element with a read/write amplifier circuit board is integrally formed with the suspension, which includes the step of: (1) forming a laminated plate having a flexible insulating base material which has an electrically conductive layer on one surface and a springy metal layer on the other surface; (2) photoetching the electrically conductive layer of the laminated plate to form a metal mask having a desired shape which does not cover an exposed area of the flexible insulating base material; (3) removing the flexible insulating base material from the exposed area; (4) photoetching the metal mask to produce a circuit wiring pattern; (5) producing a surface protecting layer on the surface of the circuit wiring pattern; and (6) photoetching the springy metal layer and bending the springy metal layer to form a suspension having a desired shape.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 28, 1997
    Assignee: Nippon Mektron, Ltd.
    Inventors: Inaba Masaichi, Matsumoto Hirofumi, Tanaka Yasuyuki
  • Patent number: 5589251
    Abstract: A resonant tag is manufactured in the manner described below: a conductive thin film is formed to a predetermined thickness on two surfaces of an insulating thin film. Thereafter, a conductive pattern, composed of an inductor element and a capacitor element corresponding to a resonant frequency of a resonant circuit, is printed on a surface of one of the conductive thin films, and a conductive pattern, composed of a capacitor element corresponding to the resonant frequency of the resonant circuit, is printed on a surface of the other insulating thin film at a position which faces the capacitor element formed on one of the conductive thin films using an ink which resists etching. A non-printed portion of the conductive thin films is removed by etching to form a resonant circuit pattern.
    Type: Grant
    Filed: August 22, 1995
    Date of Patent: December 31, 1996
    Assignee: Tokai Electronics Co., Ltd.
    Inventors: Hideaki Imaichi, Takeshi Matsumoto, Yuji Suzuki, Koichi Himura, Tadayoshi Haneda
  • Patent number: 5579424
    Abstract: An arrangement for optically coupling a planar optical waveguide and an optical fiber comprises forming a planar optical waveguide on a surface of the substrate, forming a trench-like depression in the surface of the substrate leading from an end face of the planar waveguide to an edge of the substrate, forming a second holder part having a fiber secured between two planar surfaces lying in a common plane, assembling the separate holder part on a pair of planar surfaces lying on each side of the depression of said substrate so that the fiber is placed in the depression with play and the fiber will be arranged with the axis of the fiber being aligned with the axis of the planar waveguide.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: November 26, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hartmut Schneider
  • Patent number: 5547094
    Abstract: A nozzle assembly for use in atomizing and generating sprays from a fluid. The nozzle assembly includes two members joined together. In one of the two members are formed one or more nozzle outlets, one or more fluid inlets, and a plurality of channels that form filter passageways. The nozzle outlets discharge fluid jets that impinge on one another to thereby atomize the fluid. Alternatively, an impact element or a vortex-generating structure can be used in the nozzle outlet to atomize the fluid. Methods are also provided for producing the nozzle assembly by forming the inlets, outlets, and/or channels through electrical or chemical etching or other processes that selectively remove material from at least one face of a nozzle assembly member.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 20, 1996
    Assignees: DMW (Technology) Ltd., Boehringer Ingelheim International GmbH
    Inventors: Frank Bartels, Wulf Bachtler, Stephen T. Dunne, Joachim Eicher, Bernhard Freund, William B. Hart, Christoph Lessmoellmann
  • Patent number: 5544771
    Abstract: A method for manufacturing a collimator comprising the steps of patterning a plurality of thin metal strips into a plurality of basic plates, and forming grooves or ridges on front and back surfaces of each basic plates. Thereafter, the thin strips are folded, mated, and welded together to form pillar cells within the collimator.
    Type: Grant
    Filed: June 22, 1995
    Date of Patent: August 13, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jueng-gil Lee, Sun-hoo Park, Gil-heyun Choi
  • Patent number: 5544549
    Abstract: A process for producing a steel punching sheet that has the same ideal dimension over the entire length of the punching edge has the following steps: producing webs carrying punching edges on a steel starting sheet; processing the punching edges, wherein the distance between the punching edges and the back of the sheet is adjusted to a positive tolerance with respect to an ideal dimension; and grinding the back of the sheet to remove material in excess of the ideal dimension to within a tolerance of not more than 0.02 mm, more particularly a tolerance of not more than 0.005 mm. Advantageously, the process includes the following additional steps: adjusting the distance between the punching edges and the back of the sheet to a negative tolerance, with respect to an ideal dimension, and applying material to the back of the sheet to make-up for the negative tolerance up to a positive tolerance of not more than 0.02 mm, more particularly, a tolerance of not more than 0.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: August 13, 1996
    Inventor: Fritz Helferich
  • Patent number: 5535904
    Abstract: The present invention relates to an improved etchant for iron materials and method for etching iron materials. The etchant is an aqueous solution of ferrous chloride and phosphoric acid. The etchant preferably consisting of essentially of 20.6 gm FeCl.sub.2 .multidot.4H.sub.2 O, 88 ml H.sub.3 PO.sub.4 (concentrated 85%) and deionized water sufficient to make a 500 ml solution total. The method of etching includes the steps of preparing the surface of the iron material to be etched by degreasing and abrading the surface and etching the surface by immersing the iron material in the ferrous chloride and phosphoric acid solution. After the surface has been completely dried, an epoxy material may be bonded thereto. The method and etchant of the present invention provide an iron surface which bonds well with an epoxy, but does not destroy any existing epoxy bond in the material as would be present in a wound iron core material bonded with an epoxy cement.
    Type: Grant
    Filed: January 25, 1995
    Date of Patent: July 16, 1996
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Wayne C. Tucker
  • Patent number: 5531343
    Abstract: This invention involves a fiber probe device and a method of making it. The probe includes a relatively thick upper cylindrical region, typically in the form of a solid right circular cylinder, terminating in a tapered region that terminates in a relatively thin lower cylindrical region (tip), typically also in the form of a solid right circular cylinder, the lower region having a width (diameter) in the approximate range 0.01 .mu.m to 150 .mu.m.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: July 2, 1996
    Assignee: AT&T Corp.
    Inventors: Robert W. Filas, Herschel M. Marchman
  • Patent number: 5516430
    Abstract: A process for reactive ion etching or ion milling of an air bearing slider comprises the steps of mechanical alignment of unetched slider rows with active transducer devices onto an alignment fixture; positioning a layer of thermally conductive adhesive between the rows and a substrate; heating the adhesive through the substrate such that the adhesive bonds the rows to the substrate while encapsulating the rows; removing the alignment fixture; patterning and etching the exposed planarized slider surfaces; stripping the resist and cutting the rows into individual sliders while still bonded to the substrate; stripping the adhesive with an organic solvent. This process increases tolerance to manufacturing variability, minimizes damage and contamination of the transducer devices, and decreases the cycle time and production costs.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: May 14, 1996
    Assignee: Read-Rite Corporation
    Inventor: Keith R. Hussinger
  • Patent number: 5508206
    Abstract: Thin semiconductor devices, such as thin solar cells, and a method of fabricating same are disclosed. A microblasting procedure is employed to thin a semiconductor wafer or substrate, such as a solar cell wafer, wherein fine abrasive particles are used to etch away wafer material through a mask. Thick areas remain at the perimeter of the semiconductor device or solar cell, in regions of the semiconductor device or solar cell behind the front interconnect attachment pads, and at corresponding rear interconnect attachment areas. In addition, there are thick areas in a pattern that comprise interconnected beams that support the thin wafer areas. Consequently, predetermined areas of the wafer are thinned to form a predetermined structural pattern in the wafer that includes an external frame and a plurality of interconnected beams.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: April 16, 1996
    Assignee: Spectrolab, Inc.
    Inventors: Gregory S. Glenn, B. Terence Cavicchi
  • Patent number: 5483378
    Abstract: A method for producing a narrow band anti-reflective film on a substrate, and the film produced by that method. The improved method being the concept of trimming the outer layer in order to correct for its thickness layers as well as those of the inner layer.
    Type: Grant
    Filed: January 10, 1992
    Date of Patent: January 9, 1996
    Assignee: Litton Systems, Inc.
    Inventor: John P. Rahn
  • Patent number: 5480048
    Abstract: A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kitamura, Hisashi Sugiyama, Yoshihide Yamaguchi, Masayuki Kyoui, Hideyasu Murooka, Ryoji Iwamura, Makio Watanabe
  • Patent number: 5478436
    Abstract: A selective cleaning process for fabricating a semiconductor device includes the steps of processing a semiconductor substrate (10) and introducing metal contaminants (22) by contacting the semiconductor substrate (10) with a polishing slurry during a polished planarization process. The metal contaminants (22) are removed by applying a cleaning solution including an organic solvent and a compound containing fluorine. The chemical constituents of the cleaning solution are substantially unreactive with metal interconnect material (12) underlying dielectric layers (18) present on the semiconductor substrate (10). The preferred cleaning solution comprises an aqueous solution of ethylene glycol and ammonium fluoride.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: December 26, 1995
    Assignee: Motorola, Inc.
    Inventors: Paul M. Winebarger, Mark A. Zaleski, Troy B. Morrison, Jeffrey J. Sultemeier
  • Patent number: 5468345
    Abstract: A method of making printed circuit boards in a continuous process. The method uses copper base metal sputtered onto a substrate. This base metal is much thinner than the base metal normally used in printed circuit processes and ultimately allows a greater number of conductors per unit of length to be made on the boards.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: November 21, 1995
    Inventors: Ronald K. Kirby, James W. Watson
  • Patent number: 5466331
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 20) which are fabricated from novel materials using unique methods of patterning. Trenches (22) are formed in the ceramic substrate from the front side and filled with a filler material (e.g. parylene 24). An elevation layer (e.g. polyimide 26) is deposited above the filler material, and a front side optical coating (e.g. transparent metal layer 34, transparent organic layer 36 and conductive metallic layer 38 ) is elevated above the substrate between the ceramic islands. The elevation layer provides added protection to the optical coating during filler material removal. The substrate is thinned from the back side down through a portion of the trench filler material. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 62) containing a massive array of sensing circuits.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: November 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: James F. Belcher
  • Patent number: 5451295
    Abstract: A method for removing film from a substrate, and more particularly, photoresist from a semiconductor wafer, by a shear stress process. A wafer is coated with a medium having coefficients of thermal expansion and elasticity, such as water, and then cooled. The cooling causes shear stress to occur between the photoresist and the wafer, thereby loosening the photoresist from the wafer. The wafer is then heated to remove the medium and photoresist from the wafer. The coating, cooling and heating steps are repeated until all of the photoresist is removed. Relative to the prior art, this invention provides a novel process for removing film from a substrate that minimizes expense; substantially cuts processing time; is less complex; less hazardous; and environmentally favorable.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: September 19, 1995
    Assignee: Micron Technology, Inc.
    Inventor: Gary H. Kroll
  • Patent number: 5447779
    Abstract: A resonant tag is manufactured in the manner described below: a conductive thin film is formed to a predetermined thickness on two surfaces of an insulating thin film. Thereafter, a conductive pattern, composed of an inductor element and a capacitor element corresponding to a resonant frequency of a resonant circuit, is printed on a surface of one of the conductive thin films, and a conductive pattern, composed of a capacitor element corresponding to the resonant frequency of the resonant circuit, is printed on a surface of the other insulating thin film at a position which faces the capacitor element formed on one of the conductive thin films using an ink which resists etching. A non-printed portion of the conductive thin films is removed by etching to form a resonant circuit pattern.
    Type: Grant
    Filed: January 27, 1993
    Date of Patent: September 5, 1995
    Assignee: Tokai Electronics Co., Ltd.
    Inventors: Hideaki Imaichi, Takeshi Matsumoto, Yuji Suzuki, Koichi Himura, Tadayoshi Haneda
  • Patent number: 5447601
    Abstract: The method comprises the steps of providing a substrate wafer (10); depositing a first layer of resist (12) upon the substrate wafer (10); removing selected areas of the first resist layer (12), thereby to provide first etch windows; forming first cavities (16) in the substrate wafer (10) by a first etching process through the first windows; bonding a relatively thick membrane wafer (24) to the substrate wafer (10), thereby covering the cavities (16); polishing the surface of the relatively thick membrane wafer (24) thereby to produce a relatively thin membrane (24a); depositing a second layer of resist (33) on the relatively thin membrane (24a); removing selected areas of the second deposited resist layer, thereby to provide second etch windows (40); etching away the relatively thin membrane (24a) in the region of the second etch windows (40) until the first cavities (16) are exposed, thereby to form in the relatively thin membrane (24a) a free standing resonator structure (18 ) suspended on a plurality of c
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: September 5, 1995
    Assignee: British Aerospace PLC
    Inventor: Timothy S. Norris
  • Patent number: 5441593
    Abstract: An ink fill slot can be precisely manufactured in a substrate utilizing photolithographic techniques with chemical etching, plasma etching, or a combination thereof. These methods may be used in conjunction with laser ablation, mechanical abrasion, or electromechanical machining to remove additional substrate material in desired areas. The ink fill slots are appropriately configured to provide the requisite volume of ink at increasingly higher frequency of operation of the printhead by means of an extended portion that results in a reduced shelf length and thus reduced fluid impedance imparted to the ink. The extended portion is precisely etched to controllably align it with other elements of the printhead.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: August 15, 1995
    Assignee: Hewlett-Packard Corporation
    Inventors: Kit C. Baughman, Jeffrey A. Kahn, Paul H. McClelland, Kenneth E. Trueba, Ellen R. Tappon
  • Patent number: 5437762
    Abstract: The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: August 1, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Akihiko Ochiai, Makoto Hashimoto, Takeshi Matsushita, Machio Yamagishi, Hiroshi Sato, Muneharu Shimanoe
  • Patent number: 5435889
    Abstract: A process is disclosed for coating a ceramic composite in which the composite has a pattern of grooves cut into the surface followed by coating to increase adhesion and inhibit cracking of the coating.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: July 25, 1995
    Assignee: Chromalloy Gas Turbine Corporation
    Inventor: Herbert Dietrich
  • Patent number: 5433819
    Abstract: A method of making circuit boards is disclosed that is suitable for use in a high-volume automated processing plant. The method can be used to produce either single-sided or double-sided circuit boards with access windows allowing electrical access and connection between traces from both sides. In the process, access holes are punched in a coverfilm. A copper sheet having a tin plating on one side is laminated to the coverfilm, with the tin side facing the coverfilm. A pattern representing a circuit is screened on the resulting laminate with a UV-curable resist, developed in a UV dryer, and then the unprotected copper is etched away. The remaining tin is then removed with solder stripping agent, and the resulting circuit is protected with a coverfilm. The process can be applied to large rolls of materials in an automated process, with large numbers of circuits applied to the laminated board. The circuits can then be punched out of the web with a hydraulic press in large numbers.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: July 18, 1995
    Assignee: Pressac, Inc.
    Inventor: Mark T. McMeen
  • Patent number: 5429711
    Abstract: There is disclosed a wafer-manufacturing method in which a single crystal ingot is first sliced into a plurality of wafers, and both surfaces of each wafer are subjected to grinding or lapping operation. Then, the front and back surfaces of the wafer are subjected to etching. Thereafter, the back surface of the wafer is subjected to chemical mechanical polishing to half-polish the same, following which the wafer is placed on a polishing machine, with the half-polished back surface of the wafer being adhered to a carrier plate; and the front surface of the wafer is mirror-polished. In the foregoing, a polysilicon film for extrinsic gettering may be formed on the back surface of the etched wafer prior to the half-polishing.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: July 4, 1995
    Assignees: Mitsubishi Materials Corporation, Mitsubishi Materials Silicon Corporation
    Inventors: Mineo Watanabe, Hitoshi Harada, Masanori Takemura
  • Patent number: 5427052
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: June 27, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5425840
    Abstract: A process for making plates from a photopolymer sheet which has been pre-exposed to ultraviolet radiation for conversion into printing plates for flexography, letterpress or dry-offset printing, includes the steps of inserting the sheet into an apparatus, sensitive side facing upwards and at high speed, so that the sheet is received on an etching plane and beneath a set of brushes, and etching the sheet under forces resulting from alternating movement of the brushes and to-and-fro movement of the brushes in a horizontal direction perpendicular to the alternating movement of the brushes. The sheet is automatically held in position during etching. Also disclosed is an apparatus for implementing this process, allowing for very rapid etching.
    Type: Grant
    Filed: October 5, 1993
    Date of Patent: June 20, 1995
    Assignee: Photomeca
    Inventor: Mario Ferrante
  • Patent number: 5415727
    Abstract: A large aperture microlens array assembly has at least two arrays of microlenses with individual unit cell trains optically interconnecting individual microlenses in one array with related individual microlenses in another array. In each unit cell train the light entering an entrance pupil of a microlens in one array is transmitted through the exit surface of a related microlens of the other array to provide a collimated output through the exit. One array may be moved with respect to the other array for scanning a field of regard.
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: May 16, 1995
    Assignee: Lockheed Missiles & Space Co., Inc.
    Inventors: George Gal, Howard E. Morrow
  • Patent number: 5413679
    Abstract: A method of producing a silicon membrane has a step of forming an etch stop layer on an upper surface of a silicon substrate having lower and upper opposing surfaces, the etch stop layer comprising an alloy of silicon and at least one other Group IV element. The method of producing a silicon membrane has another step of forming a cap layer on the etch stop layer, the cap layer having lower and upper opposing surfaces with the lower surface contacting the etch stop layer. The method of producing a silicon membrane has a further step of removing a portion of the silicon substrate at a time when the upper surface of the cap layer is exposed, the portion of the silicon substrate being removed extending from the upper surface of the silicon substrate to the lower surface of the silicon substrate to thereby define an exposed portion of the etch stop layer. The exposed portion of the etch stop layer may be removed.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: May 9, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: David J. Godbey