Gas Phase And Nongaseous Phase Etching On The Same Substrate Patents (Class 216/57)
  • Patent number: 8318034
    Abstract: In a surface processing method for processing a surface of a member made of silicon carbide (SiC) and having a fragmental layer on a surface thereof, the surface of the member having the fragmental layer is modified into a dense layer to reduce the number of particles generated from the surface of the member when the member is applied to a plasma processing apparatus. Here, the SiC of the surface of the member is recrystallized by heating the fragmental layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 27, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Naoyuki Satoh, Nobuyuki Nagayama, Keiichi Nagakubo
  • Patent number: 8308967
    Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer-insulating layer-second inorganic material layer or a layer construction of inorganic material layer-insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: November 13, 2012
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsuya Sakayori, Terutoshi Momose, Shigeki Kawano, Tomoko Togashi, Hiroko Amasaki, Nobuhiro Sakihama, Tsuyoshi Yamazaki, Michiaki Uchiyama, Hiroshi Yagi
  • Patent number: 8298434
    Abstract: A method of forming an electrode having an electrochemical catalyst layer is disclosed. The method includes etching a surface of a substrate, followed by immersing the substrate in a solution containing surfactants to form a conditioner layer on the surface of the substrate, and immersing the substrate in a solution containing polymer-capped noble metal nanoclusters dispersed therein to form a polymer-protected electrochemical catalyst layer on the conditioner layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: October 30, 2012
    Assignee: Tripod Technology Corporation
    Inventors: Tzu-Chien Wei, Hai-Peng Cheng, Shien-Ping Feng, Jo-Lin Lan, Chao Peng, Wen-Chi Hsu, Ya-Huei Chang, Wen-Hsiang Chen
  • Patent number: 8293128
    Abstract: A method of processing a substrate through the use of an apparatus, including a substrate carrier for carrying a substrate; a liquid-applying unit for applying chemical to said substrate; and a gas-applying unit for applying gas atmosphere to said substrate, wherein the method includes processing an organic film pattern formed on a substrate, by, in sequence, removing one of an altered layer and a deposited layer formed on the organic film pattern, and fusing said organic film pattern for deformation by applying gas atmosphere to the organic film pattern in the gas-applying unit, wherein at least a part of the removal step is carried out by applying a liquid to the organic film pattern in the liquid-applying unit. The process may include an ashing unit for ashing the substrate and/or a development unit for developing the organic film pattern.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: October 23, 2012
    Assignee: NEC Corporation
    Inventor: Shusaku Kido
  • Patent number: 8226840
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8216946
    Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: July 10, 2012
    Assignee: Nanya Technology Corporation
    Inventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
  • Patent number: 8211322
    Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gun Park, Dong-Won Kim, Sung-Young Lee, Yang-Kyu Choi, Chang-Hoon Kim, Ju-Hyun Kim
  • Patent number: 8206603
    Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20120125889
    Abstract: A cluster beam generating apparatus that generates a cluster beam includes a mixer that mixes a gas source material and a liquid source material; a nozzle that supplies a cluster beam including clusters originating from the gas source material and the liquid source material that are mixed in the mixer; and a temperature adjusting portion that adjusts a temperature of the nozzle, thereby controlling a ratio of the clusters originating from the gas source material and the clusters originating from the liquid source material in the cluster beam.
    Type: Application
    Filed: May 23, 2011
    Publication date: May 24, 2012
    Applicants: Tokyo Electron Limited, HYOGO PREFECTURE
    Inventors: Noriaki TOYODA, Isao Yamada, Masaki Narushima
  • Publication number: 20120118856
    Abstract: A silsesquioxane resin is applied over the patterned photo-resist and cured at the pattern surface to produce a cured silsesquioxane resin on the pattern surface. The uncured silsesquioxane resin layer is then removed leaving the cured silsesquioxane resin on the pattern surface. The cured silsesquioxane resin on horizontal surfaces is removed to expose the underlying photo-resist. This photo-resist is removed leaving a pattern of cured silsesquioxane. Optionally, the new pattern can be transferred into the underlying layer(s).
    Type: Application
    Filed: June 22, 2010
    Publication date: May 17, 2012
    Inventors: Peng-Fei Fu, Eric Scott Moyer, Jason D. Suhr
  • Patent number: 8163185
    Abstract: A method of lifting off photoresist beneath an overlayer includes providing a structure including photoresist and depositing an overlayer impenetrable to a liftoff solution over the photoresist and a field region around the structure. The method also includes forming a mask over the structure and ion milling to remove the overlayer in the field region not covered by the mask. The method then includes lifting off the photoresist using the liftoff solution.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: April 24, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Hai Sun, Liubo Hong, Rowena Schmidt, Lijie Zhao, Winnie Yu, Hongping Yuan
  • Patent number: 8153015
    Abstract: The invention concerns article having a surface oxide layer up to 20 nm thick, the surface oxide layer comprising chromium and cobalt oxides where the atomic ratio of Cr/Co is more than 3. The invention also concerns methods for treating a chromium containing material, said method comprising contacting said material with a gas plasma under conditions effective to oxidize at least a portion of the material; and contacting said material with an acid. The treated surface is corrosion resistant and can be used in orthopedic implants, especially the wear surface of the orthopedic implant to reduce wear, and other corrosive environment.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: April 10, 2012
    Assignee: DePuy Products, Inc.
    Inventors: Lawrence Salvati, Sophie Xiaofan Yang
  • Patent number: 8148267
    Abstract: A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Whee Won Cho, Jong Hye Cho
  • Patent number: 8114780
    Abstract: A method of removing carbon doped silicon oxide between metal contacts is provided. A layer of the carbon doped silicon oxide is converted to a layer of silicon oxide by removing the carbon dopant. The converted layer of silicon oxide is selectively wet etched with respect to the carbon doped silicon oxide and the metal contacts, which forms recess between the metal contacts.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 14, 2012
    Assignee: Lam Research Corporation
    Inventors: Mayumi Block, Robert C. Hefty, Stephen M. Sirard, Kenji Takeshita
  • Patent number: 8105498
    Abstract: A method for fabricating micromachined structures is provided. A structure including a dielectric layer, a metal layer and a passivation layer is formed, wherein the dielectric layer has a via thereon. An etching window is formed on the passivation layer. An etching solution is poured into the via through the etching window to perform a process of etching. After etching, the etching solution is removed and the passivation layer is removed. Finally, the structure is etched again to form the micromachined structure.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: January 31, 2012
    Assignee: PixArt Imaging Inc.
    Inventors: Chuanwei Wang, Ming Han Tsai, Chih Ming Sun, Weileun Fang
  • Patent number: 8092704
    Abstract: A method of fabricating a c-aperture or E-antenna plasmonic near field source for thermal assisted recording applications in hard disk drives is disclosed. A c-aperture or E-antenna is built for recording head applications. The technique employs e-beam lithography, partial reactive ion etching and metal refill to build the c-apertures. This process strategy has the advantage over other techniques in the self-alignment of the c-aperture notch to the c-aperture internal diameter, the small number of process steps required, and the precise and consistent shape of the c-aperture notch itself.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 10, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hamid Balamane, Thomas Dudley Boone, Jr., Jordan Asher Katine, Barry Cushing Stipe
  • Patent number: 7998651
    Abstract: A method of making an imprint template includes providing a transfer layer on a substrate and providing a layer of imprintable medium on the transfer layer, using a master imprint template to imprint a pattern into the imprintable medium, polymerizing the imprintable medium by exposing it to actinic radiation, then etching the resulting polymer layer, the transfer layer and the substrate such that the imprinted pattern is transferred to the substrate, the substrate thereby becoming an imprint template bearing a pattern which is the inverse of a pattern provided on the master imprint template.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: August 16, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Sander Frederik Wuister, Johan Frederik Dijksman, Yvonne Wendela Kruijt-Stegeman, Ivar Schram
  • Publication number: 20110192819
    Abstract: A method for manufacturing surgical blades from either a crystalline or poly-crystalline material, preferably in the form of a wafer, is disclosed. The method includes preparing the crystalline or poly-crystalline wafers by mounting them and machining trenches into the wafers. The methods for machining the trenches, which form the bevel blade surfaces, include a diamond blade saw, laser system, ultrasonic machine, and a hot forge press. The wafers are then placed in an etchant solution which isotropically etches the wafers in a uniform manner, such that layers of crystalline or poly-crystalline material are removed uniformly, producing single or double bevel blades. Nearly any angle can be machined into the wafer which remains after etching. The resulting radii of the blade edges is 5-500 nm, which is the same caliber as a diamond edged blade, but manufactured at a fraction of the cost.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Inventors: Joseph Francis Keenan, Vadim Mark Daskal, James Joseph Hughes
  • Patent number: 7993534
    Abstract: A method for forming a chemical microreactor includes forming at least one capillary microchannel in a substrate having at least one inlet and at least one outlet, integrating at least one heater into the chemical microreactor, interfacing the capillary microchannel with a liquid chemical reservoir at the inlet of the capillary microchannel, and interfacing the capillary microchannel with a porous membrane near the outlet of the capillary microchannel, the porous membrane being positioned beyond the outlet of the capillary microchannel, wherein the porous membrane has at least one catalyst material imbedded therein.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 9, 2011
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Jeffrey D. Morse, Alan Jankowski
  • Patent number: 7993539
    Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20110132872
    Abstract: A method of forming a nozzle and an ink chamber of an ink jet device, includes forming a nozzle passage by subjecting a substrate to a directional first etch process from one side of the substrate; applying a second etch process from the same side of the substrate for widening an internal part of the nozzle passage, to form a cavity forming at least a portion of the ink chamber adjacent to the nozzle; and controlling the shape of the cavity by providing, on the opposite side of the substrate, an etch accelerating layer buried under an etch stop layer and by allowing the second etch process to proceed into the etch accelerating layer. The following steps precede the first etch process: forming an annular trench in the substrate on the side of the substrate where the nozzle is to be formed; and passivating the walls of the trench so as to become resistant against the second etch process. The material surrounded by the trench is removed in the first etch process.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 9, 2011
    Applicant: OCE TECHNOLOGIES B.V.
    Inventors: Henricus Johannes Adrianus VAN DE SANDE, Willem Maurits HIJMANS, Gerardus Johannes BURGER, Dionysius Antionius Petrus OUDEJANS
  • Publication number: 20110120972
    Abstract: Processes for removing a metal oxide product from a crack with an opening in an outer surface of a part, such as a turbine component. The process includes exposing the metal oxide product to a solution effective to remove a first portion of the metal oxide product from surfaces inside the crack. After the metal oxide product is exposed to the solution, the metal oxide product is heated to a temperature and in an atmosphere effective to remove a second portion of the thermal oxide product from the surfaces inside the crack. The cleaning process may be a substitute for fluoride ion cleaning.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 26, 2011
    Applicant: MEYER TOOL, INC.
    Inventors: Mark Faulkner, Len Hampson
  • Publication number: 20110123771
    Abstract: A nanofabrication process for use with a photoresist that is disposed on a substrate includes the steps of exposing the photoresist to a grayscale radiation pattern, developing the photoresist to remove a irradiated portions and form a patterned topography having a plurality of nanoscale critical dimensions, and selectively etching the photoresist and the substrate to transfer a corresponding topography having a plurality of nanoscale critical dimensions into the substrate.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 26, 2011
    Inventors: Samuel Martin Stavis, Elizabeth Arlene Strychalski, Michael Gaitan
  • Patent number: 7938973
    Abstract: By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: May 10, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Joerg Hohage, Martin Mazur
  • Patent number: 7914623
    Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: March 29, 2011
    Assignee: Applied Materials, Inc.
    Inventors: James S. Papanu, Han-Wen Chen, Brian J. Brown, Steven Verhaverbeke
  • Patent number: 7871530
    Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 18, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eunkyoung Kim, Sung Q Lee, Kang Ho Park
  • Publication number: 20110006037
    Abstract: In a surface processing method for processing a surface of a member made of silicon carbide (SiC) and having a fragmental layer on a surface thereof, the surface of the member having the fragmental layer is modified into a dense layer to reduce the number of particles generated from the surface of the member when the member is applied to a plasma processing apparatus. Here, the SiC of the surface of the member is recrystallized by heating the fragmental layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 13, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Naoyuki SATOH, Nobuyuki NAGAYAMA, Keiichi NAGAKUBO
  • Patent number: 7862731
    Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: January 4, 2011
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Matthias Aikele, Albert Engelhardt, Marcus Frey, Bernhard Schmid, Helmut Seidel
  • Patent number: 7861387
    Abstract: A method for manufacturing a piezoelectric resonator element from a substrate made of piezoelectric material is provided. The method includes forming a first dry etching mask in a first masking region of a first surface of the substrate in a first mask forming process and performing a first dry etching process to remove a portion of the substrate in areas between the first dry etching mask after the first mask forming process. The method further includes maintaining a first un-etched portion of the substrate between the first dry etching mask after the first dry etching process and removing the first dry etching mask in a mask removing process after the first dry etching process. A wet etching process is performed to remove the first un-etched portion of the substrate after the mask removing process, thereby forming the piezoelectric resonator element.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: January 4, 2011
    Assignee: Epson Toyocom Corporation
    Inventors: Akira Hokibara, Sachi Yamamoto
  • Patent number: 7850863
    Abstract: A process for fabricating a hydrogenated amorphous silicon carbide film having through-pores includes the formation on a substrate of a film consisting of an amorphous hydrogenated silicon carbide matrix in which silicon oxide nanowires are dispersed therethrough, and then the selective destruction by a chemical agent of the silicon oxide nanowires present in the film formed at step a). Applications include microelectronics and micro-technology, in all fabrication processes that involve the degradation of a sacrificial material by diffusion of a chemical agent through a film permeable to this agent for the production of air gaps, in particular the fabrication of air-gap interconnects for integrated circuits.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: December 14, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Aziz Zenasni
  • Patent number: 7846843
    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chai O Chung, Jong Min Lee, Chan Bae Kim, Hyeon Ju An, Hyo Seok Lee, Sung Kyu Min
  • Patent number: 7837889
    Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: November 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20100224590
    Abstract: A method for forming a hollow microneedle structure includes processing the front side of a wafer to form at least one microneedle projecting from a substrate and a through-bore passing through the microneedle and through a thickness of the substrate. An entire length of the through-bore is formed by a dry etching process performed from the front side of the wafer. Most preferably, upright surfaces of the microneedle structure and the through bore of the structure are formed by dry etching performed via a single mask with differing depths obtained by harnessing aspect ratio limitations of the dry etching process.
    Type: Application
    Filed: May 20, 2008
    Publication date: September 9, 2010
    Applicant: NanoPass Technologies Ltd.
    Inventors: Yehoshua Yeshurun, Meint de Boer, J.W. Berenschot
  • Patent number: 7771604
    Abstract: A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
  • Patent number: 7758760
    Abstract: A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Ha Choi, Min-Seok Oh, Hong-Kee Chin, Sang-Gab Kim, Yu-Gwang Jeong
  • Patent number: 7750059
    Abstract: A method of forming features on substrates by imprinting is provided. The method comprises: (a) forming a polymer solution comprising at least one polymer dissolved in at least one polymerizable monomer; and (b) depositing the polymer solution on a substrate to form a liquid film thereon; and then either: (c) curing the liquid film by causing the monomer(s) to polymerize and optionally cross-linking the polymer(s) to thereby form a polymer film, the polymer film having a glass transition temperature (Tg); and imprinting the polymer film with a mold having a desired pattern to form a corresponding negative pattern in the polymer film, or (d) imprinting the liquid film with the mold and curing it to form the polymer film. The temperature of imprinting is as little as 10° C. above the Tg, or even less if the film is in the liquid state. The pressure of the imprinting can be within the range of 100 to 500 psi.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: July 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gun Young Jung, Sivapackia Ganapathiappan, Yong Chen, R. Stanley Williams
  • Patent number: 7741222
    Abstract: An etch stop layer is formed over a first structure by depositing a metal oxide material over the first structure and annealing the deposited metal oxide material. A second structure is formed over the etch stop layer, and a formation is etched through the second structure using the etch stop layer as an etch stop.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: June 22, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Jae-Young Park, Won-Shik Shin, Hyeon-Deok Lee, Ki-Vin Im, Seok-Woo Nam, Hun-Young Lim, Won-Jun Jang, Yong-Woo Hyung
  • Patent number: 7704402
    Abstract: An optical element manufacturing method includes: disposing a light-shielding layer (14) that includes at least an Si layer as an uppermost layer, on a substrate (12) used as a base member, forming an optical aperture (14a) at the light-shielding layer (14) and forming a fine recession/projection structure (MR) at a surface of the uppermost layer through dry etching.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: April 27, 2010
    Assignee: Nikon Corporation
    Inventors: Yutaka Hamamura, Kiyoshi Kadomatsu, Noboru Amemiya
  • Publication number: 20100068105
    Abstract: A microfluidic structure includes a first layer (1) containing an active fluidic device (4); a second layer (3) containing an interconnect channel (6) for connecting the device (4) to a fluid source and/or outlet and/or another device and an intermediate layer (2) for defining at least one via (5) defining a fluid passage way between the device (4) and the interconnect channel (6) wherein the flow paths through the device (4) and the interconnect channel (6) are generally parallel.
    Type: Application
    Filed: April 25, 2006
    Publication date: March 18, 2010
    Inventor: Gordon R. Green
  • Patent number: 7672750
    Abstract: An etching monitoring apparatus and related method for use in the manufacture of microstructures (and in particular MEMS) located within an etching chamber is described. The apparatus and related method operates by setting the temperature of the chamber within which the microstructure is located at a starting temperature, and maintaining the partial pressure of an etching gas within the chamber at a constant value. As a result the surface temperature of the micro structure within the chamber is primarily determined by the etch rate. Therefore, by employing a thermometer to monitor the change in etching surface temperature, a direct diagnostic for monitoring the etching process is provided.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: March 2, 2010
    Assignee: Point 35 Microstructures Ltd.
    Inventors: Anthony O'Hara, Michael Leavy, Graeme Pringle
  • Patent number: 7666321
    Abstract: A method for decapsulating a package is provided. The method comprises steps of providing a package having a chip therein, wherein the chip has an active surface and a rear surface. Further, the package further comprises a heat sink, a plurality of solder bumps, a substrate, an underfill and a plurality of solder balls. The method further comprises removing the heat sink and removing the substrate together with the solder balls. A dry etching process is performed to remove a portion of the underfill. A wet etching process is performed to remove the rest portion of the underfill. A thermal process solder bump removal process is performed to melt the solder bumps and then a solder bump removal process is performed to remove the melted solder bumps from the active surface of the chip.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: February 23, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Tung-Yi Shih
  • Patent number: 7662301
    Abstract: A method of producing a free standing structure, the method comprising: providing a substrate having a raised pattern formed on a surface of said substrate, said raised pattern comprising at least one material which forms said surface; depositing material over said raised pattern; and dissolving said substrate to release said deposited material to form said free standing structure from said released deposited material.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: February 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Carl E. Norman
  • Publication number: 20100025367
    Abstract: A high throughput chemical treatment system for processing a plurality of substrates is described. The chemical treatment system is configured to chemically treat a plurality of substrates in a dry, non-plasma environment.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jay R. Wallace, Hiroyuki Takahashi
  • Patent number: 7649173
    Abstract: A method for preparing TEM sample, comprising the following steps: providing a sample with two pits and a failure region between the two pits, the failure region comprising a semiconductor device; milling the first surface of the failure region, till the cross section of the semiconductor device is exposed; etching the first surface of the failure region; cleaning the sample; milling the second surface of the failure region, till the failure region can be passed by electron beam. A sample can be prepared for a high resolution TEM through above steps. When the sample is observed, it is easy to distinguish the lightly doped drain, source/drain regions from the silicon substrate and observe the pattern and defects in the lightly doped drain, source/drain regions clearly; in addition, it is easy to distinguish the BPSG from the non-doped silicon dioxide in the failure region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Jianqiang Hu, Zhixian Rui, Yanli Zhao, Yanjun Wang, Ming Li, Min Pan
  • Patent number: 7635418
    Abstract: Apparatus and methods for shielding a feature projecting from a first area on a substrate to a plasma while simultaneously removing extraneous material from a different area on the substrate with the plasma. The apparatus includes at least one concavity positioned and dimensioned to receive the feature such that the feature is shielded from the plasma. The apparatus further includes a window through which the plasma removes the extraneous material. The method generally includes removing the extraneous material while shielding the feature against plasma exposure.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: December 22, 2009
    Assignee: Nordson Corporation
    Inventors: Robert S. Condrashoff, James D. Getty, James S. Tyler
  • Publication number: 20090208689
    Abstract: A method of introducing weakening into a solid or a workpiece, preferably a ceramic or a glass, by an energy source which, by means of specific energy input acting locally, weakens the solid or the workpiece at the location of the energy input. A chromophore substance is applied to the location of the energy input before or at the same time as the energy input, such that a physical, chemical or biological visible change in the solid body or the workpiece is achieved at the location of the energy input.
    Type: Application
    Filed: May 21, 2007
    Publication date: August 20, 2009
    Inventor: Claus Peter Kluge
  • Patent number: 7572385
    Abstract: A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is comprised of a second material. An opening is formed in the first layer and an etchant is provided in the opening to etch both the substrate and the first layer to form a first mold for a first micro-lens. The etchant etches the first layer at a different rate than the substrate. A lens material is added to the etched molds to form micro-lenses.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 11, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Jin Li
  • Patent number: 7569152
    Abstract: A useful layer (1) is initially attached by a sacrificial layer (2) to a layer (3) forming a substrate. Before etching of the sacrificial layer (2), at least a part of the surface (4, 5) of at least one of the layers in contact with the sacrificial layer (2) is doped. After etching of the sacrificial layer (2), the surface (4, 5) is superficially etched so as to increase the roughness of its doped part. After doping, a mask (9) is deposited on a part of the useful layer (1) so as to delineate a doped zone and a non-doped zone of the surface (4, 5), one of the zones forming a stop after the superficial etching phase.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: August 4, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Grange, Bernard Diem, Sylvie Viollet Bosson, Michel Borel
  • Patent number: 7553430
    Abstract: Aqueous polishing slurries for chemical-mechanical polishing are effective for polishing copper at high polish rates. The aqueous slurries according to the present invention may include soluble salts of molybdenum dissolved in an oxidizing agent and molybdic acid dissolved in an oxidizing agent. Methods for polishing copper by chemical-mechanical planarization include polishing copper with low pressures using a polishing pad and a aqueous slurries including soluble salts of molybdenum dissolved in an oxidizing agent and molybdic acid dissolved in an oxidizing agent, particles of MoO3 dissolved in an oxidizing agent, and particles of MoO2 dissolved in an oxidizing agent.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: June 30, 2009
    Assignee: Climax Engineered Materials, LLC
    Inventors: Sunil Chandra, Sreehari Nimmala, Suryadevara Vijayakumar Babu, Udaya B. Patri, Sharath Hedge, Youngki Hong
  • Patent number: RE40951
    Abstract: A dry etching method in which a plasma of an etching gas is generated and a magnetic material is dry-etched using a mask material made of a non-organic material, wherein an alcohol having at least one hydroxyl group is used as the etching gas. The alcohol used as the etching gas has one hydroxyl group such as an alcohol selected from the group including methanol (CH3OH), ethanol (C2H5OH) and propanol (C3H7OH).
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 10, 2009
    Assignee: Canon Anelva Corporation
    Inventors: Yoshimitsu Kodaira, Taichi Hiromi