Gas Phase And Nongaseous Phase Etching On The Same Substrate Patents (Class 216/57)
  • Publication number: 20020014403
    Abstract: After a Ta radiation absorber 13 is subjected to reactive ion overetching to form a desired pattern till an upper portion of the SiO2 buffer film 12 is removed, the buffer film 12 is removed by two steps of reactive sputter pre-underetching and final wet etching. In the wet etching, a substrate is rotated while spraying a dilute hydrofluoric acid solution, spray and rotation are ceased, the substrate is illuminated with a light beam to detect regularly reflected light, the detected signal is amplified, differentiated and compared with a reference voltage to detect an etching endpoint, and etching is ceased after a predetermined time has elapsed from the detection of the etching endpoint. At an inspection step, an image of a reflective mask is obtained with a microscope and it is determined that the side etching amount of the buffer film is short if the luminance, at a point of the maximum change rate on a luminance curve around the edge of the Ta radiation absorber 13, is lower than a reference value.
    Type: Application
    Filed: April 3, 2001
    Publication date: February 7, 2002
    Inventor: Eiichi Hoshino
  • Patent number: 6344148
    Abstract: An easy method proposes a passive alignment by using an alignment mark. That is, V-shaped grooves are utilized as alignment marks in place of a metal pattern of the prior art in observing an optical contrast. Also, in order to adjust a height of an optical device, the support made of a metal is formed in the conventional method, whereas in the present invention a height of an optical device is adjusted by etching the silicon substrate and clamped through the use of solder bumps formed in the V-shaped grooves. And also, in this invention, it is possible that V-shaped grooves can be facilely formed on a non-planarized substrate by using a method of burying a mask material during the formation of the V-shaped grooves. By applying the above principle, the present invention proposes a process capable of passive aligning an optical device, a planar lightwave circuit (PLC) and an optical fiber, simultaneously.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: February 5, 2002
    Assignee: Korea Telecom
    Inventors: Soo-Jin Park, Ki-Tae Jeong, Tae-Seok Suh, Young-Bok Choi, Sang-Pil Han
  • Patent number: 6328905
    Abstract: Methods of removing resist residues from semiconductor workpiece surfaces are provided. In one aspect, a method of removing resist from a surface of a workpiece is provided that includes the steps of exposing the workpiece to a plasma and rinsing the workpiece with CO2 and water in a processing chamber to dissolve the resist. Reliance on post plasma strip solvent rinses for resist removal is eliminated. The combination of CO2 with post-plasma strip water rinse increases the solubility and thus the removal rate of resist residues.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: December 11, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Lebowitz, Laura E. Faulk
  • Publication number: 20010042734
    Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.
    Type: Application
    Filed: June 12, 2001
    Publication date: November 22, 2001
    Inventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-Chou Vincent Wang
  • Patent number: 6313040
    Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorena Beghin, Francesca Canali, Francesco Cazzaniga, Luca Riva, Carmelo Romeo
  • Patent number: 6309554
    Abstract: A method of producing a needle-like diamond structure including the steps of forming a layer of anodized alumina on a diamond substrate, the anodized alumina having a plurality of through holes; vapor-depositing a substance resistant to plasma etching by a vacuum vapor-depositing method to form dots on said diamond substrate, wherein the layer of anodized alumina acts as a mask for the vapor deposition; removing the anodized alumina; and performing a plasma etching treatment while using the dots as a mask, thereby forming regularly-arranged, needle-like diamond columns.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: October 30, 2001
    Assignee: The University of Tokyo
    Inventors: Akira Fujishima, Hideki Masuda
  • Patent number: 6303042
    Abstract: A method for forming an ink jet nozzle plate includes providing a structure having a top substrate layer, a bottom substrate layer, and a buried layer disposed between the top substrate layer and the bottom substrate layer; providing a composite mask over the top substrate layer having a cavity mask which provides openings and a bore mask having openings which are entirely within the openings of the cavity mask and extend to the top substrate layer; anisotopically etching through the bore mask openings through top substrate layer and the buried layer into a portion of the bottom substrate layer; removing the bore mask and etching the top and bottom substrate layers without substantially affecting the buried layer to extend the openings in the top substrate layer and the bottom substrate layer; removing the cavity mask and attaching the top substrate layer to a base provided with ink delivery channels with correspond to the openings in the buried layer; and removing the bottom substrate layer.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: October 16, 2001
    Assignee: Eastman Kodak Company
    Inventors: Gilbert A. Hawkins, Xin Wen
  • Publication number: 20010027965
    Abstract: This invention relates to a method for gas assisted energy beam engraving of a target object. This invention employs and energy beam, such as a laser beam or an electron beam, to irradiate a target object in the presence of a selected gaseous environment in order to engrave a mark in the object.
    Type: Application
    Filed: June 4, 2001
    Publication date: October 11, 2001
    Inventors: Mary Helen McCay, C. Michael Sharp, John Brice Bible, John A. Hopkins, T. Dwayne McCay, Narendra Dahotre, Frederick A. Schwartz
  • Patent number: 6296740
    Abstract: Before submitting a sample, including a first material layered upon a substrate, to an ion milling process, whereby a second material is sputtered onto the surface of the first material and the sample is then submitted to an etching process, an irregularity is formed on the surface of the first material. The overall process results in the formation of cones, or micro-tip structures, which may then be layered with a layer of low work function material, such as amorphous diamond. The irregularity in the surface of the first material may be formed by polishing, sandblasting, photolithography, or mechanical means such as scratching.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: October 2, 2001
    Assignee: SI Diamond Technology, Inc.
    Inventors: Chenggang Xie, Dean Joseph Eichman
  • Publication number: 20010024883
    Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 27, 2001
    Applicant: Micron Technology, Inc.
    Inventors: Karen Huang, Christophe Pierrat
  • Patent number: 6267867
    Abstract: A process for coating a tungsten carbide base material substrate with CVD diamond film includes carburization and gas-assisted vaporization of cobalt from the surface with simultaneous recrystallization of surface grains of tungsten carbide to change their stoichiometry for improved adherence. Also disclosed is a WC—Co cutting tool having a relatively fine WC grain size and being coated with adherent CVD diamond.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: July 31, 2001
    Assignee: Saint-Gobain Industrial Ceramics, Inc.
    Inventor: James M. Olson
  • Publication number: 20010006167
    Abstract: A process for etching oxides having differing densities which is not only highly selective, but which also produces uniform etches is provided and includes the steps of providing an oxide layer on a surface of a substrate, exposing the oxide layer to a liquid comprising a halide-containing species, and exposing the oxide layer to a gas phase comprising a halide-containing species. The process desirably is used to selectively etch a substrate surface in which the surface of the substrate includes on a first portion thereof a first silicon oxide and on a second portion thereof a second silicon oxide, with the first silicon oxide being relatively more dense than the second silicon oxide, such as, for example, a process which forms a capacitor storage cell on a semiconductor substrate.
    Type: Application
    Filed: February 9, 2001
    Publication date: July 5, 2001
    Inventors: Randhir Thakur, James Pan
  • Patent number: 6235638
    Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch which produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: May 22, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Karen Huang, Christophe Pierrat
  • Patent number: 6228563
    Abstract: Adherent matrix layers such as post-etch and other post-process residues are removed from a substrate by exposing them to a vapor phase solvent to allow penetration of the vapor phase solvent into the adherent matrix layers and condensing the vapor phase solvent into the adherent matrix layers and revaporized to promote fragmentation of the matrix and facilitate removal. Megasonic energy may be transmitted via a transmission member to the adherent matrix through the solvent condensed thereon to loosen fragments and particles. The substrate is typically rotated to improve contact between the megasonic energy transmission member and the condensed solvent and achieve more uniform cleaning. A co-solvent which is soluble in the vapor phase solvent may be added to enhance removal of specific adherent matrix materials.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: May 8, 2001
    Assignee: Gasonics International Corporation
    Inventors: Vladimir Starov, Syed S. Basha, Krishnan Shrinivasan, Karen A. Reinhardt, Aleksandr Kabansky
  • Patent number: 6217787
    Abstract: We are familiar with etching printed circuit boards chemically by providing a copper board with a mask and etching copper away chemically at those points where the mask is not present. This is disadvantageous, e.g. from environmental standpoints, because the chemical liquid is increasingly enriched with copper, and, when the liquid has been used, it can no longer be employed and is also difficult to dispose of. The invention is based on the object of providing a method of either applying or removing conductive material electrically.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: April 17, 2001
    Assignee: Deutsche Thomson-Brandt GmbH
    Inventor: Hans-Otto Haller
  • Patent number: 6217784
    Abstract: A process for etching oxides having differing densities which is not only highly selective, but which also produces uniform etches is provided and includes the steps of providing an oxide layer on a surface of a substrate, exposing the oxide layer to a liquid comprising a halide-containing species, and exposing the oxide layer to a gas phase comprising a halide-containing species. The process desirably is used to selectively etch a substrate surface in which the surface of the substrate includes on a first portion thereof a first silicon oxide and on a second portion thereof a second silicon oxide, with the first silicon oxide being relatively more dense than the second silicon oxide, such as, for example, a process which forms a capacitor storage cell on a semiconductor substrate.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 17, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Randhir Thakur, James Pan
  • Patent number: 6214243
    Abstract: A process for the manufacture of a Coriolis rate-of-rotation sensor with oscillatory support masses spring-suspended on a substrate as well as driving means for the excitation of the planar oscillation of the oscillating masses and evaluation means for the determination of a Coriolis acceleration. Oscillating masses, driving means and integrated stops are structured in a common operation by means of plasma etching from a silicon-on-insulator (SOI) wafer.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: April 10, 2001
    Assignee: Robert Bosch GmbH
    Inventors: Horst Muenzel, Franz Laermer, Michael Offenberg, Andrea Schilp, Markus Lutz
  • Patent number: 6214245
    Abstract: A method for forming an ink jet nozzle plate includes providing a buried layer over a bottom substrate layer; providing and patterning a top substrate layer over the buried layer and having openings having inclined walls; providing an ink jet nozzle plate layer over the patterned top substrate layer and into the openings formed in the patterned top substrate layer, the ink jet nozzle plate layer contacting the buried layer; attaching the ink jet nozzle plate layer to a base having ink delivery channels; removing by etching the bottom substrate layer; and providing bore regions into the ink jet nozzle plate layer with each bore region corresponding to a delivery channel.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: April 10, 2001
    Assignee: Eastman Kodak Company
    Inventors: Gilbert A. Hawkins, Xin Wen
  • Patent number: 6204190
    Abstract: A method for producing an electronic device, comprises the steps of: depositing a thin film on a substrate; etching a portion of the thin film by a reactive ion etching so as to leave a remaining portion of the thin film behind; and removing the remaining thin film by a physical etching using an inert gas.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: March 20, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihiro Koshido
  • Patent number: 6194320
    Abstract: In a method for preparing a semiconductor device wherein a first silicon oxide film, a second silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate, and both silicon oxide films and the silicon nitride film are patterned, a patterned resist 45 is formed on the silicon nitride film, the silicon nitride film is etched with phosphoric acid the resist serving as a mask, and both silicon oxide films are etched with hydrofluoric acid the resist serving as a mask.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: February 27, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Makoto Oi
  • Patent number: 6192899
    Abstract: A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: February 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Donald L. Westmoreland, Donald L. Yates
  • Patent number: 6169036
    Abstract: A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: January 2, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Siddhartha Bhowmik, Joseph William Buckfeller, G. Craig Clabough, Sailesh Mansinh Merchant
  • Patent number: 6156243
    Abstract: (1) Alignment mark transfer portion(s) is/are formed on the transfer molding surface of a mold that is used for press-molding a optical element fixing member and having alignment marks; (2) alignment mark(s) is/are formed on the mold material by dry-etching, and the mold material is worked using the alignment mark(s) as a reference to form the transfer molding surface constituted by a plurality of transfer patterns, in order to obtain a mold for press-molding; and (3) the transfer patterns are formed by dry-etching, or a transfer molding bare surface for transfer patterns is formed by dry-etching and a mold release film is formed thereon to reflect the shape of the transfer molding base surface, in order to obtain a mold for press-molding.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: December 5, 2000
    Assignee: Hoya Corporation
    Inventors: Hiroyuki Kosuga, Yoshiatsu Yokoo
  • Patent number: 6149828
    Abstract: A supercritical etching composition and method for etching an inorganic material of a semiconductor-based substrate are provided. The method includes providing a semiconductor-based substrate having an exposed inorganic material and exposing the substrate to the supercritical etching composition, whereby exposed inorganic material is removed from the substrate. In one embodiment, the supercritical etching composition includes a supercritical component, which is not capable of etching a particular exposed inorganic material, and a nonsupercritical etching component, which is capable of etching the particular exposed inorganic material. In another embodiment, the supercritical etching composition includes a supercritical component, which is capable of etching the particular exposed inorganic material.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: November 21, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 6126847
    Abstract: A process for etching oxides having differing densities which is not only highly selective, but which also produces uniform etches is provided and includes the steps of providing an oxide layer on a surface of a substrate, exposing the oxide layer to a liquid comprising a halide-containing species, and exposing the oxide layer to a gas phase comprising a halide-containing species. The process desirably is used to selectively etch a substrate surface in which the surface of the substrate includes on a first portion thereof a first silicon oxide and on a second portion thereof a second silicon oxide, with the first silicon oxide being relatively more dense than the second silicon oxide, such as, for example, a process which forms a capacitor storage cell on a semiconductor substrate.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: October 3, 2000
    Assignee: Micron Technology Inc.
    Inventors: Randhir Thakur, James Pan
  • Patent number: 6090688
    Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: July 18, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
  • Patent number: 6054062
    Abstract: A method and apparatus agitates an etchant contained within a bath. A wafer is immersed in a bath containing an etchant that is continuously mixed by release of a gas, preferably nitrogen, into the bath at a sufficient flow rate to agitate the etchant and assure a robust and substantially uniform selective etching process. The apparatus comprises valve assembly that receives gas from a source of gas under pressure and controls the flow rate and release pressure of the gas. In addition, the valve assembly contains an on/off valve that, when turned on, releases gas for a predetermined time period. Accordingly, a single operation of the on/off valve releases gas for the duration of a single selective etching cycle. A dispersion plate receives the gas from the valve assembly for release into the bath. The released gas passes through the baffle distribution plate that distributes the gas throughout the bath.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: April 25, 2000
    Assignee: LSI Logic Corporation
    Inventors: Jeffrey C. Calio, Stephanie A. Yoshikawa, Timothy Hendrix
  • Patent number: 6044850
    Abstract: Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: April 4, 2000
    Assignee: Fujitsu Limited
    Inventors: Soichiro Ozawa, Satoru Mihara, Kunihiko Nagase, Masaaki Aoyama, Naoki Nishida
  • Patent number: 6033583
    Abstract: A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: March 7, 2000
    Assignee: The Regents of the University of California
    Inventors: Ronald G. Musket, John D. Porter, James M. Yoshiyama, Robert J. Contolini
  • Patent number: 6025270
    Abstract: An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: February 15, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chue-San Yoo
  • Patent number: 6024884
    Abstract: Microstructures are ion milled in an existing layer by a process including forming a metal mask then milling in the presence of a reactive gas which combines with the metal to form a surface that mills at a lower rate than the metal alone. The metal mask is formed through wet etching, with a wet etch stop film preventing the existing layer from being attacked by the wet etchant. In a preferred embodiment, cobalt-zirconium-tantalum (CZT) is milled to form top poles for tape write heads. A gold. (Au) wet etch stop film is first applied to the CZT layer. Next, a titanium (Ti) layer is deposited. A photoresist mask is formed and the Ti is wet etched, producing a metal mask. Milling with nitrogen (N.sub.2) in the presence of argon (Ar) ions causes the exposed layer of Ti to form titanium nitride (TiN), which mills at a slower rate than Ti.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: February 15, 2000
    Assignee: Storage Technology Corporation
    Inventors: Steven R. Bryant, Steven C. Herrera
  • Patent number: 5967156
    Abstract: In one aspect, foreign material on the surface of a substrate is processed to form a reaction product by: providing a directed flow of a fluid, comprising a reactant, to the vicinity of the foreign material to be processed; and delivering an aerosol of at least partially frozen particles continuously or intermittently to the foreign material to aid the reactant react with the foreign material to form the reaction product. In another aspect, foreign material is processed by: providing a directed flow of a fluid, comprising a reactant, to the foreign material to be processed in a limited area reaction region corresponding to a minor fraction of the total area of the substrate; agitating the foreign material in the limited area reaction region to aid the reactant react with the foreign material to form the reaction product; and providing relative motion between the substrate and the directed flow of fluid to achieve a substantially uniform exposure of the foreign material to fluid flow and the agitation.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: October 19, 1999
    Assignee: Krytek Corporation
    Inventors: Peter H. Rose, Piero Sferlazzo
  • Patent number: 5928960
    Abstract: According to the present invention, an improved method for planarizing the surface of a dielectric or metal layer in an integrated circuit manufacturing process is disclosed. The dielectric or metal layer to be planarized is selectively patterned and etched over different regions of the surface. The size, shape, density, and depth of the patterns are determined by the pattern factor of the integrated circuit structures underlying the layer to be planarized. Further, by using the pattern factor of the underlying structures to determine the density, size, depth and placement of the surface pattern, the overall planarization process can be improved. Other empirically determined factors, such as material strength, CMP slurry temperature, and pad pressure can also be used to further refine the CMP process. By varying the pattern over the entire surface of the layer to be planarized, the CMP material removal rate can be controlled to achieve a more planar surface.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Nancy Anne Greco, Stephen Edward Greco
  • Patent number: 5916453
    Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: June 29, 1999
    Assignee: Fujitsu Limited
    Inventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-chou Vincent Wang
  • Patent number: 5895583
    Abstract: Silicon carbide wafers are prepared for semiconductor epitaxial growth by first lapping a silicon carbide wafer derived from a boule, by placing the wafer in a recess of a metal backed template and moving the wafer over and against a rotating plate. Two different diamond slurry mixtures of progressively smaller diamond grit sizes are sequentially used, along with a lubricant, for a predetermined period of time. The lapping operation is followed by a polishing operation which sequentially utilizes two different diamond slurry mixtures of progressively smaller diamond grit sizes, along with three different apertured pads sequentially applied to a rotatable plate, with the pads being of progressively softer composition. In a preferred embodiment the wafers are cleaned and the templates are changed after each new diamond slurry mixture used.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: April 20, 1999
    Assignee: Northrop Grumman Corporation
    Inventors: Godfrey Augustine, Donovan L. Barrett, Elizabeth Ann Halgas
  • Patent number: 5890501
    Abstract: Disclosed is a method of dissolving a surface of a semiconductor substrate or a thin-film surface layer formed on the semiconductor substrate, with an oxidizing agent and fluorine-series gas. The method is characterized in that an initial dissolution rate is controlled by gradually increasing a concentration of fluorine-series gas introduced in a dissolving solution containing the oxidizing agent.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minako Kaneko, Ayako Shimazaki, Itsuro Ishizaki
  • Patent number: 5863829
    Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: January 26, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yuichi Nakayoshi, Hiroaki Yamamoto, Akihiro Ishii
  • Patent number: 5801070
    Abstract: A gas sensor and a method for measuring gas constituents, particularly exhaust gas constituents for an internal combustion engine, comprising a pair of polysilicon plates, each plate supporting a pair of resistors, one serving as a heater and the other as a thermometer, one plate being coated with a catalyst to promote combustion of unburned combustible gas constituents, wherein provision is made for reducing temperature gradients across the plates and for effecting temperature uniformity of the catalyst while maintaining a high degree of structural integrity.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: September 1, 1998
    Assignee: Ford Global Technologies, Inc.
    Inventors: Margherita Zanini-Fisher, Jacobus Visser
  • Patent number: 5795492
    Abstract: A metal, such as Platinum, is stripped from a wafer during processing of an integrated circuit. The wafer, typically within a cassette of wafers, is submerged in de-ionized water. The de-ionized water is, for example, held within a container made of quartz. Optimally, the de-ionized water is heated, for example, to a temperature of 80 degrees Centigrade. Chlorine gas and hydrochloric acid gas are bubbled into the de-ionized water to oxidize the metal.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Kenneth Reis, Allen Page
  • Patent number: 5746930
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5662815
    Abstract: A multiple micro-tip field emission device is fabricated by forming a titanium adhesion layer under a striped tungsten cathode, etching the tungsten cathode radially using an aluminum mask and selectively etching the titanium adhesion layer, so that multiple micro-tips are formed due to the intrinsic internal stress of the tungsten itself. Thereby, the adjustment of the tip size is optionally available during the process and has excellent reproducibility since the process uses the intrinsic internal stress of the tungsten and the characteristic of a buffered oxide etching (BOE) method. Also, the output current can be controlled in a wide range from nA to mA because of the multiple micro-tips. By forming the tips with tungsten, the device has good strength, oxidation characteristics and work function and has good electrical, chemical and mechanical endurance.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: September 2, 1997
    Assignee: Samsung Display Devices Co., Ltd.
    Inventor: Jong-min Kim
  • Patent number: 5632847
    Abstract: The method of removing a film from a substrate (wafer) comprises a step of injecting ozone (13) into an acid aqueous solution (12) (e.g., a mixed liquid of dilute hydrogen fluoride aqueous solution and dilute hydrochloric acid); and a step of bringing bubbles (18) formed by the ozone injection step into contact with a film (17) (e.g., organic or metal contaminated film) adhering on to the substrate to remove the film (17) from the substrate (16). Therefore, the organic film or metal contaminated film adhering onto the substrate surface can be removed easily and effectively. Further, the film removing agent is bubbles formed when ozone (13) is injected into an acid aqueous solution. Each bubble is composed of an inside ozone bubble and an outside acid aqueous solution bubble. Therefore, when the bubbles are brought into contact with the film, an intermediate between ozone and the film is first formed, and then the formed intermediate can be removed from the substrate by the acid aqueous solution.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: May 27, 1997
    Assignees: Chlorine Engineers Corp., Ltd., Kabushiki Kaisha Toshiba
    Inventors: Reiko Ohno, Terumi Matsuoka
  • Patent number: 5626773
    Abstract: An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) regions of the substrate (46). A second layer of metal contacts (62) is formed on the first layer of contacts (60). A radiation etch mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). A dry-etch mask layer (74) is formed to encapsulate the exposed portions of the first layer of contacts (60) and radiation etch mask layer (66). An initial portion of each unmasked region (68) is etched using a dry-etch process. The remaining portions of the unmasked regions (68) are exposed to an etchant (70) and irradiated with electromagnetic energy to substantially increase the reactivity between the remaining portions and the etchant (70).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: May 6, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5567332
    Abstract: A gaseous process for removing and vaporizing at least a portion of a silicon oxide film from between a substrate and a superstructure leaving a space between the substrate and the superstructure. The silicon oxide layer is removed in two steps. In the first step the bulk of the silicon oxide layer is removed by a rapid liquid or gaseous etching process, leaving at least a portion of the silicon oxide layer directly underlying the superstructure in place so as to support the superstructure during a wash cycle. In the second silicon oxide removal step the substrate is introduced to a high flow rate gaseous environment containing a relatively high concentration of anhydrous HF to which no, or only a relatively very low amount of, additional water vapor is provided until the silicon oxide directly underlying the superstructure has been removed.
    Type: Grant
    Filed: June 9, 1995
    Date of Patent: October 22, 1996
    Assignee: FSI International
    Inventor: Jitesh Mehta
  • Patent number: 5520299
    Abstract: This is a system and method of etching pyroelectric devices post ion milling. The method may comprise: forming a mask 32 for thermal isolation trenches on a substrate 14; ion milling thermal isolation trenches 40 in the substrate 14; and etching undesired defects 44 caused by the ion milling by applying a dry etch, a solvent etch, or a liquid etch to the trenches. The etch may include: hydrofluoric acid, perchloric acid, a solution of a chlorine salt and water which is then exposed to ultraviolet light or any similar chemical solution giving the correct reducing properties. The mask 32 and ion milling may be applied from either the front side or the back side of the infrared detector.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: May 28, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan
  • Patent number: 5515984
    Abstract: A method for etching a Pt film of the present invention includes the steps of: forming an etching resistant film on a Pt film, followed by patterning; etching the Pt film by using as an etching mask the etching resistant film and by using, as an etching gas, a mixed gas containing oxygen gas and chlorine gas or chloride gas, during which layers made of PtCl.sub.x O.sub.y or a mixture containing PtCl.sub.x and PtO.sub.y are formed on side walls of the etching resistant film and the Pt film; and removing the layers made of PtCl.sub.x O.sub.y or the mixture containing PtCl.sub.x and PtO.sub.y with an acid by wet etching after the etching step.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: May 14, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichi Yokoyama, Yasuyuki Ito, Shigeo Onishi, Jun Kudo, Keizo Sakiyama
  • Patent number: 5464480
    Abstract: Provided is a process for removing organic materials from semiconductor wafers. The process involves the use of subambient deionized water with ozone absorbed into the water. The ozonated water flows over the wafers and the ozone oxidizes the organic materials from the wafers to insoluble gases. The ozonated water may be prepared in-situ by diffusing ozone into a tank containing wafers and subambient deionized water. Also provided is a tank for the treatment of semiconductor wafers with a fluid and a gas diffuser for diffusion of gases directly into fluids in a wafer treatment tank.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: November 7, 1995
    Assignee: Legacy Systems, Inc.
    Inventor: Robert R. Matthews
  • Patent number: 5431774
    Abstract: A dry etch for metals such as copper using .pi.-acids in an energetic environment such as a plasma, laser, or afterglow reactor (102) or by using ligands forming volatiles at low temperature within a pulsed energetic environment.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: July 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Monte A. Douglas
  • Patent number: 5417799
    Abstract: A process is provided for modifying a surface of a large area, non-planar substrate to form micro structures therein that alter its optical properties. The process includes forming the micro structures by reactive ion beam etching through a chosen pattern that has been prepared on the surface.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: May 23, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Thomas W. Daley, Charles L. Schaub, Hugh L. Garvin, Klaus Robinson