Etchant Is Devoid Of Chlorocarbon Or Fluorocarbon Compound (e.g., C.f.c., Etc.) Patents (Class 216/64)
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Patent number: 11227774Abstract: Methods and systems for etching SiCN with mutli-color selectivity may include receiving the substrate having a multi-line layer formed thereon, the multi-line layer including a region having a pattern of alternating lines of a plurality of materials, wherein each line has a horizontal thickness, a vertical height, and extends horizontally across an underlying layer, wherein each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer. Such a method may also include forming a patterned recess in the multi-line layer to expose at least a first component of the multi-line layer and a second component of the multi-line layer. An embodiment of a method many also include etching the first component with a non-corrosive etch process that is selective to the second component.Type: GrantFiled: November 25, 2020Date of Patent: January 18, 2022Assignee: Tokyo Electron LimitedInventors: Shihsheng Chang, Andrew Metz
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Patent number: 10559472Abstract: An embodiment of the present disclosure provides a method of processing a workpiece in which a plurality of holes are formed on a surface of the workpiece. The method includes a first sequence including a first process of forming a film with respect to an inner surface of each of the holes and a second process of isotropically etching the film. The first process includes a film forming process using a plasma CVD method, and the film contains silicon.Type: GrantFiled: August 24, 2018Date of Patent: February 11, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Masahiro Tabata, Toru Hisamatsu, Yoshihide Kihara
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Patent number: 9991116Abstract: The invention disclosed a method for forming high aspect ratio patterning structure. Firstly, forming a dielectric film ashing stop layer, a first photoresist layer, a first hard mask layer and a second photoresist layer on a semiconductor substrate in turn. A second hard mask layer having a high etch selectivity ratio with the first photoresist layer is formed on top surface and sidewall of the pattern by utilizing a low temperature chemical vapor deposition process, which can be a protect for the pattern sidewall during the later etching process of the first photoresist layer. So, the cone-shaped or the bowling-shaped photoresist morphology caused by plasma bombardment can be avoided. Therefore, the problems of the insufficient of selectivity ratio, burrs at the edge of the pattern and larger critical dimension can be solved, and the implanted ions can be well distributed according to the design of the device.Type: GrantFiled: December 21, 2016Date of Patent: June 5, 2018Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Peng Liu, Qiyan Feng, Yu Ren, Yukun Lv, Jun Zhu, Hsusheng Chang
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Patent number: 9502264Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.Type: GrantFiled: August 17, 2015Date of Patent: November 22, 2016Assignee: IMEC VZWInventors: Eddy Kunnen, Vasile Paraschiv
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Patent number: 9202707Abstract: A semiconductor device manufacturing method is provided that includes etching with a plasma a multilayer film including a first film and a second film with differing dielectric constants alternately stacked on a substrate using a photoresist layer arranged on the multilayer film as a mask, and forming the multilayer film into a stepped configuration. The semiconductor device manufacturing method includes repetitively performing a first step of etching the first film using the photoresist layer as the mask; a second step of adjusting a pressure within a processing chamber to 6-30 Torr, generating the plasma by applying a first high frequency power for biasing and a second high frequency power for plasma generation to the lower electrode, and etching the photoresist layer using the generated plasma; and a third step of etching the second film using the photoresist layer and the first film as the mask.Type: GrantFiled: February 5, 2013Date of Patent: December 1, 2015Assignee: Tokyo Electron LimitedInventors: Masaya Kawamata, Masanobu Honda
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Patent number: 9039911Abstract: Methods for etching a substrate in a plasma processing chamber having at least a primary plasma generating region and a secondary plasma generating region separated from said primary plasma generating region by a semi-barrier structure. The method includes generating a primary plasma from a primary feed gas in the primary plasma generating region. The method also includes generating a secondary plasma from a secondary feed gas in the secondary plasma generating region to enable at least some species from the secondary plasma to migrate into the primary plasma generating region. The method additionally includes etching the substrate with the primary plasma after the primary plasma has been augmented with migrated species from the secondary plasma.Type: GrantFiled: September 25, 2012Date of Patent: May 26, 2015Assignee: Lam Research CorporationInventors: Eric A. Hudson, Andrew D. Bailey, III, Rajinder Dhindsa
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Publication number: 20150072526Abstract: Embodiments of methods for removing carbon-containing films are provided herein. In some embodiments, a method for removing a carbon-containing layer includes providing an ammonia containing process gas to a process chamber having a substrate with a silicon oxide layer disposed atop the substrate and a carbon-containing layer disposed atop the silicon oxide layer disposed in the process chamber; providing RF power to the process chamber to ignite the ammonia containing process gas to form a plasma; and exposing the substrate to NH and/or NH2 radicals and hydrogen radicals formed in the plasma to remove the carbon-containing layer.Type: ApplicationFiled: September 12, 2014Publication date: March 12, 2015Inventors: WEI LIU, NAOMI YOSHIDA, MANDAR BALASAHEB PANDIT
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Patent number: 8951428Abstract: This invention presents a method for the fabrication of periodic nanostructures on polymeric surfaces by means of plasma processing, which method comprises the following steps: (i) provision of a homogeneous organic polymer (such as PMMA, or PET, or PEEK, or PS, or PE, or COC) or inorganic polymer (such as PDMS or ORMOCER); (ii) exposure of the polymer to an etching plasma such as oxygen (O2) or sulphur hexafluoride (SF6) or a mixture of oxygen (O2) and sulphur hexafluoride (SF6), or mixtures of etching gases with inert gases such as any Noble gas (Ar, He, Ne, Xe).Type: GrantFiled: June 15, 2009Date of Patent: February 10, 2015Inventors: Evangelos Gogolides, Angeliki Tserepi, Vassilios Constantoudis, Nikolaos Vourdas, Georgios Boulousis, Maria-Elena Vlachopoulou, Aikaterini Tsougeni, Dimitrios Kontziampasis
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Patent number: 8871102Abstract: A method for fabricating a structure in magnetic recording head is described. First and second hard mask layers are provided on the layer(s) for the structure. A BARC layer and photoresist mask having a pattern are provided on the second hard mask layer. The pattern includes a line corresponding to the structure. The pattern is transferred to the BARC layer and the second hard mask layer in a single etch using an etch chemistry. At least the second hard mask layer is trimmed using substantially the same first etch chemistry. A mask including a hard mask line corresponding to the line and less than thirty nanometers wide is thus formed. The pattern of the second hard mask is transferred to the first hard mask layer. The pattern of the first hard mask layer is transferred to the layer(s) such that the structure has substantially the width.Type: GrantFiled: May 25, 2011Date of Patent: October 28, 2014Assignee: Western Digital (Fremont), LLCInventor: Wei Gao
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Patent number: 8821739Abstract: A method for processing a substrate is provided; wherein the method comprises applying a film of a copolymer composition, comprising a poly(styrene)-b-poly(siloxane) block copolymer component; and, an antioxidant to a surface of the substrate; optionally, baking the film; subjecting the film to a high temperature annealing process under a gaseous atmosphere for a specified period of time; followed by a treatment of the annealed film to remove the poly(styrene) from the annealed film and to convert the poly(siloxane) in the annealed film to SiOx.Type: GrantFiled: July 12, 2012Date of Patent: September 2, 2014Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLCInventors: Xinyu Gu, Shih-Wei Chang, Phillip D. Hustad, Jeffrey D. Weinhold, Peter Trefonas
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Patent number: 8821738Abstract: A method for processing a substrate is provided; wherein the method comprises applying a film of a copolymer composition, comprising a poly(styrene)-b-poly(siloxane) block copolymer component; and, an antioxidant to a surface of the substrate; optionally, baking the film; annealing the film in a gaseous atmosphere containing ?20 wt % oxygen; followed by a treatment of the annealed film to remove the poly(styrene) from the annealed film and to convert the poly(siloxane) in the annealed film to SiOx.Type: GrantFiled: July 12, 2012Date of Patent: September 2, 2014Assignees: Rohm and Haas Electronic Materials LLC, Dow Global Technologies LLCInventors: Phillip D. Hustad, Xinyu Gu, Shih-Wei Chang, Jeffrey D. Weinhold, Peter Trefonas
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Patent number: 8771538Abstract: Embodiments of the present invention generally provide a plasma source apparatus, and method of using the same, that is able to generate radicals and/or gas ions in a plasma generation region that is symmetrically positioned around a magnetic core element by use of an electromagnetic energy source. In general, the orientation and shape of the plasma generation region and magnetic core allows for the effective and uniform coupling of the delivered electromagnetic energy to a gas disposed in the plasma generation region. In general, the improved characteristics of the plasma formed in the plasma generation region is able to improve deposition, etching and/or cleaning processes performed on a substrate or a portion of a processing chamber that is disposed downstream of the plasma generation region.Type: GrantFiled: November 18, 2010Date of Patent: July 8, 2014Assignee: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Jang-Gyoo Yang, Matthew Miller, Jay Pinson, Kien Chuc
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Patent number: 8623230Abstract: The present method relates to processes for the removal of a material from a sample by a gas chemical reaction activated by a charged particle beam. The method is a multiple step process wherein in a first step a gas is supplied which, when a chemical reaction between the gas and the material is activated, forms a non-volatile material component such as a metal salt or a metaloxide. In a second consecutive step the reaction product of the first chemical reaction is removed from the sample.Type: GrantFiled: December 18, 2008Date of Patent: January 7, 2014Assignee: Carl Zeiss SMS GmbHInventors: Nicole Auth, Petra Spies, Tristan Bret, Rainer Becker, Thorsten Hofmann, Klaus Edinger
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Patent number: 8617411Abstract: Substrate processing systems and methods for etching an atomic layer are disclosed. The methods and systems are configured to introducing a first gas into the chamber, the gas being an etchant gas suitable for etching the layer and allowing the first gas to be present in the chamber for a period of time sufficient to cause adsorption of at least some of the first gas into the layer. The first gas is substantially replaced in the chamber with an inert gas, and metastables are then generated from the inert gas to etch the layer with the metastables while substantially preventing the plasma charged species from etching the layer.Type: GrantFiled: July 20, 2011Date of Patent: December 31, 2013Assignee: Lam Research CorporationInventor: Harmeet Singh
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Patent number: 8591661Abstract: Improved methods for stripping photoresist and removing etch-related residues from dielectric materials are provided. In one aspect of the invention, methods involve removing material from a dielectric layer using a hydrogen-based etch process employing a weak oxidizing agent and fluorine-containing compound. Substrate temperature is maintained at a level of about 160° C. or less, e.g., less than about 90° C.Type: GrantFiled: December 11, 2009Date of Patent: November 26, 2013Assignee: Novellus Systems, Inc.Inventors: David Cheung, Ted Li, Anirban Guha, Kirk Ostrowski
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Publication number: 20130284701Abstract: [Object] To provide a method of manufacturing a dielectric device and an ashing method that are capable of suppressing the occurrence of resist residue. [Solving Means] In the ashing method, a base material having a surface etched by a plasma of chlorine gas or fluorocarbon gas via a resist mask (6) formed of an organic material is disposed in a chamber, bombardment treatment is performed on the resist mask (6) by using oxygen ions in the chamber, and the resist mask is removed by using oxygen radicals in the chamber. According to the ashing method described above, etching reactants adhering to the surface of the resist mask are physically removed by the bombardment treatment using oxygen ions. Thus, it is possible to suppress the occurrence of resist residue due to the etching reactants and efficiently remove the resist mask from the surface of the base material.Type: ApplicationFiled: December 19, 2011Publication date: October 31, 2013Applicant: ULVAC, INC.Inventors: Yoshiaki Yoshida, Yutaka Kokaze
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Patent number: 8506718Abstract: A polymer removing apparatus for use in removing polymer annularly adhered to a peripheral portion of a target substrate includes a processing chamber for accommodating the target substrate having the polymer annularly adhered to the peripheral portion thereof; a mounting table for mounting the target substrate thereon; and a laser irradiation unit for irradiating ring-shaped laser light at once to the whole polymer annularly adhered to the target substrate. The polymer removing apparatus further includes an ozone gas supply unit for supplying an ozone gas to the polymer annularly adhered to the target substrate and a gas exhaust unit for exhausting the ozone gas.Type: GrantFiled: August 17, 2010Date of Patent: August 13, 2013Assignee: Tokyo Electron LimitedInventors: Takehiro Shindou, Masaki Kondo
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Patent number: 8486741Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.Type: GrantFiled: May 25, 2012Date of Patent: July 16, 2013Assignee: STMicroelectronics S.r.l.Inventors: Pietro Montanini, Giovanna Germani, Ilaria Gelmi, Marta Mottura
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Patent number: 8444869Abstract: A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable the simultaneous removal of material from the wafer front side, backside and edges. The apparatus may include a single processing station having the gap residing therein, or the apparatus may include a plurality of processing stations, each capable of forming the gap therein for simultaneously removing additional material from the wafer front side, backside and edges.Type: GrantFiled: May 24, 2010Date of Patent: May 21, 2013Assignee: Novellus Systems, Inc.Inventors: Haruhiro Harry Goto, David Cheung
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Patent number: 8372298Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by a procedure in which a silicon wafer on a susceptor in the epitaxy reactor, is pretreated in a first step with a hydrogen flow rate of 1-100 slm and in a second step with hydrogen and an etching medium at a hydrogen flow rate of 1-100 slm, and an etching medium flow rate of 0.5-1.5 slm, at an average temperature of 950-1050° C., and is subsequently coated epitaxially, wherein, during the second pretreatment step, the power of heating elements is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical central region of the silicon wafer and an outer region of the silicon outside the central region.Type: GrantFiled: February 2, 2010Date of Patent: February 12, 2013Assignee: Siltronic AGInventor: Joerg Haberecht
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Publication number: 20130028829Abstract: Disclosed herein is a method of growth of enhanced adhesion MWCNTs on a substrate, referred to as the HGTiE process, the method comprising: chemical vapor deposition of an adhesive underlayer composed of alumina on a substrate composed of titanium or similar; chemical vapor deposition of a catalyst such as a thin film of iron on top of the adhesive underlayer; pretreatment of the substrate to hydrogen at high temperature; and exposure of the substrate to a feedstock gas such as ethylene at high temperature. The substrate surface may be roughened before placement of an adhesive layer through mechanical grinding or chemical etching. Finally, plasma etching of the MWCNT film may be performed with oxygen plasma. This method of growth allows for high strength adhesion of MWCNTs to the substrate the MWCNTs are grown upon.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Inventors: John G. Hagopian, Stephanie A. Getty, Manuel A. Quijada
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Patent number: 8128831Abstract: A plasma processing apparatus includes a first and a second electrode disposed to face each other in a processing chamber, the second electrode supporting a substrate; a first RF power supply for applying a first RF power of a higher frequency to the second electrode; a second RF power supply for applying a second RF power of a lower frequency to the second electrode; and a DC power source for applying a DC voltage to the first electrode. In a plasma etching method for etching a substrate by using the plasma processing apparatus, the first and the second radio frequency power are applied to the second electrode to convert a processing gas containing no CF-based gas into a plasma and a DC voltage is applied to the first electrode, to thereby etch an organic film or an amorphous carbon film on the substrate by using a silicon-containing mask.Type: GrantFiled: December 28, 2006Date of Patent: March 6, 2012Assignee: Tokyo Electron LimitedInventors: Manabu Sato, Yoshiki Igarashi, Yoshimitsu Kon, Masanobu Honda
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Patent number: 8097088Abstract: Methods for processing substrates in dual chamber processing systems comprising first and second process chambers that share resources may include performing a first internal chamber clean in each of the first process chamber and the second process chamber; and subsequently processing a substrate in one of the first process chamber or the second process chamber by: providing a substrate to one of the first process chamber or the second process chamber; providing a process gas to the first process chamber and the second process chamber; forming a plasma in only the one of the first process chamber or the second process chamber having the substrate contained therein; and providing an inert gas to the first process chamber and the second process chamber via one or more channels formed in a surface of respective substrate supports disposed in the first process chamber and the second process chamber while processing the substrate.Type: GrantFiled: April 18, 2011Date of Patent: January 17, 2012Assignee: Applied Materials, Inc.Inventors: Eu Jin Lim, Adauto Diaz, Jr., Benjamin Schwarz, James P. Cruse, Charles Hardy
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Patent number: 8066894Abstract: A substrate can be appropriately oxidized, while oxidation of the substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a processing chamber to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the processing chamber to form a plasma discharge, and processing the substrate by the hydrogen plasma.Type: GrantFiled: March 14, 2006Date of Patent: November 29, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
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Publication number: 20110165382Abstract: This invention presents a method for the fabrication of periodic nanostructures on polymeric surfaces by means of plasma processing, which method comprises the following steps: (i) provision of a homogeneous organic polymer (such as PMMA, or PET, or PEEK, or PS, or PE, or COC) or inorganic polymer (such as PDMS or ORMOCER); (ii) exposure of the polymer to an etching plasma such as oxygen (O2) or sulphur hexafluoride (SF6) or a mixture of oxygen (O2) and sulphur hexafluoride (SF6), or mixtures of etching gases with inert gases such as any Noble gas (Ar, He, Ne, Xe).Type: ApplicationFiled: June 15, 2009Publication date: July 7, 2011Applicant: NATIONAL CENTER FOR SCIENTIFIC RESEARCH "DEMOKRITOS"Inventors: Evangelos Gogolides, Aagelike Tserepi, Vassilios Constantoudis, Nikolaos Vourdas, Georgios Boulousis, Maria-Elenma Vlachopoulou LACHOPOULOU, Aikaterini Tsougeni, Dimitrios Kontziampasis
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Patent number: 7955512Abstract: Disclosed are medical devices having textured surfaces and related methods for texturing. Methods of surface texturing using gas-phase plasma provide medical devices with myriad complex surface morphologies.Type: GrantFiled: February 13, 2007Date of Patent: June 7, 2011Assignee: Medtronic, Inc.Inventors: Eunsung Park, Catherine E. Taylor, Kevin Casey
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Patent number: 7955510Abstract: The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first gas and a second gas, and a ratio of the first gas and a second gas is determined by the desired removal rate.Type: GrantFiled: December 18, 2009Date of Patent: June 7, 2011Assignee: Applied Materials, Inc.Inventors: Reza Arghavani, Chien-Teh Kao, Xinliang Lu
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Patent number: 7938976Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.Type: GrantFiled: February 27, 2007Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventor: Kang-Wook Lee
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Publication number: 20110049099Abstract: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing a non-carbon containing trim gas comprising oxygen and a fluorine containing compound, forming a plasma from the trim gas, and trimming the hardmask. Features are etched into the polysilicon layer through the hardmask.Type: ApplicationFiled: November 9, 2010Publication date: March 3, 2011Applicant: LAM RESEARCH CORPORATIONInventor: Tom A. Kamp
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Patent number: 7851367Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage.Type: GrantFiled: March 15, 2007Date of Patent: December 14, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Akio Ui
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Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces
Patent number: 7771541Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.Type: GrantFiled: March 22, 2007Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla -
Patent number: 7718543Abstract: Methods for removing a BARC layer from a feature are provided in the present invention. In one embodiment, the method includes providing a substrate having a feature filled with a BARC layer in an etching chamber, supplying a first gas mixture comprising NH3 gas into the chamber to etch a first portion of the BARC layer filling in the feature, and supplying a second gas mixture comprising O2 gas into the etching chamber to etch the remaining portion of the BARC layer disposed in the feature.Type: GrantFiled: December 8, 2006Date of Patent: May 18, 2010Assignee: Applied Materials, Inc.Inventors: Zhilin Huang, Siyi Li, Gerardo A. Delgadino
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Patent number: 7682517Abstract: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The surface damaged layer that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: GrantFiled: February 14, 2006Date of Patent: March 23, 2010Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Kenya Iwasaki
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Publication number: 20090255900Abstract: An oil gas separation membrane combines a gas permeable yet oil and temperature resistant bulk polymer membrane such as poly(tetrafluoroethylene) and poly(tetrafluoroethylene-co-hexafluoropropylene); a porous metal support such as sintered metal frit disk made with stainless steel, bronze or nickel; and an highly gas permeable adhesive that bonds firmly the bulk polymer membrane and the metal frit surface together. The adhesive is either a homogenous polymer that has desirable gas permeability, or a coalescent porous polymer particulates network.Type: ApplicationFiled: May 28, 2009Publication date: October 15, 2009Inventor: Ren Yan Qin
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Publication number: 20090218315Abstract: A method and system for controlling the center-to-edge distribution of a species within a plasma is provided. In one embodiment, the invention provides a method for plasma processing, comprising determining plasma processing center-to-edge profile requirements of a substrate, and selecting a ratio of two inert gases to be provided to a plasma processing chamber in response to the plasma processing center to edge profile requirements.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Inventor: Steven Shannon
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Publication number: 20090050604Abstract: Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.Type: ApplicationFiled: August 22, 2007Publication date: February 26, 2009Inventors: Jeannette Michelle Jacques, Yong Seok Choi
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Publication number: 20080230519Abstract: A method and system of etching a metal nitride, such as titanium nitride, is described. The etching process comprises introducing a process composition having a halogen containing gas, such as Cl2, HBr, or BCl3, and a fluorocarbon gas having the chemical formula CxHyFz, where x and z are equal to unity or greater and y is equal to 0 or greater.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicant: TOKYO ELECTRON LIMITEDInventor: Hiroyuki Takahashi
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Patent number: 7344996Abstract: Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.Type: GrantFiled: June 22, 2005Date of Patent: March 18, 2008Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Wenxian Zhu, Ratsamee Limdulpaiboon, Judy H. Huang
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Patent number: 7270761Abstract: A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.Type: GrantFiled: October 18, 2002Date of Patent: September 18, 2007Assignee: Appleid Materials, IncInventors: Xikun Wang, Hui Chen, Anbei Jiang, Hong Shih, Steve S. Y. Mak
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Patent number: 7169440Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.Type: GrantFiled: September 30, 2002Date of Patent: January 30, 2007Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
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Patent number: 7122125Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.Type: GrantFiled: November 4, 2002Date of Patent: October 17, 2006Assignee: Applied Materials, Inc.Inventors: Shashank C. Deshmukh, Thorsten B. Lill
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Patent number: 6949202Abstract: Processes for the addition or removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the use of recirculation of the process gas. Recirculation is effected by a pump that has no sliding or abrading parts that contact the process gas, nor any wet (such as oil) seals or purge gas in the pump. Improved processing can be achieved by a process chamber that contains a baffle, a perforated plate, or both, appropriately situated in the chamber to deflect the incoming process gas and distribute it over the workpiece surface. In certain embodiments, a diluent gas is added to the recirculation loop and continuously circulated therein, followed by the bleeding of the process gas (such as an etchant gas) into the recirculation loop. Also, cooling of the process gas, etching chamber and/or sample platen can aid the etching process. The method is particularly useful for adding to or removing material from a sample of microscopic dimensions.Type: GrantFiled: August 28, 2000Date of Patent: September 27, 2005Assignee: Reflectivity, INCInventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Niles K. MacDonald
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Patent number: 6902683Abstract: A method of plasma-processing is provided which includes placing a sample on one of electrodes provided in a vacuum processing chamber and holding the sample onto the electrodes by an electrostatic attracting force. A processing gas is introduced into an environment in which said sample is placed, and the environment is evacuated to a pressure condition for processing said sample. The processing gas is then formed into a plasma under the pressure condition, the sample is processed by the plasma, and a pulse bias voltage having a pulse cycle of 0.1 ?m to 10 ?m is applied to the sample.Type: GrantFiled: May 5, 2000Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Tetsunori Kaji, Shinichi Tachi, Toru Otsubo, Katsuya Watanabe, Katsuhiko Mitani, Junichi Tanaka
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Patent number: 6886573Abstract: A process for cleaning a deposit from an interior surface of a processing chamber includes generating a plasma from a cleaning gas including SO2F2 and contacting the interior surface with the plasma for a time sufficient to convert the deposit into a volatile product, thereby cleaning the deposit from the interior surface, in which the process is conducted in the absence of SF6. The deposits, which may be removed by the process of the invention, include silicone, silicone oxide, silicone nitride, tungsten, copper and aluminum.Type: GrantFiled: September 6, 2002Date of Patent: May 3, 2005Assignee: Air Products and Chemicals, Inc.Inventors: John Peter Hobbs, James Joseph Hart
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Patent number: 6863936Abstract: A method of plating an aromatic polymer substrate comprises: applying a strippable coating of a non-aromatic polymer to a substrate surface to be plated; selectively illuminating the coated substrate surface with laser light to ablate a selected area of the strippable coating and to activate an underlying region of the substrate surface exposed by the ablation of the strippable coating; contacting the substrate surface with a seeding solution containing polymer-stabilised catalytic seeding particles, so that the seeding particles adhere preferentially to the activated region of the substrate; and electrolessly plating the substrate surface, whereby the seeded areas of the substrate surface are selectively plated.Type: GrantFiled: December 18, 2001Date of Patent: March 8, 2005Assignee: Agency for Science, Technology and ResearchInventors: William T. Chen, Peter M. Moran, Harvey M. Phillips
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Patent number: 6858153Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: November 5, 2001Date of Patent: February 22, 2005Assignee: Applied Materials Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 6854175Abstract: A method of manufacturing a thin film magnetic head capable of improving a yield while making a pole width extremely minute with high precision is provided. A write gap layer and a bottom pole are selectively etched in a region other than a portion corresponding to a front end part through the RIE with the front end part having an extremely minute uniform width as a mask in an atmosphere of gas including at least chlorine out of chlorine and boron trichloride and at an ambient temperature within a range of 30° C. to 300° C. The width (pole width) of a pole portion can be made uniform with high precision along a length direction so that the yield of the thin film magnetic head can be improved.Type: GrantFiled: October 12, 2001Date of Patent: February 15, 2005Assignee: TDK CorporationInventor: Yoshitaka Sasaki
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Patent number: 6849192Abstract: There is provided a method for surface treating where the environmental load is small. The surface treating method of the invention comprises that a cluster bonded by the first molecule and the second molecule by means of an intermolecular force is produced in a gas phase. At least a part of internal energy released in producing the cluster is utilized whereby the first molecule contained in the cluster is made in a state having higher reactivity than that of the first molecular not bonded with the second molecular. The surface of the member to be treated is treated in a gas phase with the cluster containing the first molecule made in a state of higher reactivity.Type: GrantFiled: November 14, 2003Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Yasushi Nakasaki
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Patent number: 6843858Abstract: A method of operating a substrate processing chamber. In one embodiment the method includes processing one or more substrates in the substrate processing chamber and subsequently cleaning the chamber using a dry cleaning process. This substrate processing and dry cleaning sequence is then repeated multiple times before chamber is further cleaned by flowing a cleaning gas into the chamber and forming a plasma within the chamber from the cleaning gas in an extended cleaning process. During the extended cleaning process the plasma is maintained within the chamber for a total of at least 5 minutes before the chamber is reused to process a substrate.Type: GrantFiled: April 2, 2002Date of Patent: January 18, 2005Assignee: Applied Materials, Inc.Inventor: Kent Rossman
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Patent number: 6811959Abstract: A process for manufacturing and a photomask including a chrome layer over a transparent substrate, followed by a thin hardmask/barrier layer directly over the chrome layer having a thin resist layer thereover. The thin resist layer is patterned and developed wherein the barrier layer acts to retard the formation of a resist “foot” at the bottom of the resist profile. Exposed portions of the hardmask/barrier layer and the underlying chrome layer are etched, and then any remaining hardmask/barrier layer and resist layer is subsequently removed by an etchant. The hardmask/barrier layer directly over the chrome layer enables an improved pattern transfer mask during chrome etching processes, allows for further reduction in the thickness of the resist layer, improves the image quality, the achievable minimum resolution features, and provides nominal image size control and image size uniformity across the photomask within current process flows and manufacturing.Type: GrantFiled: March 4, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventor: Christopher K. Magg