Etching Of Substrate Containing At Least One Compound Having At Least One Oxygen Atom And At Least One Metal Atom Patents (Class 216/76)
  • Patent number: 7425510
    Abstract: Methods of cleaning a processing chamber of semiconductor device fabrication equipment are highly effective in removing polymers produced as a by-product of a fabrication process from surfaces in a processing chamber. The cleaning process uses a plasma etchant produced from cleaning gas including an O-based gas and at least one gas selected from the group consisting of an F-based gas and a Cl-based gas. The polymer is dissolved in-situ using the plasma etchant. Thus, frequency at which PM (preventative maintenance) of the equipment must be performed is minimized, and the method contributes to maximizing the yield and quality of the semiconductor devices.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Ju Kim
  • Patent number: 7368394
    Abstract: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 6, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Meihua Shen, Uwe Leucke, Guangxiang Jin, Xikun Wang, Wei Liu, Scott Williams
  • Patent number: 7361285
    Abstract: A method for fabricating a cliché including: providing a transparent glass substrate; depositing a metal layer on the substrate; patterning the metal layer and thereby forming a first metal pattern; etching the glass substrate by using the first metal pattern as a mask and thereby forming a first convex pattern; patterning the first metal pattern and thereby forming a second metal pattern; and etching the first convex pattern by using the second metal pattern as a mask and thereby forming a second convex pattern.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 22, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Chul-Ho Kim
  • Patent number: 7357138
    Abstract: A process for the removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance having a dielectric constant greater than silicon dioxide from a substrate by reacting the substance with a reactive agent that comprises at least one member from the group consisting a halogen-containing compound, a boron-containing compound, a hydrogen-containing compound, nitrogen-containing compound, a chelating compound, a carbon-containing compound, a chlorosilane, a hydrochlorosilane, or an organochlorosilane to form a volatile product and removing the volatile product from the substrate to thereby remove the substance from the substrate.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: April 15, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Bing Ji, Stephen Andrew Motika, Ronald Martin Pearlstein, Eugene Joseph Karwacki, Jr., Dingjun Wu
  • Patent number: 7354526
    Abstract: A processing method for glass substrate of the present invention includes: applying heat and external force to a glass substrate and then cooling it down to thereby form a compression stressed part having a different etching rate from that of other parts with respect to an etching reagent to be used, on the surface of the glass substrate and in the vicinity thereof, and performing chemical etching using the etching reagent on the glass substrate having the compression stressed part formed thereon, so as to form a relief on the surface of the glass substrate.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: April 8, 2008
    Assignees: Olympus Corporation, Nippon Sheet Glass Co., Ltd.
    Inventors: Takeshi Hidaka, Hiroaki Kasai, Masamichi Hijino, Yasushi Nakamura, Akihiro Koyama, Keiji Tsunetomo, Junji Kurachi, Hirotaka Koyo, Shinya Okamoto, Yasuhiro Saito
  • Patent number: 7335600
    Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 26, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Sheng Chien, Yen-Wu Hsieh
  • Patent number: 7264677
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: September 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Patent number: 7217665
    Abstract: A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: May 15, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani C. Nallan, Guangxiang Jin, Ajay Kumar
  • Patent number: 7187523
    Abstract: A method of marking a sintered body includes the step of preparing the sintered body by sintering a mixture of first and second types of powder particles. The first type of powder particles is made of a first material and the second type of powder particles is made of a second material that has a different etch susceptibility from the first material. The method further includes the step of writing ID information on the surface of the sintered body by forming a first concave region to a depth of at least about 10 nm under the surface of the sintered body and a second concave region under the first concave region, respectively. The first concave region is formed by etching away both the first and second types of powder particles, while the second concave region is formed by etching away only the first type of powder particles.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: March 6, 2007
    Assignee: Neomax Co., Ltd.
    Inventor: Taisuke Hirooka
  • Patent number: 7147794
    Abstract: An optical thin film stack for a dark aperture is deposited using thermal ion-assisted deposition (“IAD”). The IAD provides an energetic deposition of chromium and chromium oxide that results in a dark mirror optical thin film stack with superior etch properties. Edge definition is improved, and the edge profile is controllable by the selection of IAD parameters. An in situ IAD cleaning process can be used to clean the substrate sufficiently so that an intermediate adhesion layer of chromium is not required.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: December 12, 2006
    Assignee: JDS Uniphase Corporation
    Inventor: Paul J. Gasloli
  • Patent number: 7128846
    Abstract: A method including the steps of: modifying at least one part of a sapphire substrate by dry etching to thereby form any one of a dot shape, a stripe shape, a lattice shape, etc. as an island shape on the sapphire substrate; forming an AlN buffer layer on the sapphire substrate; and epitaxially growing a desired Group III nitride compound semiconductor vertically and laterally so that the AlN layer formed on a modified portion of the surface of the sapphire substrate is covered with the desirably Group III nitride compound semiconductor without any gap while the AlN layer formed on a non-modified portion of the surface of the sapphire substrate is used as a seed, wherein the AlN buffer layer is formed by means of reactive sputtering with Al as a target in an nitrogen atmosphere.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: October 31, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Kazuki Nishijima, Masanobu Senda, Toshiaki Chiyo, Jun Ito, Naoki Shibata, Toshimasa Hayashi
  • Patent number: 7111629
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: September 26, 2006
    Assignee: APL Co., Ltd.
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Patent number: 7107998
    Abstract: Carbon monoxide gas is provided in a ruthenium-deposition apparatus to clean undesired ruthenium-containing deposits from apparatus surfaces. Carbon monoxide gas is mixed with reactant gases in apparatus tubing and in a ruthenium-deposition reaction chamber to inhibit formation of undesired ruthenium deposits on apparatus surfaces and to remove ruthenium deposits.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: September 19, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Harold F. R. Greer, James A. Fair, Junghwan Sung, Nerissa Sue Draeger
  • Patent number: 7096873
    Abstract: A method for manufacturing a group III nitride compound semiconductor device includes irradiating a surface of a wafer with ultraviolet rays to thereby clean a resist residue from the surface of the wafer, the surface including a group III nitride compound semiconductor. The ultraviolet rays cause a reaction of oxygen molecules to form stimulated oxygen atoms having a strong oxidative power at the surface.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: August 29, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Naoki Nakajo
  • Patent number: 7037848
    Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Daryl C. New
  • Patent number: 7025896
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: April 11, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Patent number: 6939472
    Abstract: The present invention teaches a method and apparatus for removing sacrificial materials in fabrications of microstructures using one or more selected spontaneous vapor phase etchants. The selected etchant is fed into an etch chamber containing the microstructure during each feeding cycle of a sequence of feeding cycles until the sacrificial material of the microstructure is exhausted through the chemical reaction between the etchant and the sacrificial material. Specifically, during a first feeding cycle, a first amount of selected spontaneous vapor phase etchant is fed into the etch chamber. At a second feeding cycle, a second amount of the etchant is fed into the etch chamber. The first amount and the second amount of the selected etchant may or may not be the same. The time duration of the feeding cycles are individually adjustable.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 6, 2005
    Assignee: Reflectivity, Inc.
    Inventors: Gregory P. Schaadt, Hongqin Shi
  • Patent number: 6906895
    Abstract: A method of marking a sintered body includes the step of preparing the sintered body by sintering a mixture of first and second types of powder particles. The first type of powder particles is made of a first material and the second type of powder particles is made of a second material that has a different etch susceptibility from the first material. The method further includes the step of writing ID information on the surface of the sintered body by forming a first concave region to a depth of at least about 10 nm under the surface of the sintered body and a second concave region under the first concave region, respectively. The first concave region is formed by etching away both the first and second types of powder particles, while the second concave region is formed by etching away only the first type of powder particles.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: June 14, 2005
    Assignee: Neomax Co., Ltd.
    Inventor: Taisuke Hirooka
  • Patent number: 6838012
    Abstract: Methods of etching dielectric materials in a semiconductor processing apparatus use a thick silicon upper electrode that can be operated at high power levels for an extended service life.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 4, 2005
    Assignee: Lam Research Corporation
    Inventor: Eric H. Lenz
  • Patent number: 6835317
    Abstract: A slider prevent the phenomenon of sticking and reduce entrapping of foreign particles between sliding surfaces. A method for making micro-protrusions or micro-cavities on a surface of a substrate comprises placing the substrate in a process chamber, supporting a mask member having a micro shielding surface independent of and in front of the substrate, and irradiating fast atomic beams onto the surface of the substrate through the mask member.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: December 28, 2004
    Assignees: Ebara Corporation
    Inventors: Yotaro Hatamura, Masayuki Nakao
  • Patent number: 6824699
    Abstract: This invention relates to a method of heating an insulating layer, such as is found in semiconductor devices, in which a formation has been etched through a layer of resist comprising reactive etching the resist, inhibiting absorption of or removing water vapour and/or oxygen at the exposed surfaces of the etched formation and filling the formation with conductive metal in the absence of said water vapour and/or oxygen.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: November 30, 2004
    Assignee: Trikon Holdings Ltd.
    Inventor: Christopher David Dobson
  • Patent number: 6806035
    Abstract: A serialization process presents an efficient method of creating serial numbers on a ceramic-like semiconductor wafer by forming a non-rigid photomask that incorporates character specifications for the serial numbers. The non-rigid photomask is retained in a rigid, optically transparent photomask holder that enables the photomask to be handled as a rigid structure. Upon preparation of the wafer, the serial numbers are created onto wafer dies using a combined process involving photolithography, and a reactive ion etching process with a selective etch rate. The serialization process enables a rapid creation of serial numbers, with the selective RIE process substantially increasing the optical contrast of the characters without the need for deep trenches and without generation of excessive debris.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: October 19, 2004
    Assignee: Western Digital (Fremont), Inc.
    Inventors: Thanawatana Atireklapvarodom, Richard D. Anderson
  • Patent number: 6706334
    Abstract: Disclosed are a processing method and apparatus for removing a native oxide film from the surface of a subject to be treated. In this method and apparatus, gas generated from N2, H2 and NF3 gases is reacted with the surface of the subject to degenerate the native oxide film into a reactive film. If the subject is heated to a given temperature, the reactive film is sublimated and thus the native oxide film is removed. Plasma is generated from the N2 and H2 gases and then activated to form an activated gas species. The NF3 gas is added to the activated gas species to generate an activated gas of these three gases. In the step of forming the reactive film, the subject is cooled to not higher than a predetermined temperature by a cooling means. In the step of sublimating the reactive film, the subject is lifted up to a predetermined heating position.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: March 16, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Yasuo Kobayashi, Kotaro Miyatani, Kaoru Maekawa
  • Patent number: 6685848
    Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing half-tone phase-shift film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a half-tone phase-shift photomask by forming patterns to be transferred to a wafer on a photomask blank for a chromium-containing half-tone phase-shift mask. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: February 3, 2004
    Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaei Sasaki, Noriyuki Harashima, Satoshi Aoyama, Shouichi Sakamoto
  • Patent number: 6679996
    Abstract: In a pattern forming method for selectively forming an oxide layer on a substrate surface, the substrate surface is selectively coated with a coating layer. On the coating layer and an exposed part of the substrate surface, an oxide layer is formed by the use of a predetermined solution. Subsequently, the oxide layer on the coating layer is removed together with the coating layer to selectively leave the oxide layer on the substrate surface. Thus, a pattern is formed. The coating layer is removed in a liquid phase or optically together with the oxide layer on the coating layer. The oxide layer is formed by the use of, as the predetermined solution, an aqueous solution or a hydrofluoric acid solution of a fluoro metal complex compound and/or metal fluoride of at least one element selected from the group consisting of alkaline earth metal, transition metal, gallium, indium, silicon, tin, lead, antimony, and bismuth in the presence of an fluoride ion capturing agent.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: January 20, 2004
    Assignees: Hoya Corporation, Takeshi Yao
    Inventor: Takeshi Yao
  • Patent number: 6674562
    Abstract: Improvements in an interferometric modulator that has a cavity defined by two walls.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: January 6, 2004
    Assignee: Iridigm Display Corporation
    Inventor: Mark W. Miles
  • Patent number: 6666983
    Abstract: The present invention is directed to an article with a patterned appearance provided by a visually observable contrast between one or more genereally transparent thin film coatings deposited over a substrate. At least one of the deposited coatings exhibits a reflected color and/or contrast and visible differing transmitted color and/or contrast or a plurality of coatings together exhibit different reflected colors and/or contrasts. The coatings are selected from the group of: metals depositable by magnetron sputtering vacuum deposition, chemical vapor deposition, pyrolytic coating, or sol-gel techniques, metal oxide coatings, metal nitride coatings, semi-conductor containing coatings, metal oxynitrides and mixtures thereof. The present invention is also directed to a method of making the articles having a visually observable patterned appearance involving masking and applying the coating or applying the coating and removing a portion of the coating to form the pattern.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 23, 2003
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Gary J. Marietti, Mehran Arbab, James J. Finley
  • Patent number: 6623653
    Abstract: A method has been provided for etching adjoining layers of indium tin oxide (ITO) and silicon in a single, continuous dry etching process. A conventional dry etching gas, such as HI, is used to etch ITO using RF or plasma energy. When the silicon layer underlying the ITO layer is reached, oxygen or nitrogen is added to etching gas to improve the selectivity of ITO to silicon. In some aspects of the invention an etch-stop layer is formed in the silicon layer. A specific example of fabricating a bottom gate thin film transistor (TFT) is also provided where adjoining layers of source metal, ITO, and channel silicon are etched in the same dry etch step.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: September 23, 2003
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Gaku Furuta, Apostolos Voutsas
  • Patent number: 6613242
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: September 2, 2003
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Patent number: 6592770
    Abstract: This invention relates to a method of heating an insulating layer, such as is found in semiconductor devices, in which a formation has been etched through a layer of resist comprising reactive etching the resist, inhibiting absorption of or removing water vapor and/or oxygen at the exposed surfaces of the etched formation and filling the formation with conductive metal in the absence of said water vapor and/or oxygen.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: July 15, 2003
    Assignee: Trikon Holdings Limited
    Inventor: Christopher David Dobson
  • Patent number: 6537461
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: March 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Patent number: 6528429
    Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: March 4, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Daryl C. New
  • Patent number: 6511918
    Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: January 28, 2003
    Assignee: Infineon Technologies AG
    Inventors: Stephan Wege, Kerstin Krahl
  • Publication number: 20020190024
    Abstract: Presented is an etching method capable of easily etching an oxide containing an alkaline-earth metal. One method is to etch the oxide by using an etching gas containing a halogen gas except for fluorine, an interhalogen compound consisting of only a halogen element except for fluorine, or a halogen hydride consisting of a halogen element except for fluorine and hydrogen. Particularly chlorides, bromides, and iodides of alkaline-earth metals have relatively high vapor pressures, so a thin film containing an alkaline-earth metal can be etched by using chlorine gas, bromine gas, or iodine gas. When a halogen gas containing fluorine is used, damages to SiO2 portions used in a film formation apparatus are prevented by coating these SiO2 portions with a fluoride of an alkaline-earth metal.
    Type: Application
    Filed: July 18, 2002
    Publication date: December 19, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Eguchi, Katsuya Okumura, Masahiro Kiyotoshi, Katsuhiko Hieda, Soichi Yamazaki
  • Publication number: 20020185466
    Abstract: A method has been provided for etching adjoining layers of indium tin oxide (ITO) and silicon in a single, continuous dry etching process. A conventional dry etching gas, such as H1, is used to etch ITO using RF or plasma energy. When the silicon layer underlying the ITO layer is reached, oxygen or nitrogen is added to etching gas to improve the selectivity of ITO to silicon. In some aspects of the invention an etch-stop layer is formed in the silicon layer. A specific example of fabricating a bottom gate thin film transistor (TFT) is also provided where adjoining layers of source metal, ITO, and channel silicon are etched in the same dry etch step.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 12, 2002
    Inventors: Gaku Furuta, Apostolos Voutsas
  • Publication number: 20020175142
    Abstract: A method of forming a capacitor element is provided. After the barrier layer is formed on the dielectric layer, the lower electrode layer, the ferroelectric layer, and the upper electrode layer are formed on the barrier layer in this order. Thereafter, the etching mask having a pattern for a desired capacitor element is formed on the upper electrode layer. Using the etching mask, the upper electrode layer, the ferroelectric layer, the lower electric layer, and the barrier layer are selectively removed by dry etching. The etching gas containing fluorine (F) as one of its constituent elements is used in the step of selectively removing the barrier layer. The mask layer is etched back by an etching action in the same step, thereby eliminating the mask layer. The aspect ratio of the contact hole that exposes the upper capacitor electrode can be decreased by the thickness of the remaining mask layer. Therefore, a desired capacitor element can be formed by using a process (e.g.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 28, 2002
    Applicant: NEC Corporation
    Inventor: Yukihiko Maejima
  • Patent number: 6436304
    Abstract: A plasma processing method using helicon wave excited plasma which makes it possible to control a degree of dissociation for a process gas by controlling the source power. In the plasma processing method using helicon wave excited plasma, the source power applied to the plasma generator is set lower than a source power corresponding to a discontinuous change of a characteristic line indicating the dependency of electron density or saturated ion current density on source power.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: August 20, 2002
    Assignee: Anelva Corporation
    Inventor: Hiroshi Nogami
  • Patent number: 6428714
    Abstract: An improved process for manufacturing a spin valve structure that has buried leads is disclosed. A key feature is the inclusion in the process of a temporary protective layer over the seed layer on which the spin valve structure will be grown. This protective layer remains in place while the buried leads as well as longitudinal bias means are formed. Processing includes use of photoresist liftoff. The protective layer is removed as a natural byproduct of surface cleanup just prior the formation of the spin valve.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: August 6, 2002
    Assignee: Headway Technologies, Inc.
    Inventors: Chyu-Jiuh Torng, Chen-Jung Chien, Kochan Ju, Jei-Wei Chang
  • Patent number: 6423240
    Abstract: A method of altering the topography of a trailing edge of a slider is disclosed, the slider having a substrate surface, at least one magnetic recording head imbedded in an alumina undercoat, and a vertical axis relative to the substrate surface. The steps include first applying an alumina overcoat to at least the trailing edge, followed by lapping at least the trailing edge of the slider. The slider (or sliders) is then placed on a pallet that rotates, exposing the trailing edge to an ion beam. The ion beam is generated using an etchant gas such as Argon, or a mixture of gases such as Argon and Hydrogen, or Argon and CHF3. The trailing edge (or trailing edges) are then exposed at least once to the ion beam at a predetermined milling angle and predetermined time, the milling angle being the angle made by the ion beam relative to the vertical axis. The milling angle is typically between 0° and 85°.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: July 23, 2002
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Wang, Cherngye Hwang
  • Patent number: 6419845
    Abstract: It is an object to provide a method of etching which enables measurement control of the micro width of a magnetic layer while shortening the time required for the etching procedure. An inorganic insulating film made of alumina which is the same material as the write gap layer is formed on a top pole layer by, for example, sputtering method. A photoresist film (first mask) is formed on the inorganic insulating film by photolithography. Next, an inorganic insulating mask (second mask) is formed by selectively etching the inorganic insulating film by reactive ion etching (RIE) using gas etchant such as CF4 (carbon ride), BCl3(boron trichloride), Cl2 (chlorine), SF6 (sulfur hexafluoride) and so on using the photoresist film as a mask. The top layer is selectively removed by, for example, ion milling with Ar (argon) using the inorganic insulating mask.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: July 16, 2002
    Assignee: TDK Corporation
    Inventor: Yoshitaka Sasaki
  • Publication number: 20020084257
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Application
    Filed: November 5, 2001
    Publication date: July 4, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20020074309
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Application
    Filed: November 5, 2001
    Publication date: June 20, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20020070194
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Application
    Filed: October 23, 2001
    Publication date: June 13, 2002
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Publication number: 20020008078
    Abstract: The slider according to the invention can prevent the phenomenon of sticking and reduce entrapping of foreign particles between the sliding surfaces. The method for making micro-protrusions or micro-cavities on a surface of a substrate comprises the steps of: placing the substrate in a process chamber; supporting a mask member, having a micro shielding surface, independent of and in front of the substrate; and irradiating fast atomic beams onto the surface of the substrate through the mask member.
    Type: Application
    Filed: August 30, 2001
    Publication date: January 24, 2002
    Inventors: Yotaro Hatamura, Masayuki Nakao
  • Patent number: 6340435
    Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: January 22, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
  • Publication number: 20010050265
    Abstract: The invention generally provides an apparatus and a method of removing metal oxides, particularly copper oxides and aluminum oxides, from a substrate surface. Primarily, the invention eliminates sputtering of copper oxide from the bottom of an interconnect feature onto the side walls of an interconnect feature, thereby preventing diffusion of the copper atom through the dielectric material and degradation of the device. The invention also eliminates sputtering of the copper oxides onto the chamber side walls that may eventually flake off and cause defects on the substrate. The method of reducing metal oxides from a substrate surface comprises placing the substrate within a plasma processing chamber, flowing a processing gas comprising hydrogen into the chamber, and maintaining a plasma of the processing gas within the chamber through inductive coupling.
    Type: Application
    Filed: May 21, 1998
    Publication date: December 13, 2001
    Inventors: BARNEY M. COHEN, GILBERT HAUSMANN, VIJAY PARKHE, ZHENG XU
  • Patent number: 6315913
    Abstract: A method for structuring at least one layer to be structured. Initially, a mask is applied to the layer and the layer is structured using the mask. After the structuring step, the mask is then removed, while leaving behind redepositions of the material of the layer. The redepositions of the material of the layer are then removed by sound action.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: November 13, 2001
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Volker Weinrich
  • Publication number: 20010035357
    Abstract: Provided are a method of forming a magnetic layer pattern and a method of manufacturing a thin film magnetic head, which can reduce the number of manufacturing steps and thus reduce the manufacturing time. A precursory nonmagnetic layer and a precursory bottom pole layer are formed in this sequence so as to cover a frame pattern formed on an underlayer (a top shield layer) and having an opening. Then, the precursory nonmagnetic layer and the precursory bottom pole layer are patterned by polishing the overall surface by CMP until at least the frame pattern is exposed, and thus a nonmagnetic layer and a bottom pole are selectively formed. The number of manufacturing steps can be reduced and thus the manufacturing time can be reduced, as compared to the case of forming the nonmagnetic layer and the bottom pole without forming the frame pattern.
    Type: Application
    Filed: April 18, 2001
    Publication date: November 1, 2001
    Applicant: TDK CORPORATION
    Inventor: Yoshitaka Sasaki
  • Patent number: 6296777
    Abstract: A layer is structured by first applying a sacrificial layer on the layer to be structured, forming a mask with an inorganic material on the sacrificial layer, then patterning the sacrificial layer and the layer to be structured through the mask, and, finally, removing the sacrificial layer and the mask.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: October 2, 2001
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Volker Weinrich
  • Patent number: RE39273
    Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresists layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Syun-Ming Jang, Ming-Hsin Huang