Etching Of Substrate Containing Elemental Copper, Or An Alloy Or Compound Thereof Patents (Class 216/78)
  • Patent number: 9797047
    Abstract: A method of removing copper oxide from copper surfaces is disclosed that comprises application of vapor generated by an ultrasonic wave nebulizer. The energized vapor droplets include water and a weak organic acid such as acetic acid, lactic acid, citric acid, uric acid, oxalic acid, or formic acid that have a vapor pressure proximate to that of water. The weak organic acid preferably has a pKa high enough to avoid Cu etching but is sufficiently acidic to remove copper oxide at a rate that is compatible with high throughput manufacturing. In one embodiment, weak acid/water vapor is applied to a substrate in a spin bowl and is followed by a deionized water rinse step in the same spin bowl. Improved wettability results in improved uniformity in subsequently plated copper films. Considerable cost savings is realized as a result of reduced chemical consumption and higher product yields.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 24, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Chao-Peng Chen, Jas Chudasama, Chien-Li Lin, David Wagner
  • Patent number: 9705124
    Abstract: A method of preparing a high capacity nanocomposite cathode of FeF3 in carbon pores may include preparing a nanoporous carbon precursor, employing electrochemistry or solution chemistry deposition to deposit Fe particles in the carbon pores, reacting nano Fe with liquid hydrofluoric acid to form nano FeF3 in carbon, and milling to achieve a desired particle size.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 11, 2017
    Assignee: The Johns Hopkins University
    Inventors: Jeremy D. Walker, Jeffrey P. Maranchi, Edward D. Russell, Jennifer L. Sample, Marcia W. Patchan, Lance M. Baird, Rengaswamy Srinivasan
  • Patent number: 8894870
    Abstract: A system and method for etching a material, including a compound having a formulation of XYZ, wherein X and Y are one or more metals and Z is selected from one or more Group 13-16 elements, such as carbon, nitrogen, boron, silicon, sulfur, selenium, and tellurium, are disclosed. The method includes a first etch process to form one or more first volatile compounds and a metal-depleted layer and a second etch process to remove at least a portion of the metal-depleted layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 25, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jereld Lee Winkler, Eric James Shero, Fred Alokozai
  • Patent number: 8871107
    Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Patent number: 8790529
    Abstract: A gas supply system for supplying a gas into a processing chamber for processing a substrate to be processed includes: a processing gas supply unit; a processing gas supply line; a first and a second branch line; a branch flow control unit; an additional gas supply unit; an additional gas supply line; and a control unit. The control unit performs, before processing the substrate to be processed, a processing gas supply control and an additional gas supply control by using the processing gas supply unit and the additional gas supply unit, respectively, wherein the additional gas supply control includes a control that supplies the additional gas at an initial flow rate greater than a set flow rate and then at the set flow rate after a lapse of a period of time.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shinichiro Hayasaka, Ken Horiuchi, Fumiko Yagi, Takeshi Yokouchi
  • Patent number: 8778197
    Abstract: The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Clean Energy Labs, LLC
    Inventors: William Neil Everett, William Martin Lackowski, Joseph F. Pinkerton
  • Patent number: 8758638
    Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 24, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Weifeng Ye, Victor Nguyen, Mei-Yee Shek, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty
  • Patent number: 8709881
    Abstract: A substrate is provided that has a metallic layer on a substrate surface of a substrate. A film made of a two dimensional (2-D) material, such as graphene, is deposited on a metallic surface of the metallic layer. The metallic layer is dewet and/or removed to provide the film on the substrate surface.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: April 29, 2014
    Assignee: The Regents of the University of California
    Inventors: Yuegang Zhang, Ariel Ismach
  • Patent number: 8679359
    Abstract: The present invention is directed to a method and apparatus for etching various metals that may be used in semiconductor or integrated circuit processing through the use of non-halogen gases such as hydrogen, helium, or combinations of hydrogen and helium with other gases such as argon. In one exemplary embodiment of the present invention, in a reaction chamber, a substrate having a metal interconnect layer deposited thereon is exposed to a plasma formed of non-halogen gas. The plasma generated is maintained for a certain period of time to provide for a desired or expected etching of the metal. In some embodiments, the metal interconnect layer may be copper, gold or silver.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Fangyu Wu, Dennis W. Hess, Galit Levitin
  • Publication number: 20140008327
    Abstract: Provided in one embodiment is a method of forming a movable joint or connection between parts that move with respect to one another, wherein at least one part is at least partially enclosed by at least one second part. The method includes positioning an etchable material over an at least one first part, molding or forming an at least one second part over at least the etchable material, and removing the etchable material.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Inventors: CHRISTOPHER D. PREST, Joseph C. Poole, Matthew S. Scott, Dermot J. Stratton
  • Patent number: 8623230
    Abstract: The present method relates to processes for the removal of a material from a sample by a gas chemical reaction activated by a charged particle beam. The method is a multiple step process wherein in a first step a gas is supplied which, when a chemical reaction between the gas and the material is activated, forms a non-volatile material component such as a metal salt or a metaloxide. In a second consecutive step the reaction product of the first chemical reaction is removed from the sample.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 7, 2014
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Nicole Auth, Petra Spies, Tristan Bret, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 8608974
    Abstract: There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15. Plasma is generated from this processing gas. In the inner space of the processing chamber 15, there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40. As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Eiichi Nishimura
  • Patent number: 8597527
    Abstract: The invention provides a method of forming a concavo-convex pattern by partly removing a magnetic layer and a carbon protective layer in an intermediate product of a magnetic recording medium having at least the magnetic layer and the protective layer formed on a substrate surface, wherein the magnetic layer is partly removed to form the concavo-convex pattern by a dry etching method using a etching gas of a mixture gas of argon and a deposition gas containing one or more types of carbon compounds. Also disclosed is a method of manufacturing a patterned medium type magnetic recording medium employing the method of forming a concavo-convex pattern. As a result a concavo-convex pattern free of after-corrosion and exhibiting good productivity is provided.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: December 3, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsumi Taniguchi
  • Patent number: 8444868
    Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Stephan Grunow, Zhengwen Li, Huilong Zhu
  • Patent number: 8383437
    Abstract: An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 26, 2013
    Assignees: Samsung Display Co., Ltd., Dongwoo Fine-Chem Co., Ltd.
    Inventors: Ji-Young Park, Shin-Il Choi, Jong-Hyun Choung, Sang Gab Kim, Seon-Il Kim, Sang-Tae Kim, Joon-Woo Lee, Young-Chul Park, Young-Jun Jin, Kyong-Min Kang, Suck-Jun Lee, O-Byoung Kwon, In-Ho Yu, Sang-Hoon Jang, Min-Ki Lim, Yu-Jin Lee
  • Patent number: 8137641
    Abstract: A method of making a microfluidic module is disclosed that includes forming a fluid flow channel in a self-bonding rebondable polyimide film to provide a channel sheet, the self-bonding rebondable polyimide film having a first mask layer self-bonded thereto; removing the first mask layer from the channel sheet after forming the fluid flow channel; and self-bonding the surface of the channel sheet exposed by removal of the first mask layer to a cover sheet.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: March 20, 2012
    Assignee: YSI Incorporated
    Inventor: Donald R. Moles
  • Patent number: 8138095
    Abstract: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing gas includes organic acid metal complex or organic acid metal salt.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8124541
    Abstract: An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF3 and at least one oxidizing agent, such as at least one of oxygen, ozone, nitrous oxide, nitric oxide and hydrogen peroxide. The etchant gas provides a method of uniformly removing the late transition metal structure or a portion thereof. Moreover, the etchant gas facilitates removing a late transition metal structure with an increased etch rate and at a decreased etch temperature. A method of removing a late transition metal without removing more reactive materials proximate the late transition metal and exposed to the etchant gas is also disclosed.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8088294
    Abstract: An exemplary method for manufacturing printed circuit boards is provided. In the method, a copper clad substrate having a copper layer thereon is provided. A surface of the copper layer is roughened by applying an atmospheric pressure plasma thereto. A photoresist layer is formed on the roughened surface of the copper layer. The photoresist layer is exposed. The photoresist layer is developed to form a patterned photoresist layer, thereby exposing portions of the copper layer. The exposed portions of the copper layer exposed are removed so that the remaining portions of the copper layer form electrical traces. The patterned photoresist layer is removed.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: January 3, 2012
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Tso-Hung Yeh, Hung-Yi Chang, Chia-Cheng Chen
  • Patent number: 8012879
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 6, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 7955454
    Abstract: The method for forming wiring includes: laminating a thermosetting resin film and a metallic foil on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by using as a mask the metallic foil; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil; forming an electroless-plated layer that covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring; and forming wiring including an electroplated layer on the electroless-plated layer.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: June 7, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Kosaku Harayama, Hiroyuki Kato, Tetsuya Koyama
  • Patent number: 7947188
    Abstract: A method for manufacturing a thin film magnetic head includes a step for forming an MR layered body; a step for forming a first sacrificial layer made of material removable by wet etching, and subsequently, forming a cap layer on the upper surface of the first sacrificial layer; further, a step for patterning the MR layered body and the cap layer and then filling part of the removed areas of the MR layered body and the cap layer with a bias magnetic layer and the remaining with insulating layers; a step for removing the cap layer by dry etching and, subsequently, removing the first sacrificial layer by wet etching; and a step for forming a second shield layer above the MR layered body and the bias magnetic layer.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 24, 2011
    Assignee: TDK Corporation
    Inventors: Toshiyuki Ayukawa, Shinji Hara, Daisuke Miyauchi, Takahiko Machita, Yoshihiro Tsuchiya
  • Patent number: 7897516
    Abstract: Methods for resputtering and plasma etching include an operation of generating an ultra-high density plasma using an ultra-high magnetic field. For example, a plasma density of at least about 1013 electrons/cm3 is achieved by confining a plasma using a magnetic field of at least about 1 Tesla. The ultra-high density plasma is used to create a high flux of low energy ions at the wafer surface. The formed high density low energy plasma can be used to sputter etch a diffusion barrier or a seed layer material in the presence of an exposed low-k dielectric layer. For example, a diffusion barrier material can be etched with a high etch rate to deposition rate (E/D) ratio (e.g., with E/D>2) without substantially damaging an exposed dielectric layer. Resputtering and plasma etching can be performed, for example, in iPVD and in plasma pre-clean tools, equipped with magnets configured for confining a plasma.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald L. Kinder, Anshu A. Pradhan
  • Patent number: 7879533
    Abstract: An etching residue removal method includes a cleaning sequence. Preferably, the cleaning sequence has a first washing processing, first drying processing, stripper processing, rinsing processing, second washing processing and second drying processing. In the first washing processing, an insulation film and metal lines thereon are washed by pure water. In the first drying processing, the insulation film and metal lines are dried in a nitrogen atmosphere at room temperature, for example. In the stripper processing, the etching residue on the insulation film and metal lines are stripped by amine stripper, for example. In the rinsing processing, the insulation film and metal lines are rinsed with an IPA rinse solution, for example. In the second washing processing, the insulation film and metal lines are washed with pure water. In the second drying processing, the insulation film and metal lines are dried in the nitrogen atmosphere at room temperature, for example.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: February 1, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takeshi Itou
  • Publication number: 20090215156
    Abstract: The present invention relates to a method of fabricating a nanogap and a nanogap sensor, and to a nanogap and a nanogap sensor fabricated using the method. The present invention relates to a method of fabricating a nanogap and a nanogap sensor, which can be realized by an anisotropic etching using a semiconductor manufacturing process. According to the method of present invention, the nanogap and nanogap sensor can be simply and cheaply produced in large quantities.
    Type: Application
    Filed: September 5, 2006
    Publication date: August 27, 2009
    Inventors: Bong hyun Chung, Sang kyu Kim, Hye Jung Park
  • Patent number: 7563380
    Abstract: An apparatus and a method comprising same for removing metal oxides from a substrate surface are disclosed herein. In one particular embodiment, the apparatus comprises an electrode assembly that has a housing that is at least partially comprised of an insulating material and having an internal volume and at least one fluid inlet that is in fluid communication with the internal volume; a conductive base connected to the housing comprising a plurality of conductive tips that extend therefrom into a target area and a plurality of perforations that extend therethrough and are in fluid communication with the internal volume to allow for a passage of a gas mixture comprising a reducing gas.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: July 21, 2009
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Chun Christine Dong, Wayne Thomas McDermott, Alexander Schwarz, Gregory Khosrov Arslanian, Richard E. Patrick, Gary A. Orbeck, Donald A. Seccombe, Jr.
  • Patent number: 7553427
    Abstract: A method and apparatus are provided for plasma etching of Cu-containing layers in semiconductor devices using an aluminum source in the presence of a halogen-containing plasma. The aluminum source reacts with halogenated Cu-containing surfaces and forms volatile etch products that allows for anisotropic etching of Cu-containing layers using conventional plasma etching tools.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: June 30, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Audunn Ludviksson, Lee Chen
  • Patent number: 7540969
    Abstract: A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 2, 2009
    Assignee: Subtron Technology Co., Ltd.
    Inventors: Chung W. Ho, Leo Shen
  • Publication number: 20090011604
    Abstract: Preferred embodiments provide a method for removing at least part of a copper comprising layer from a substrate, the substrate comprising at least a copper comprising surface layer. The method comprises in a first reaction chamber converting at least part of the copper comprising surface layer into a copper halide surface layer and in a second reaction chamber removing at least part of the copper halide surface layer by exposing it to a photon comprising ambient, thereby initiating formation of volatile copper halide products. During exposure to the photon comprising ambient, the method furthermore comprises removing the volatile copper halide products from the second reaction chamber to avoid saturation of the volatile copper halide products in the second reaction chamber. The method according to preferred embodiments may be used to pattern copper comprising layers.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 8, 2009
    Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Katholieke Universiteit Leuven, K.U.LEUVEN R&D
    Inventor: Dries Dictus
  • Patent number: 7434719
    Abstract: A method of detecting and calibrating dry fluxing metal surfaces of one or more components to be soldered by electron attachment using a gas mixture of reducing gas comprising hydrogen and deuterium, comprising the steps of: a) providing one or more components to be soldered which are connected to a first electrode as a target assembly; b) providing a second electrode adjacent the target assembly; c) providing a gas mixture comprising a reducing gas comprising hydrogen and deuterium between the first and second electrodes; d) providing a direct current (DC) voltage to the first and second electrodes to form an emission current between the electrodes and donating electrons to the reducing gas to form negatively charged ionic reducing gas and molecules of hydrogen bonded to deuterium; e) contacting the target assembly with the negatively charged ionic reducing gas and reducing oxides on the target assembly. Related apparatus is also disclosed.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: October 14, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Chun Christine Dong, Eugene Joseph Karwacki, Jr., Richard E. Patrick
  • Patent number: 7387738
    Abstract: The present invention relates to a method for removing metal oxides from a substrate surface. In one particular embodiment, the method comprises: providing a substrate, a first, and a second electrode that reside within a target area; passing a gas mixture comprising a reducing gas through the target area; supplying an amount of energy to the first and/or the second electrode to generate electrons within the target area wherein at least a portion of the electrons attach to a portion of the reducing gas and form a negatively charged reducing gas; and contacting the substrate with the negatively charged reducing gas to reduce the metal oxides on the surface of the substrate.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: June 17, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Chun Christine Dong, Wayne Thomas McDermott, Alexander Schwarz, Gregory Khosrov Arslanian, Richard E. Patrick
  • Patent number: 7368393
    Abstract: A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 6, 2008
    Assignee: International Business Machines Corporation
    Inventors: William G. America, Steven H. Johnston, Brian W. Messenger
  • Publication number: 20080087638
    Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition sources that may be used for calibrating a plasma process. The selective-redeposition sources are constructed to promote the redeposition of a controllable and/or measurable amount of material during the plasma process.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 17, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jozef Brcka, Rodney L. Robison, Takashi Horiuchi
  • Patent number: 7297285
    Abstract: A manufacturing process of an emboss type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic surface layer and the organic surface layer is solidified.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: November 20, 2007
    Inventor: Roger Chang
  • Patent number: 7285229
    Abstract: An etchant of the present invention includes an aqueous solution containing hydrochloric acid, nitric acid, and a cupric ion source. An etching method of the present invention includes bringing the etchant into contact with at least one metal selected from nickel, chromium, nickel-chromium alloys, and palladium. Another etching method of the present invention includes bringing a first etchant that includes an aqueous solution containing at least the following components A to C (A. hydrochloric acid; B. at least one compound selected from the following (a) to (c): (a) compounds with 7 or less carbon atoms, containing a sulfur atom(s) and at least one group selected from an amino group, an imino group, a carboxyl group, a carbonyl group, and a hydroxyl group; (b) thiazole; and (c) thiazole compounds; and C.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: October 23, 2007
    Assignee: MEC Company, Ltd.
    Inventors: Masayo Kuriyama, Ryo Ogushi, Daisaku Akiyama, Kaoru Urushibata
  • Patent number: 7214327
    Abstract: A method and apparatus for dry etching pure Cu and Cu-containing layers (220, 310) for manufacturing integrated circuits. The invention uses a directional beam of O-atoms with high kinetic energy (340) to oxidize the Cu and Cu-containing layers, and etching reagents (370) that react with the oxidized Cu (360) to form volatile Cu-containing etch products (390). The invention allows for low-temperature, anisotropic etching of pure Cu and Cu-containing layers in accordance with a patterned hard mask or photoresist (230, 330).
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Lee Chen, Audunn Ludviksson
  • Patent number: 7148073
    Abstract: Methods and systems for preparing a substrate for analysis are provided. One method includes removing a portion of a copper structure on the substrate using an etch chemistry in combination with an electron beam. The etch chemistry is substantially inert with respect to the copper structure except in the presence of the electron beam. Other methods involve forming masking layers on a substrate that will protect the substrate during etching. For example, one method includes exposing a first portion of the substrate to an electron beam. A second portion of the substrate not exposed to the electron beam includes a copper structure. The method also includes exposing the substrate to a fluorine containing chemical. The fluorine containing chemical bonds to the first portion but not the second portion to form a fluorine containing layer on the first portion.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: December 12, 2006
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: David Soltz, Mehran Nasser-Ghodsi, Harold Winters, John W. Coburn, Alexander Gubbens, Gabor Toth
  • Patent number: 7086141
    Abstract: A manufacturing method of an MR sensor including a step of stacking an anti-ferromagnetic layer made of an electrically conductive anti-ferromagnetic material, a step of stacking a pinned layer on the anti-ferromagnetic layer, a step of stacking a nonmagnetic spacer layer on the pinned layer, a step of exposing at least once a surface of the nonmagnetic spacer layer to an oxygen-contained atmosphere, a step of stacking a free layer on the nonmagnetic spacer layer, a magnetization direction of the free layer being free depending upon a magnetic filed applied thereto, and a step of providing the pinned layer a magnetization direction fixed by an exchange coupling between the anti-ferromagnetic layer and the pinned layer.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 8, 2006
    Assignee: TDK Corporation
    Inventors: Yoshihiro Tsuchiya, Tetsuro Sasaki
  • Patent number: 7064076
    Abstract: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the subject matter include, but are not necessarily limited to, Cl, Br, F, and I. Once the CuX, or CuX and CuX2, are formed the subject invention can then involve passing a reducing gas over the area of Cu for a sufficient time to etch away at least a portion of the CuX, or CuX2, respectively. With respect to a specific embodiment in which CuX and CuX2 are produced when the halide gas is passed over the area of Cu, the reducing gas can be passed until essentially all of the CuX2 is etched and at least a portion of the CuX is etched. Examples of reducing gases which can be utilized with the subject invention include, but are not necessarily limited to, hydrogen gas and hydrogen gas plasma.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 20, 2006
    Inventor: Nagraj Kulkarni
  • Patent number: 7063091
    Abstract: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Koschinsky, Volker Kahlert, Peter Huebler
  • Patent number: 6987067
    Abstract: A method of repairing a semiconductor chip containing copper is taught, whereby copper is selectively removed from the chip. The method involves processing the chip inside a chamber in which the chip is exposed to various gases and an energy source, such as a focused ion beam. To the extent the chip may have non-copper materials, such as nitride and oxide layers, on top of the copper that is to be removed, those non-copper materials will first be selectively removed. Such removal typically results in a hole (a so-called “elevator shaft”) leading to the copper that is to be removed. Next, the method teaches the introduction of a combination of nitrogen and oxygen into the chamber and the directing of the ion beam at the spot where the copper is to be removed. In this manner, the copper on the chip is cleanly and reliably removed, without causing damage to the processing chamber.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Fischer, Steven B. Herschbein
  • Patent number: 6960306
    Abstract: In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising: a) depositing on a first underlayer, a blanket of an aluminum compound containing an electrical short reducing amount of an alloy metal in electrical contact with the underlayer; b) depositing a photoresist and exposing and developing to leave patterns of photoresist on the blanket aluminum compound containing an electrical short reducing amount of an alloy metal; and c) reactive ion etching to obtain an aluminum compound containing an alloy metal line characterized by reduced shorts in amounts less than the aluminum compound without said short reducing amount of alloy metal.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 1, 2005
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Roy C. Iggulden, Padraic Shafer, Kwong Hon (Keith) Wong, Michael M. Iwatake, Jay W. Strane, Thomas Goebel, Donna D. Miura, Chet Dziobkowski, Werner Robl, Brian Hughes
  • Patent number: 6949202
    Abstract: Processes for the addition or removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the use of recirculation of the process gas. Recirculation is effected by a pump that has no sliding or abrading parts that contact the process gas, nor any wet (such as oil) seals or purge gas in the pump. Improved processing can be achieved by a process chamber that contains a baffle, a perforated plate, or both, appropriately situated in the chamber to deflect the incoming process gas and distribute it over the workpiece surface. In certain embodiments, a diluent gas is added to the recirculation loop and continuously circulated therein, followed by the bleeding of the process gas (such as an etchant gas) into the recirculation loop. Also, cooling of the process gas, etching chamber and/or sample platen can aid the etching process. The method is particularly useful for adding to or removing material from a sample of microscopic dimensions.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: September 27, 2005
    Assignee: Reflectivity, INC
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Niles K. MacDonald
  • Patent number: 6939796
    Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: September 6, 2005
    Assignee: Lam Research Corporation
    Inventors: Shrikant P. Lohokare, Andrew D. Bailey, III, David Hemker, Joel M. Cook
  • Patent number: 6843899
    Abstract: Chemical sensors include a flexible substrate, a flexible lower electrode on the flexible substrate, and a patterned flexible dielectric layer on the flexible lower electrode opposite the flexible substrate. A patterned flexible upper electrode also is included on the patterned flexible dielectric layer opposite the flexible lower electrode. The patterned flexible dielectric layer and the patterned flexible upper electrode are patterned to establish a first current flow path between the flexible lower electrode and the patterned flexible upper electrode through the chemical, if present, upon application of voltage between the flexible lower electrode and the patterned flexible upper electrode. The flexible lower electrode also may be patterned to establish a second current flow path between portions of the patterned flexible lower electrode through the chemical, if present, upon application of voltage between the portions of the patterned flexible lower electrodes.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: January 18, 2005
    Assignee: North Carolina State University
    Inventor: Stefan Ufer
  • Patent number: 6840249
    Abstract: In order to clean a semiconductor device having a dielectric layer deposited on a top surface of a lower metal wiring of the semiconductor device, and a contact hole or a via hole formed in the dielectric layer to expose the lower metal line therethrough, the semiconductor device is located within a radio frequency (RF) cleaning chamber. A gas mixture of HCl and H2O is introduced into the RF cleaning chamber and Ar gas plasma is generated in the RF cleaning chamber to excite HCl gas so that the HCl gas and an excited HCl gas are used to remove carbon radicals and metal particles.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo Min Seo
  • Patent number: 6824655
    Abstract: A micro-machining process that includes etching a substrate having copper overlying a dielectric layer to a charged particle beam in the presence of an etch assisting agent. The etch assisting agent is selected from the group consisting of ammonia, acetic acid, thiolacetic acid, and combinations thereof.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: November 30, 2004
    Assignee: Credence Systems Corporation
    Inventors: Vladimir V. Makarov, Javier Fernandez Ruiz, Tzong-Tsong Miau
  • Patent number: 6782897
    Abstract: A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: August 31, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yu Wang, Chender Huang, Pei-Haw Tsao, Ken Chen, Hank Huang
  • Patent number: 6780342
    Abstract: A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 Mz is applied to a lower electrode 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: August 24, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Masaaki Hagihara, Koichiro Inazawa, Wakako Naito