Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: An insulating sheet for use in forming an insulating layer of an interconnect substrate includes a semi-cured insulating resin layer, a semi-cured protective resin layer laminated on an upper surface of the insulating resin layer, and a cover layer laminated on an upper surface of the protective resin layer, wherein the protective resin layer has lower resistance to a predetermined solution than the insulating resin layer has, the predetermined solution being capable of dissolving the insulating resin layer and/or the protective resin layer.

Abstract: A method for introducing at least one cutout, in particular in the form of an aperture, into a sheetlike workpiece having a thickness of less than 3 mm, involving detecting a laser beam onto the surface of the workpiece, selecting the exposure time of the laser beam to be extremely short so that only a modification of the workpiece concentrically around a beam axis of the laser beam occurs, such a modified region having defects resulting in a chain of blisters, and, as a result of the action of a corrosive medium, anisotropically removing material by successive etching in those regions of the workpiece that are formed by the defects and have previously been modified by the laser beam, resulting, along the cylindrical zone of action, in producing a cutout as an aperture in the workpiece.

Abstract: A method for preparation of conductive polymer/carbon nanotube (CNT) composite nanofiltration (NF) membrane and the use thereof. This conductive polymer/CNT composite NF membrane is obtained by polymerizing conductive polymer into a CNT membrane and then in-situ cross-linking with glutaraldehyde under acidic condition. The synthetic method for the conductive polymer/CNT composite NF membrane is simple and has no need of expensive equipment. The prepared membrane has controllable membrane structure and possesses superior electrical conductivity and electrochemical stability. The membrane can couple with electrochemistry for electrically assisted filtration. With the electrical assistance, the membrane can achieve improved ion rejection performance while retaining high permeability by enhancement of membrane surface charge density, which alleviates the permeability-selectivity trade-off.

Abstract: A method of manufacturing a structure, the method comprising: obtaining a flowable liquid comprising a homogenous mixture of an active material and a binding material; generating a plurality of droplets from the flowable liquid; and depositing the plurality of generated droplets on a support, wherein the plurality of droplets self-assemble to form a continuous structure, wherein the continuous structure comprises a plurality of microstructure units, and wherein the active material and the binding material self-segregate to form a non-uniform distribution of the active material and the binding material in each of the units.

Abstract: A process of making a microneedle array comprising providing a microneedle array having a plurality of microneedles of a desired shape, illuminating at least a portion of said microneedle array that comprises at least one microneedle, capturing an observed image of said at least one microneedle using an optical device, electronically processing said observed image and determining at least one shape parameter for said at least one microneedle, accepting said microneedle array if said at least one shape parameter is within an acceptable range, thereby providing a microneedle array that comprises a known shape of the plurality of microneedles.

Abstract: A method for producing a porous member, whereby a member having smaller microgaps can be produced, and additionally, the outermost surface alone can be made porous and a porous layer can be formed on the surface while maintaining the characteristics of portions in which no porous layer is formed, is provided.

Abstract: The present invention provides a method to fabricate an optical coupler comprising the steps of: preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide; masking a halftone design with variation in optical density to delineate an optical element in the glass; exposing the photosensitive glass substrate to an activating energy source; exposing the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature; cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass-crystalline substrate; and etching the glass-crystalline substrate with an etchant solution to form the one or more optical elements.

Abstract: A semiconductor manufacturing process is provided. A trench is formed in a semiconductor structure and an oxide layer is deposited on sidewalls of the trench. A solid-state by-product layer is formed on surfaces of the trench by introducing a first etchant gas to react with a naturally occurred oxide layer at the bottom of the trench and the deposited oxide layer. The solid-state by-product layer has a thickness on the bottom less than a thickness on the sidewalls. A second etchant gas is introduced into the trench to react with the solid-state by-product layer, thereby providing a thinned solid-state by-product layer on the sidewalls to protect the deposited oxide layer. By a heating process, the thinned solid-state by-product layer is removed from the sidewalls of the trench, exposing the deposited oxide layer and a surface portion of the semiconductor structure in the trench.

Abstract: Silica-containing substrates including vias with a narrow waist, electronic devices incorporating a silica-containing substrate, and methods of forming vias with narrow waist in silica-containing substrates are disclosed. In one embodiment, an article includes a silica-containing substrate including greater than or equal to 85 mol % silica, a first surface, a second surface opposite the first surface, and a via extending through the silica-containing substrate from the first surface toward the second surface. The via includes a first diameter at the first surface wherein the first diameter is less than or equal to 100 ?m, a second diameter at the second surface wherein the first diameter is less than or equal to 100 ?m, and a via waist between the first surface and the second surface. The via waist has a waist diameter that is less than the first diameter and the second diameter such that a ratio between the waist diameter and each of the first diameter and the second diameter is less than or equal to 75%.

Abstract: The instant disclosure provides a self-adsorbed catalyst composition, a method for preparing the self-adsorbed catalyst composition and a method for manufacturing an electroless plating substrate. The self-adsorbed catalyst composition includes colloidal nanoparticles and a silane compound. The colloidal nanoparticles include palladium nanoparticles and capping agents enclosing the palladium nanoparticles. The silane compound has at least an amino group, and an interaction is established between the amino group of the silane compound and the colloidal nanoparticle.

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

Abstract: Provided is a method for forming a hole pattern in a resist film. The method includes forming a resist film on a workpiece; exposing the resist film using a bright field mask; removing an unexposed portion of the resist film by supplying a first developer to the resist film and performing a negative development after the exposing the resist film; modifying a sidewall portion of the resist film after the removing the unexposed portion of the resist film; and removing an exposed portion of the resist film by supplying a second developer to the resist film and performing a positive development after the modifying the sidewall portion of the resist film. The modifying the sidewall portion of the resist film is a processing of reducing solubility of the sidewall portion of the resist film in the second developer.

Abstract: A touchscreen system comprises a touch area. At least one transmitter is positioned proximate to outer edges of the touch area for transmitting first beams in a first direction. At least one beam splitter is positioned proximate to the outer edges of the touch area for splitting the first beams into at least second and third beams that travel through the touch area in at least second and third directions, respectively. The at least one beam splitter comprises a plurality of deflecting elements. Receivers are positioned proximate to the outer edges of the touch area for receiving the at least second and third beams.

Abstract: A window substrate includes a glass substrate including first and second surfaces opposite to each other, the glass substrate having a thickness of about 25 ?m to about 100 ?m, and a coating layer disposed on the first surface. The glass substrate includes SiO2, Al2O3 and Na2O, and the mole ratio of Al2O3/Na2O is equal to or smaller than 1.

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract: Described is a reagent that enhances acid generation of a photoacid generator and a composition containing such reagent.

Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract: An electron definable glass or an electron sensitive glass for microstructures is provided with microstructures and optical waveguides formed therein. The microstructures are formed by electron beam irradiation in selected areas in the electron definable glass followed by a high temperature heat treatment and chemical etching, whereas the optical waveguides are formed by irradiating the electron definable glass by an electron beam followed by a low temperature heat treatment.

Abstract: A method for cutting a substrate includes: radiating, as part of a first laser radiating process, a laser towards a surface of the substrate to form a first groove in a substrate. Radiating the laser towards the surface includes radiating, in sequence, the laser towards a first outer point (FOP), a second outer point (SOP), a first intermediate point (FIP), a second intermediate point (SIP), and a first cut point (FCP) of the surface, each of the points being spaced apart from one another by one or more distances. The FCP corresponds to a cut line of the substrate. The FOP and the SOP are respectively disposed at lateral sides of the FCP. The FIP is disposed between the FCP and the FOP. The SIP is disposed between the FCP and the SOP. The same kind and intensity of laser is radiated towards each of the points.

Abstract: Beam-induced etching uses a work piece maintained at a temperature near the boiling point of a precursor material, but the temperature is sufficiently high to desorb reaction byproducts. In one embodiment, NF3 is used as a precursor gas for electron-beam induced etching of silicon at a temperature below room temperature.

Abstract: In one embodiment a method of method of treating a sidewall layer of a patterned feature includes providing the patterned feature as an etched structure comprising one or more layers disposed on a substrate and generally parallel to a plane of the substrate defined by a front surface of the substrate. The sidewall layer comprises material from the one or more etched layers. The method further includes arranging the substrate proximate a sheath modifier that is adjacent a plasma, and providing ions in an ion dose to the substrate by extracting the ions from the plasma through the sheath modifier, the ions impinging upon the substrate at an angle with respect to a perpendicular to the plane of the substrate.

Abstract: A conductive pattern is formed in a polymeric layer that has (a) a reactive polymer comprising pendant tertiary alkyl ester groups, (b) a compound that provides an acid upon exposure to radiation, and (c) a crosslinking agent. The polymeric layer is patternwise exposed to radiation to provide a polymeric layer comprising non-exposed regions and exposed regions comprising a polymer comprising carboxylic acid groups. The exposed regions are contacted with electroless seed metal ions to form a pattern of electroless seed metal ions. This pattern of electroless seed metal ions can be contacted with a non-reducing reagent that reacts with the electroless seed metal ions to form an electroless seed metal compound that has a pKsp of less than 40. This bound electroless seed metal compound is then electrolessly plated with a suitable conductive metal.

Abstract: A conductive pattern is formed using a reactive polymer comprising pendant tertiary alkyl ester groups, a compound that provides an acid upon exposure to radiation, and a crosslinking agent. A polymeric layer is patternwise exposed to form first exposed regions with a polymer comprising carboxylic acid groups that are contacted with electroless seed metal ions, and then contacted with a halide to form corresponding electroless seed metal halide. Another exposure converts electroless seed metal halide to electroless seed metal nuclei and forms second exposed regions. A reducing agent is used to develop the electroless seed metal nuclei in the second exposed regions, or to develop the electroless seed metal halide in the first exposed regions. Fixing is used to remove any remaining electroless seed metal halide. The electroless seed metal nuclei are then electrolessly plated in various exposed regions.

Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28?) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28?) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).

Abstract: A method for manufacturing a touch screen panel includes reinforcing a glass substrate, the glass substrate to be formed with a plurality of touch screen panels in unit cells, reinforcing the glass substrate including forming a reinforcing layer on an upper and a lower side of the glass substrate by performing a reinforcement treatment on a whole surface of the glass substrate, cutting the reinforced glass substrate in each unit cell, removing a part of the reinforcing layer formed in the upper and the lower side of the glass substrate adjacent to a cut cross section, performing a chemical HF treatment on a cross section of the glass substrate corresponding to the cut cross section and exposing the glass substrate by partially removing the reinforcing layer, and forming a touch screen panel per region of the unit cells, respectively.

Abstract: In a method comprising a modified region forming step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a plurality of modified spots within the object along a modified region forming line tilted in a first lateral direction with respect to a thickness direction of the object and the plurality of modified spots construct a modified region, and an etching step of anisotropically etching the object after the modified region forming step so as to advance the etching selectively along the modified region and form the object with a space extending obliquely with respect to the thickness direction, the modified region forming step forms the plurality of modified spots such that the modified spots adjacent to each other at least partly overlap each other when seen in the first lateral direction.

Abstract: The present invention concerns a method for manufacturing a resonator in a substrate characterized in that it includes the following steps: a) modifying the structure of at least one region of the substrate in order to make said at least one region more selective; b) etching said at least one region in order to selectively manufacture said resonator.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object; a laser light converging step of converging the laser light at the object after the etch resist film producing step so as to form the modified region along a part corresponding to the through hole in the object and converging the laser light at the etch resist film so as to form a defect region along a part corresponding to the through hole in the etch resist film; and an etching step of etching the object after the laser light converging step so as to advance the etching selectively along the modified region and form the through hole.

Abstract: A method for providing a nanopattern of periodically ordered metal oxide nanostructures on a substrate is described. The method comprises the steps of providing a microphase separated block copolymer as a thin film on a substrate, the block copolymer comprising a first polymer having an affinity for a cations of the metal and a second polymer having a lower affinity for the cations than the first polymer, and selectively incorporating a salt of the metal cation into the first polymer of the block copolymer by means of a solvation process prior to or after formation of the microphase separated block copolymer. The block copolymer film is then treated to oxidise the metal ion salt and remove the polymers leaving a nanopattern of metal oxide nanostructures on the substrate.

Abstract: A method for manufacturing a component in a substrate including: a) modifying a structure of at least one region of the substrate to make the at least one region more selective; and b) chemically etching the at least one region to selectively manufacture the component.

Abstract: An implant includes a microstructured hyperhydrophilic surface with protrusions and depressions in which a spacing between the protrusions as a statistical mean is in a range of 1 to 100 ?m and a profile height of the protrusions and depressions as a statistical mean is in the range of 1 to 80 ?m.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: A method of manufacturing a base body having a microscopic hole, includes: forming at least one of a first modified region and a second modified region by scanning inside of a base body with a focal point of a first laser light having a pulse duration on order of picoseconds or less; forming a periodic modified group formed of a plurality of third modified regions and fourth modified regions by scanning an inside of the base body with a focal point of a second laser light having a pulse duration on order of picoseconds or less; obtaining the base body which is formed so that the first modified region and the second modified region overlap or come into contact with the modified group; and forming a microscopic hole by removing the first modified region and the third modified regions by etching.

Abstract: Disclosed is a processing method which can achieve a high processing rate, and is capable of making a surface smooth. In order to achieve this an SiC substrate is arranged in a potassium hydroxide solution containing hydrogen peroxide, and ultraviolent radiation is irradiated on the surface of the SiC substrate. An SiO2 layer is formed on the surface of the SiC substrate due to the irradiation of ultraviolet radiation, and this SiO2 layer is chemically removed by means of the potassium hydroxide solution, and also removed by a synthetic quartz surface plate.

Abstract: A donor wafer, for example of silicon, has an irregular surface following cleaving of a lamina from the surface, for example by exfoliation following implant of hydrogen and/or helium ions to define a cleave plane. Pinholes in the lamina leave column asperities at the exfoliated surface of the donor wafer, and the beveled edge may leave an edge asperity which fails to exfoliate. To prepare the surface of the donor wafer for reuse, mechanical grinding removes the column and edge asperities, and minimal additional thickness. Following cleaning, growth and removal of an oxide layer at the surface rounds remaining peaks. The smoothed surface is well adapted to bonding to a receiver element and exfoliation of a new lamina. A variety of devices may be fabricated from the lamina, for example a photovoltaic cell.

Abstract: The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate.

Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.

Abstract: A silicon substrate processing method includes forming an etching mask which has an opening portion, on a surface of a silicon substrate, forming an etching guide hole in the opening portion on the silicon substrate, and forming a through-hole which passes through the silicon substrate, by applying an etching treatment onto the silicon substrate in which the etching guide hole is formed. In the forming of the guide hole, the etching guide hole passing through the silicon substrate is formed by irradiating the opening portion with a laser beam a plurality of times, with a cooling period between each instance of irradiation with the laser beam.

Abstract: Disclosed is a method of etching semiconductor nanocrystals, which includes dissolving semiconductor nanocrystals in a halogenated solvent containing phosphine so that anisotropic etching of the surface of semiconductor nanocrystals is induced or adding a primary amine to a halogenated solvent containing phosphine and photoexciting semiconductor nanocrystals thus inducing isotropic etching of the surface of the nanocrystals, thereby reproducibly controlling properties of semiconductor nanocrystals including absorption wavelength, emission wavelength, emission intensity, average size, size distribution, shape, and surface state.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line.

Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.

Abstract: Provided are methods of manufacturing a surface light source device, the methods include forming a first structure that includes a first substrate and a plurality of glass beads each partially embedded in the first substrate. A second structure is formed that includes a second substrate and an adhesive material layer formed on the second substrate. The first structure and the second structure are adhered to each other in such a way that the glass beads are each partially embedded into the adhesive material layer.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises a laser light converging step of converging the laser light at the object so as to form the modified region along a part corresponding to the through hole in the object; an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object after the laser light converging step; and an etching step of etching the object so as to advance the etching selectively along the modified region and form the through hole after the etch resist film producing step; while the laser light converging step exposes the modified region to the outer surface of the object.

Abstract: The invention relates to a method and device for characterizing wafers during the production of solar cells. Characterizing wafers includes a) providing a wafer and carrying out a production process with the wafer for producing a solar cell or a plurality of solar cells; b) carrying out a wet chemical step with the wafer during the production process, wherein the wet chemical step decreases an influence of the wafer surface on a lifetime of charge carriers in the wafer; c) irradiating the wafer with light for creating the charge carriers in the wafer during the wet chemical step or after the wet chemical step; d) determining the lifetime of the charge carriers created in step c); and e) characterizing the wafer by means of the lifetime determined in step d).