Irradiating, Ion Implanting, Alloying, Diffusing, Or Chemically Reacting The Substrate Prior To Ethching To Change Properties Of Substrate Toward The Etchant Patents (Class 216/87)
  • Patent number: 6225232
    Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: May 1, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Whonchee Lee
  • Patent number: 6197697
    Abstract: A method of patterning a brittle material, and particularly a semiconductor material, is provided comprising ion implantation induced selective area exfoliation. The method includes steps of masking the material, implanting unmasked regions of the material, with light ions of Hydrogen or Helium, and rapid thermal annealing at the temperature causing exfoliation of the material from the implanted regions. As a result, the material is patterned to a depth determined by the depth of ion implantation. The method allows patterning through crystalline or non-crystalline materials, or several layers of different materials at the same time. When the mask has straight sharp edges aligned parallel to natural cleavage planes of the semiconductor material, the exfoliation results in formation of high quality sidewall-facets of exfoliated material and of the remaining patterned material at the boundaries of exfoliated regions.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: March 6, 2001
    Assignee: Nortel Networks Limited
    Inventors: Todd William Simpson, Ian Vaughan Mitchell, Grantley Oliver Este, Frank Reginald Shepherd
  • Patent number: 6193898
    Abstract: A plurality of reflectors respectively having the same rough reflecting surfaces are formed substantially simultaneously on a transparent substrate of a large area. A photosensitive resin film is formed on a surface of a transparent substrate. An embossing die having a rough working surface is pressed against a photosensitive resin part of the photosensitive resin film and the photosensitive resin part is irradiated with ultraviolet rays from below the transparent substrate to form a prehardened photosensitive resin part. Those steps are repeated to form a plurality of prehardened, embossed photosensitive resin parts on the transparent substrate, and then parts not prehardened of the photosensitive resin film are removed by etching. The prehardened, embossed photosensitive resin parts are heated for hardening, and a metal reflecting film is formed on the hardened embossed photosensitive resin parts to complete a plurality of reflectors.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: February 27, 2001
    Assignee: Alps Electric Co., Ltd.
    Inventors: Mitsuru Kano, Tomomasa Takatsuka, Kenji Omote
  • Patent number: 6189546
    Abstract: A multi-step polishing process for producing dopant-striation-free semiconductor wafers. The process includes polishing a surface of the wafer using a sodium stabilized colloidal silica slurry, an amine accelerant, and an alkaline etchant, polishing the surface of the wafer using a sodium stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants, and polishing the surface of the wafer using an ammonia stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: February 20, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: David Zhang, Sharon Brumer, Henry F. Erk
  • Patent number: 6171512
    Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 9, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
  • Patent number: 6149988
    Abstract: A method for treating an object with a laser including emitting a laser beam from a laser; expanding the laser beam in a first direction; removing a portion of the laser beam though a mask, the portion including at least edges of the expanded laser beam extending in the first direction; and condensing the laser beam in a second direction orthogonal to the first direction in order to form a line-shaped laser beam on an object.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: November 21, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisato Shinohara, Akira Sugawara
  • Patent number: 6140245
    Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: October 31, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Whonchee Lee
  • Patent number: 6133158
    Abstract: The present invention provides a method for removing contaminant metals from a solvent used in the manufacture of a semiconductor wafer. The method may comprise the steps of bringing a solvent having contaminant metals therein into contact with a sacrificial body having titanium oxide associated therewith and cleaning the semiconductor wafer with the solvent. The titanium oxide reacts with the contaminant metals to substantially remove them from the solvent to provide a substantially cleaner solvent for the production of metal oxide semiconductor (MOS)devices. The present invention is particularly applicable in "back-end" processes of such devices.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: October 17, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yaw S. Obeng, Robert L. Opila, Ramaswamy S. Raghavan
  • Patent number: 6120875
    Abstract: The subject of the present invention is a solid material in the form of a microperforated sheet transparent to light of wavelengths in the visible and infrared, characterized in that the mean distance between two immediately neighbouring perforations is at least 5, and preferably 7 .mu.m, and is so over each face of the material. Preferably, the mean angle of inclination of the perforations through the thickness of the material is less than 10.degree., even 5.degree.. In a particular embodiment, the material is a membrane produced from a flexible polymer film with a thickness lying between 0.1 and 100 .mu.m, more generally between 5 and 50 .mu.m, and the perforation diameters lying between 0.01 and 15 .mu.m. The membranes obtained according to the invention are particularly useful as support membranes for viewing in an optical microscope or in infrared spectroscopy. They may also be used as filter membranes or, amongst other applications, as a support for cell culture.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 19, 2000
    Assignee: Cyclopore S.A.
    Inventors: Charles Haumont, Roger Legras
  • Patent number: 6120597
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 19, 2000
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr.
  • Patent number: 6096175
    Abstract: A method for fabricating a stent or other medical device by creating a free standing thin film of metal.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: August 1, 2000
    Assignee: Micro Therapeutics, Inc.
    Inventor: Noah M. Roth
  • Patent number: 6045710
    Abstract: A manufacturing process for printing heads which operate using the coincident forces drop on demand printing principles. The print head integrates many nozzles into a single monolithic silicon structure. Semiconductor processing methods such as photolithography and chemical etching are used to simultaneously fabricate a multitude of nozzles into the monolithic head. The nozzles are etched through the silicon substrate, allowing two dimensional arrays of nozzles for color printing. The manufacturing process can be based on existing CMOS, nMOS and bipolar semiconductor manufacturing processes, allowing fabrication in existing semiconductor fabrication facilities. Drive transistors, shift registers, and fault tolerance circuitry can be fabricated on the same wafer as the nozzles. The manufacturing process uses anisotropic wet etching using KOH on a (110) wafer to form ink channels with vertical side-walls. Nozzle barrels are formed using the same etching process, using boron as an etch stop.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: April 4, 2000
    Inventor: Kia Silverbrook
  • Patent number: 6037270
    Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mokuji Kageyama, Moriya Miyashita
  • Patent number: 6033583
    Abstract: A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: March 7, 2000
    Assignee: The Regents of the University of California
    Inventors: Ronald G. Musket, John D. Porter, James M. Yoshiyama, Robert J. Contolini
  • Patent number: 6030556
    Abstract: Optical disc stampers, methods of manufacturing the optical disc stampers, systems for manufacturing the optical disc stampers, and methods of replicating optical discs using the stampers are disclosed. The optical disc stamper is formed directly on a substrate that supports a patterning material including at least one layer of a first material and at least one layer of a second material. The first and second materials can include a metal and semiconductor. The patterning material is exposed to energy in selected areas. Unexposed areas of the patterning material are then removed, resulting in an optical disc stamper. The first and second materials can form an amorphous alloy in the exposed selected areas that remains after removal of the unexposed patterning material. The optical disc stamper can be used in the replication of optical data storage discs. Also disclosed arc systems for practicing the methods to produce optical data storage disc stampers.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: February 29, 2000
    Assignee: Imation Corp.
    Inventors: James M. DePuydt, Walter R. Eppler, Michael B. Hintz
  • Patent number: 5989445
    Abstract: Microchannels for conducting and expelling a fluid are embedded in a surface of a silicon substrate. A channel seal is made of plural cross structures formed integrally with the silicon substrate. The cross structures are arranged sequentially over each channel, each cross structure having a chevron shape. The microchannel is sealed by oxidizing at least partially the cross structures, whereby the spaces therebetween are filled. A dielectric seal which overlies the thermally oxidized cross structures forms a complete seal and a substantially planar top surface to the silicon substrate. The dielectric seal is formed of a low pressure chemical vapor deposition (LPCVD) dielectric layer. The channel is useful in the production of an ink jet print in head, and has a polysilicon heater overlying the dielectric seal. A current passing through the heater causes a corresponding increase in the temperature of the ink in the microchannel, causing same to be expelled therefreom.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: November 23, 1999
    Assignee: The Regents of the University of Michigan
    Inventors: Kensall D. Wise, Jingkuang Chen
  • Patent number: 5968336
    Abstract: A method, apparatus and system for fabricating a stencil mask for ion beam and electron beam lithography are provided. The stencil mask includes a silicon substrate, a membrane formed from the substrate, and a mask pattern formed by through openings in the membrane. The method includes defining the mask pattern and membrane area using semiconductor fabrication processes, and then forming the membrane by back side etching the substrate. The apparatus is configured to electrochemically wet etch the substrate, and to equalize pressure on either side of the substrate during the etch process. The system includes an ion implanter for defining a membrane area on the substrate, optical or e-beam pattern generators for patterning various masks on the substrate, a reactive ion etcher for etching the mask pattern in the substrate, and the apparatus for etching the back side of the substrate.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: October 19, 1999
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 5910235
    Abstract: A stationary vacuum deposition machine is used in a method for controlling the height of bumps formed in annular regions of substrates; the substrates are transported to the machine in a first condition in which each substrate is subject to a chemicapillary effect when subjected to localized thermal heating and melting. The machine includes a series of stations including an entrance station for receiving substrates into the machine, first and second predetermined stations, and a transport for operating in a cycle with each cycle including a transport phase and a stationary phase such that the transport causes all the substrates that are in the machine to be moved during the transport phase, and be temporarily held stationary during the stationary phase, such that during each stationary phase a predetermined one of the stations is occupied by one of the substrates while each of a plurality of others of the stations is occupied by a respective one of a plurality of others of the substrates.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: June 8, 1999
    Assignee: Western Digital Corporation
    Inventors: Stella Zofia Gornicki, Douglas J. Krajnovich
  • Patent number: 5900160
    Abstract: Improved methods of forming a patterned self-assembled monolayer on a surface and derivative articles are provided. According to one method, an elastomeric stamp is deformed during and/or prior to using the stamp to print a self-assembled molecular monolayer on a surface. According to another method, during monolayer printing the surface is contacted with a liquid that is immiscible with the molecular monolayer-forming species to effect controlled reactive spreading of the monolayer on the surface. Methods of printing self-assembled molecular monolayers on nonplanar surfaces and derivative articles are provided, as are methods of etching surfaces patterned with self-assembled monolayers, including methods of etching silicon. Optical elements including flexible diffraction gratings, mirrors, and lenses are provided, as are methods for forming optical devices and other articles using lithographic molding.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: May 4, 1999
    Assignee: President and fellows of Harvard College
    Inventors: George M. Whitesides, Younan Xia, James L. Wilbur, Rebecca J. Jackman, Enoch Kim, Mara G. Prentiss, Milan Mrksich, Amit Kumar, Christopher B. Gorman, Hans Biebuyck, Karl K. Berggren
  • Patent number: 5879424
    Abstract: An optical micro-machining method of glass characterized in that after light is applied to glass including SiO.sub.2 and 30-70 mol % GeO.sub.2, the irradiated area is removed by etching.
    Type: Grant
    Filed: May 16, 1997
    Date of Patent: March 9, 1999
    Assignee: Agency of Industrial Science & Technology
    Inventors: Junji Nishii, Hiroshi Yamanaka
  • Patent number: 5868947
    Abstract: A processed Si product suitable for use as, for example, an X-ray mask, is produced by a process having the steps of preparing a non-porous Si substrate, changing by anodization at least a portion of the substrate into porous Si thereby forming at least one porous Si region penetrating the substrate from one to the other side thereof, and effecting an etching on the substrate by using an etchant containing hydrofluoric acid so as to remove the porous Si region. The substrate may be provided with an etching stop layer. In such a case, an unsupported membrane region formed by the etching stop layer is left after the removal of the porous Si region.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: February 9, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara
  • Patent number: 5869399
    Abstract: The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: February 9, 1999
    Assignee: Mosel Vitelic Inc.
    Inventors: Tuby Tu, Kuang-Chao Chen
  • Patent number: 5863232
    Abstract: A method for making a micro tip of an FED device includes the steps converting impurity layer regions into porous semiconductor layer regions by performing an anodic reaction using an HF aqueous solution as an electrolytic solution, oxidizing the porous silicon layer regions, and removing the oxidation layer by etching with HF aqueous solution. The shape of the fabricated micro tip is regular and precise, since the size and height of the micro tip are easily controlled. Hence, the size and direction of an electron beam emitted from the micro tip is regular, and a reliability of the FED device is enhanced.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: January 26, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Seok Soo Lee
  • Patent number: 5855801
    Abstract: A method of fabricating a microstructure is disclosed. The method includes providing a substrate for forming an interface region and an elongated portion extending away from the interface region. A patterned, non-planar etchable structure is formed on one side of the elongated portion of the substrate. An unetchable membrane layer is deposited atop the etchable structure. At least one etching hole is formed in the membrane layer. The etchable structure is etched by placing an etchant into the etching hole to form a cavity underneath the membrane layer, thereby producing a shaft.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: January 5, 1999
    Inventors: Liwei Lin, Albert P. Pisano
  • Patent number: 5849635
    Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: December 15, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Tyler A. Lowrey
  • Patent number: 5792377
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5767020
    Abstract: A method for preparing a semiconductor member comprises:forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer;bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; andetching to remove the porous silicon layer by immersing in an etching solution.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
  • Patent number: 5746930
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5743998
    Abstract: A process is provided for altering the susceptibility of a portion of a Spin-On Glass layer to etching. The process includes taking a substrate including a layer of positive or negative resist Spin-On Glass and exposing a portion of the Spin-On Glass layer to an electric field or an electron beam. Depending on the particular Spin-On Glass used, exposure of a portion of the Spin-On Glass layer to the electric field or electron beam causes the exposed portion to have either significantly enhanced or reduced susceptibility to etching as compared to the unexposed portion. This enables the exposed and unexposed portions to be differentiated by selectively removing the more etch susceptible portions of the Spin-On Glass layer during development.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: April 28, 1998
    Assignee: Park Scientific Instruments
    Inventor: Sun Woo Park
  • Patent number: 5730890
    Abstract: A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: March 24, 1998
    Assignee: Internationl Business Machines Corporation
    Inventors: Harry Randall Bickford, Elizabeth Foster, Martin Goldberg, Voya Rista Markovich, Linda Matthew, Stephen Leo Tisdale, Alfred Viehbeck
  • Patent number: 5725785
    Abstract: A method of manufacturing an accelerometer sensor having a mass portion is disclosed. A P-type silicon area is formed in an upper area of a P-type silicon substrate by means of impurity doping. An N-type silicon layer is formed on the silicon substrate through vapor phase epitaxy. A recess defining the mass portion is formed in the silicon substrate through an etching process. A current is supplied to the silicon substrate in an electrolytic solution, such as HF aq., while the substrate is connected to an anode of a power supply. The P-type silicon area is then converted to a porous silicon area. The porous silicon area is subjected to a wet etching to be hollowed, thus obtaining a mass portion of a desired shape.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: March 10, 1998
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Tatsuya Ishida, Akihiko Watanabe
  • Patent number: 5683595
    Abstract: A particle beam is irradiated locally to a film of an alloy or compound containing atoms of two or more elements, causing atoms of a specific element in the film to selectively recoil to the outside of the film, such that there is formed, inside of the film, a zone in the form of a pattern in which the rate of the atoms of the specific type is smaller than in other portions of the film. In the fine pattern thus formed, the thickness is substantially equal to that of the film, and other sizes are determined according to the particle beam irradiation zone. For example, when a focused ion beam is used as the particle beam, there can be formed a fine pattern on the 10-nm level with precision of the order of nm. This fine pattern can be a quantum wire, a quantum dot or the like. It is therefore possible to produce, with good reproducibility, a device in which a quantum effect has been utilized.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: November 4, 1997
    Assignee: Shimadzu Corporation
    Inventor: Shinji Nagamachi
  • Patent number: 5665250
    Abstract: A surface type acceleration sensor includes a p-type single crystal silicon base plate, a cantilever functioning as a cantilever structure portion, and a plurality of strain gauges. The cantilever is disposed in a recess portion formed on the front face of the p-type single crystal silicon base plate so that the cantilever can be displaced in the upward and downward direction. The cantilever includes an epitaxial growth layer principally made of n-type single crystal silicon. The strain gauge is made of p-type silicon and formed on an upper face of the base end portion of the cantilever.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: September 9, 1997
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Hitoshi Iwata, Makoto Murate
  • Patent number: 5662768
    Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: September 2, 1997
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rostoker
  • Patent number: 5643404
    Abstract: A method of examining surface defects of silicon wafer surfaces, comprising (A) preparing a semiconductor treating solution containing an impurity element labelled with a radioactive isotope; (B) bringing a silicon wafer whose crystal surface is laid bare, into contact with the treating solution to obtain a specimen wafer on which the labelled impurity has been adsorbed; (C) recording in a photostimulable phosphor layer a data of radioactivity intensible distribution present in the surface of the specimen wafer; the pattern being recorded as a latent image; and (D) reading as a visual image the data of radioactivity intensity distribution recorded in the photostimulable phosphor layer, to observe the radioactivity intensity distribution shown on the image, whereby the distribution of the surface defects being detected.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: July 1, 1997
    Assignees: Purex Co., Ltd., Kabushiki Kaisha Toshiba
    Inventors: Hisashi Muraoka, Yuji Fukazawa
  • Patent number: 5637126
    Abstract: A method is disclosed for producing an ink jet print head which both realizes a higher density and prevents a failure in ink jetting and deterioration in the printing quality. A multiplicity of individual ink passages, each having an narrow width and a large depth, are formed in an array by anisotropic etching a photosensitive glass substrate. A diaphragm is attached to the surface of the glass substrate so as to cover the individual ink passages. A common electrode is provided on the diaphragm, and individual piezoelectric elements are fixed to the common electrode at the portions corresponding to the individual ink passages. Individual electrodes are provided on the respective individual piezoelectric elements. A voltage applied to the common electrode and an individual electrode causes a portion of the diaphragm to corresponding to the individual electrode to be bend and deformed. The ink storing capacity of the corresponding individual ink passage is reduced and some of the ink is forced out.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: June 10, 1997
    Assignee: Rohm Co., Ltd.
    Inventors: Yasushi Ema, Hisayoshi Fujimoto, Nobuhisa Ishida, Toshio Amano, Akihiro Shimokata, Shinsaku Takada
  • Patent number: 5535902
    Abstract: A gimballed vibrating wheel gyroscope for detecting rotational rates in inertial space. The gyroscope includes a support oriented in a first plane and a wheel assembly disposed over the support parallel to the first plane. The wheel assembly is adapted for vibrating rotationally at a predetermined frequency in the first plane and is responsive to rotational rates about a coplanar input axis for providing an output torque about a coplanar output axis. The gyroscope also includes a post assembly extending between the support and the wheel assembly for supporting the wheel assembly. The wheel assembly has an inner hub, an outer wheel, and spoke flexures extending between the inner hub and the outer wheel and being stiff along both the input and output axes. A flexure is incorporated in the post assembly between the support and the wheel assembly inner hub and is relatively flexible along the output axis and relatively stiff along the input axis.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: July 16, 1996
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Paul Greiff
  • Patent number: 5509556
    Abstract: A process of forming an aperture in a metallic sheet including the steps of:a) defining at least one feature in a sheet of metallic material;b) laser drilling the at least one feature but not entirely removing it from the metallic sheet, the at least one feature being partially filled by metallic material which has melted and resolidified; and thenc) chemically etching the metallic sheet and the melted and resolidified metallic material wherein the etchant attacks and at least partially dissolves the melted and resolidified metallic material, weakening the bond of the melted and resolidified metallic material to the metallic sheet.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: April 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: James G. Balz, Gregory M. Johnson, Mark J. LaPlante, David C. Long
  • Patent number: 5437729
    Abstract: A method for tailoring or patterning the surface of ceramic articles is provided by implanting ions to predetermined depth into the ceramic material at a selected surface location with the ions being implanted at a fluence and energy adequate to damage the lattice structure of the ceramic material for bi-axially straining near-surface regions of the ceramic material to the predetermined depth. The resulting metastable near-surface regions of the ceramic material are then contacted with energy pulses from collapsing, ultrasonically-generated cavitation bubbles in a liquid medium for removing to a selected depth the ion-damaged near-surface regions containing the bi-axially strained lattice structure from the ceramic body.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: August 1, 1995
    Assignee: Martin Marietta Energy Systems, Inc.
    Inventors: Lynn A. Boatner, Janet Rankin, Paul Thevenard, Laurence J. Romana
  • Patent number: 5429714
    Abstract: A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: July 4, 1995
    Assignees: ETRON Technology Inc., Industrial Technology Research Institute
    Inventors: Hsiao-Chin Tuan, Hu H. Chao
  • Patent number: 5421958
    Abstract: A pattern of porous silicon is produced in the surface of a silicon substrate by forming a pattern of crystal defects in said surface, preferably by applying an ion milling beam through openings in a photoresist layer to the surface, and then exposing said surface to a stain etchant, such as HF:HNO.sub.3 :H.sub.2 O. The defected crystal will preferentially etch to form a pattern of porous silicon. When the amorphous content of the porous silicon exceeds 70% the porous silicon pattern emits visible light at room temperature.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: June 6, 1995
    Assignee: The United States of America as represented by the Administrator of the United States National Aeronautics and Space Administration
    Inventors: Robert W. Fathauer, Eric W. Jones
  • Patent number: 5418114
    Abstract: A mercury cadmium telluride (MCT) substrate 30 is immersed in a liquid 34 (e.g. 0.1 molar concentration hydrochloric acid) and illuminated with collimated radiation 24 (e.g. collimated visible/ultraviolet radiation) produced by a radiation source 20 (e.g. a 150 Watt mercury xenon arc lamp). A window 26 which is substantially transparent to the collimated radiation 24 allows the radiated energy to reach the MCT substrate 30. An etch mask 32 may be positioned between the radiation source 20 and the substrate 30. The MCT substrate 30 and liquid 34 may be maintained at a nominal temperature (e.g. 25.degree. C.). Without illumination, the MCT is not appreciably etched by the liquid. Upon illumination the etch rate is substantially increased. A further aspect is the addition of a passivant (e.g. iodine) to the liquid which forms a substantially insoluble passivation layer 36 on the substrate which is removed or partially removed by the radiation 24.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: May 23, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Monte A. Douglas
  • Patent number: 5415043
    Abstract: An acceleration sensor is used in particular for recognizing an impact experienced by a motor vehicle. The sensor has a spring-mass system (1) with at least one stable original position (4) and one stable deflection position (5). Upon acceleration in the measuring direction, the spring-mass system is initially deflected only slightly out of the original position (4). However, if a predetermined acceleration value is exceeded, then the spring-mass system (1) jumps into the deflection position (5), in which an electrical contact is closed.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: May 16, 1995
    Assignee: Robert Bosch GmbH
    Inventors: Erich Zabler, Johannes Widder
  • Patent number: 5413953
    Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: May 9, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Sun-Chieh Chien, Ming-Hua Liu
  • Patent number: 5413672
    Abstract: An etching method for etching a sendust film formed on a substrate is disclosed. In this method, a mixture of acid solutions of nitric acid and hydrochloric acid is used as an etching liquid. The etching is desirably effected while the sendust film is directly or indirectly held in electrical connection with a ferrite member, with an area of a portion of the ferrite member which contacts the etching liquid being twice to twelve times a total area of etched portions of the sendust film. Also disclosed is a method for pattern-etching a sendust film, and a chromium base film formed between the sendust film and a substrate, which includes the steps of: (a) etching the sendust film to form a predetermined sendust pattern; and (b) etching the chromium base film to form a chromium pattern which conforms to the predetermined sendust pattern, such that the chromium base film is directly or indirectly held in electrical connection with a chromium bulk.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: May 9, 1995
    Assignee: NGK Insulators, Ltd.
    Inventors: Eigo Hirotsuji, Naoya Fukuda
  • Patent number: 5411628
    Abstract: A non-photographic diffusion patterning method for making patterns in organic films utilizing a screen having a plurality of recessed polygon-shaped apertures.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: May 2, 1995
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Carl B. Wang