Wire Bonding Patents (Class 228/180.5)
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Patent number: 10049966Abstract: A semiconductor device includes a leadframe that includes contact pins and a semiconductor die that has protruding connection formations. A flexible support member is disposed between the leadframe and the semiconductor die and supports the semiconductor die. The flexible support member has electrically conductive lines that extend between the leadframe and the semiconductor die. The electrically conductive lines of the flexible support member are electrically coupled with the contact pins of the leadframe and with the connection formations of the semiconductor die.Type: GrantFiled: November 18, 2016Date of Patent: August 14, 2018Assignee: STMicroelectronics S.r.l.Inventor: Alberto Arrigoni
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Patent number: 10008477Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.Type: GrantFiled: October 5, 2016Date of Patent: June 26, 2018Assignee: Invensas CorporationInventors: Belgacem Haba, Richard Dewitt Crisp, Wael Zohni
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Patent number: 9944016Abstract: An additive manufacturing resin system including an additive manufacturing print head; a continuous carbon fiber or short carbon fibers operatively connected to the additive manufacturing print head; and a tailored resin operatively connected to the print head, wherein the tailored resin has a resin mass and wherein the tailored resin includes an epoxy component, a filler component, a catalyst component, and a chain extender component; wherein the epoxy component is 70-95% of the resin mass, wherein the filler component is 1-20% of the resin mass, wherein the catalyst component is 0.1-10% of the resin mass, and wherein the chain extender component is 0-50% of the resin mass.Type: GrantFiled: July 17, 2015Date of Patent: April 17, 2018Assignee: Lawrence Livermore National Security, LLCInventor: James Lewicki
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Patent number: 9911718Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, at least one redistribution layer includes first interconnect pads on a lower surface and second interconnect pads on an upper surface of the at least one redistribution layer. Interconnect structures are on and extend away from corresponding upper surfaces of the second interconnect pads. A microelectronic device is coupled to an upper surface of the at least one redistribution layer. A dielectric layer surrounds at least portions of shafts of the interconnect structures. The interconnect structures have upper ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.Type: GrantFiled: November 16, 2016Date of Patent: March 6, 2018Assignee: Invensas CorporationInventors: Ashok S. Prabhu, Rajesh Katkar
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Patent number: 9905502Abstract: A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.Type: GrantFiled: September 12, 2016Date of Patent: February 27, 2018Assignee: Tessera, Inc.Inventor: Wael Zohni
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Patent number: 9905652Abstract: In a conventional semiconductor chip, the source electrode and the sense pad electrode for current detection are provided separately and distanced from each other on the front surface of the semiconductor chip. The area occupied by the sense pad electrode must be several times the area of a MOSFET cell unit. Therefore, there is a problem that the area of the sense pad electrode is enlarged relative to the source electrode. Provided is a semiconductor device including a semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a first wire for a first terminal connected to the front surface electrode; and a second wire for current sensing connected to the front surface electrode. A resistance of a path through which current flows through the second wire is higher than a resistance of a path through which the current flows through the first wire.Type: GrantFiled: January 31, 2017Date of Patent: February 27, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takeyoshi Nishimura
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Patent number: 9897627Abstract: A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.Type: GrantFiled: March 25, 2017Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bing Dang, John U. Knickerbocker, Jae-Woong Nah, Robert E. Trzcinski, Cornelia Kang-I Tsang
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Patent number: 9897631Abstract: A current sensor including a measurement torus, arranged in a casing positioned around an electric conductor able to transmit an electric current, and a device for detecting a voltage in the electric conductor. The detection device is configured for surrounding the electric conductor when the current sensor is installed.Type: GrantFiled: February 1, 2016Date of Patent: February 20, 2018Assignee: SCHNEIDER ELECTRIC INDUSTRIES SASInventors: Erick Contini, Pascal Houbre, Michel Clemence
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Patent number: 9892936Abstract: A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which include a plurality of through-holes (420) from the first to the second pad surface. Another pad side includes one or more elongated windows (421) between the pad surfaces. The second pad surface includes a plurality of grooves. The leadframe further has a plurality of leads (430) with opposite elongated sides castellated by indents (431). Layers (440) of bondable metals are restricted to localized areas surrounding bond spots. A semiconductor chip (450) is attached to the pad and wire-bonded (460) to the bond spots. A package (470) encapsulates the chip, wires, pad, and lead portions, and secures the leadframe into the package by filling the through-holes, windows, grooves, and indents.Type: GrantFiled: November 1, 2016Date of Patent: February 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wei Fen Sueann Lim, Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz
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Patent number: 9883711Abstract: A shoe with a three-dimensional (3-D) surface texture created using rapid manufacturing techniques is provided. A plurality of 3-D surface texture options is presented on a user interface; each of the options is associated with one of a plurality of 3-D surface textures to be applied to a portion of a shoe. A selection of a 3-D surface texture is received and is used in part to generate a design file. The design file is used to instruct a rapid manufacturing device to manufacture the portion of the shoe comprised of the 3-D surface texture using a rapid manufacturing technique.Type: GrantFiled: July 23, 2015Date of Patent: February 6, 2018Assignee: Converse Inc.Inventors: Sean M. McDowell, Bryan Paul Cioffi
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Patent number: 9878495Abstract: A variety of techniques are disclosed for visual and functional augmentation of a three-dimensional printer.Type: GrantFiled: September 6, 2013Date of Patent: January 30, 2018Assignee: MakerBot Industries, LLCInventors: Ariel Douglas, Theodore Brandston
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Patent number: 9821502Abstract: An additive manufacturing extrusion head includes a nozzle for accepting and depositing a heated material onto a work surface and/or part. The nozzle includes a valve body and an internal poppet body moveable between positions to permit deposition of at least two bead sizes of heated material onto a work surface and/or part.Type: GrantFiled: September 11, 2015Date of Patent: November 21, 2017Assignee: UT-BATTELLE, LLCInventors: Randall F. Lind, Brian K. Post, Colin L. Cini
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Patent number: 9799624Abstract: A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.Type: GrantFiled: August 17, 2016Date of Patent: October 24, 2017Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Po-Chun Lin
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Patent number: 9793236Abstract: Provided is a wire-bonding apparatus (10) including: a capillary (28) through which a wire (30) inserted; and a controller (80). The controller (80) is configured to execute operations including: a disconnection operation, after the second bonding operation, of moving the capillary through which the wire is inserted within a horizontal plane vertical to an axial direction of the capillary while the wire is held in the clamped state, and thereby disconnecting the wire from the second bonding point; a preliminary bonding operation of feeding the wire from the second bonding point to a predetermined preliminary bonding point, and performing preliminary bonding at the preliminary bonding point; and a shaping operation, after the preliminary bonding operation, of shaping the wire projecting from a tip of the capillary into a predetermined flexed shape.Type: GrantFiled: May 15, 2015Date of Patent: October 17, 2017Assignee: SHINKAWA LTD.Inventors: Naoki Sekine, Motoki Nakazawa, Yasuo Nagashima
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Patent number: 9780062Abstract: The method of manufacturing a functional inlay comprises the steps of: a support layer with at least a first and a second side a wire antenna in said support layer processing said support layer with said embedded wire antenna to a connection station in which said support layer is approached on said first side by a holding device holding a chip with a surface comprising connection pads; said support layer is approached on said second side by a connection device; and said antenna wire is connected to said connection pads by means of a reciprocal pressure exerted between said holding device and said connection device.Type: GrantFiled: September 19, 2016Date of Patent: October 3, 2017Assignee: ASSA ABLOY ABInventors: Stephane Ayala, Urs Furter, Laurent Pellanda
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Patent number: 9728484Abstract: Disclosed relates to a power module package and a method for manufacturing the same. The power module package includes a lower substrate on which a pattern is formed, a power semiconductor element and a ribbon which are separated apart from each other at a predetermined distance to be mounted on an upper surface of the lower substrate, a first spacer attached to an upper portion of the power semiconductor element via a first adhesive layer, a second spacer attached to an upper portion of the ribbon via a second adhesive layer, and an upper substrate attached to an upper portion of each of the first and second spacers via a third adhesive layer.Type: GrantFiled: June 10, 2016Date of Patent: August 8, 2017Assignee: HYUNDAI MOBIS Co., Ltd.Inventor: Jae Hyun Ko
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Patent number: 9728493Abstract: A semiconductor device package includes a leadframe and a semiconductor chip mounted to the leadframe. The semiconductor device package further includes a molded encapsulant configured to cast-in-place the leadframe. A surface area of the leadframe remains exposed by the encapsulant. An electrically insulating covering layer extends over a part of the surface area and is configured to divide the surface area in at least two zones.Type: GrantFiled: August 28, 2015Date of Patent: August 8, 2017Assignee: Infineon Technologies AGInventors: Volker Strutz, Rainer Schaller
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Patent number: 9691706Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.Type: GrantFiled: April 20, 2012Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung
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Patent number: 9627298Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.Type: GrantFiled: November 12, 2015Date of Patent: April 18, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Teruaki Kanzaki
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Patent number: 9564395Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.Type: GrantFiled: July 27, 2015Date of Patent: February 7, 2017Assignee: MEDIATEK INC.Inventors: Hsing-Chih Liu, Chia-Hao Yang, Ying-Chih Chen
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Patent number: 9498851Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.Type: GrantFiled: December 18, 2014Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Yi-Li Hsiao, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
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Patent number: 9502374Abstract: A capillary is utilized to form the wedge wire bond comprised in a wire interconnection. A wire holding device is located above a wire clamp and the capillary to secure the wire while the wire clamp is open and not clamping onto the wire. The wire clamp and the capillary may be lifted relative to the wire in a direction away from the wedge wire bond and towards the wire holding device so as to pay out a length of wire from the capillary. At a predetermined height of the capillary, the wire clamp is closed to clamp onto the wire, and thereafter, the capillary and wire clamp may be moved further away from the wedge wire bond to cause the wire to break away from the wedge wire bond and to form the wire tail with a desired length extending from the capillary.Type: GrantFiled: October 24, 2012Date of Patent: November 22, 2016Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD.Inventors: Keng Yew Song, Wai Wah Lee, Yi Bin Wang, Wen Hua Guo, Xin Wei Zhang
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Patent number: 9469071Abstract: A fused filament fabrication system and method comprises a motor for moving the system along a linear rail during operation, a drive gear coupled to the motor. The drive gear rotates in the direction of the motor during operation and selectively operatively engages first or second idler gears during operation of the system. The system also comprises first and second filaments for the selective passage of material to corresponding first and second extruders, the first filament is positioned between the first idler gear shaft and idler bearing and the second filament is positioned between the second idler gear shaft and idler bearing.Type: GrantFiled: July 31, 2014Date of Patent: October 18, 2016Assignee: Douglass Innovations, Inc.Inventors: Brian L. Douglass, Carl R. Douglass, III
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Patent number: 9461431Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.Type: GrantFiled: June 26, 2015Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Gregorio R. Murtagian, Bhanu Jaiswal, Sriram Srinivasan, Michael J. Hill
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Patent number: 9455544Abstract: A method of forming a wire loop is provided. The method includes the steps of: (1) forming a conductive bump on a bonding location using a wire bonding tool; (2) bonding a portion of wire to another bonding location using the wire bonding tool; (3) extending a length of wire from the bonded portion of wire toward the bonding location; (4) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and (5) interrupting the lowering of the wire bonding tool during step (4) if the wire bonding tool reaches a predetermined height.Type: GrantFiled: August 3, 2011Date of Patent: September 27, 2016Assignee: Kulicke and Soffa Industries, Inc.Inventor: Gary S. Gillotti
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Patent number: 9437520Abstract: A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member.Type: GrantFiled: March 13, 2013Date of Patent: September 6, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Norimune Orimoto, Makoto Imai
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Patent number: 9373767Abstract: A light emitting device of the invention includes a substrate having a metal on a surface thereof; a light emitting element installed on the surface of the substrate; a wire that connects the light emitting element and the metal; and a light reflecting member that covers the metal, the wire having a first bonding ball that is disposed on a surface of the metal, and an extension that extends above the first bonding ball, and the light reflecting member having a protrusion over the first bonding ball.Type: GrantFiled: September 22, 2014Date of Patent: June 21, 2016Assignee: NICHIA CORPORATIONInventor: Shinya Okura
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Patent number: 9362254Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad. A package structure using the wire bonding method is also provided.Type: GrantFiled: February 12, 2015Date of Patent: June 7, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Po-Chun Lin
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Patent number: 9236332Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.Type: GrantFiled: February 12, 2013Date of Patent: January 12, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, KiYoun Jang, HunTeak Lee
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Patent number: 9230937Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.Type: GrantFiled: May 10, 2012Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Kaori Sumitomo, Hideyuki Arakawa, Hiroshi Horibe, Yasuki Takata
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Patent number: 9165903Abstract: A multi-functional detachable and replaceable wire bonding heating plate is provided with a heat blocking layer, a heating layer, a heat equalization layer, and a top layer. The bottom of the heat blocking layer has a recessed portion and the heating layer is disposed on top of the heat blocking layer. The heat equalization layer is disposed on top of the heating layer. A detachable and replaceable top layer is disposed on top of the heat equalization layer wherein a protruding support block is disposed on top of the top layer. The heat equalization layer and the top layer can be securely bonded to each other by the attraction force method, the engaging method, and the vacuum method. The invention allows the top layer to be timely detached and properly replaced to meet the specifications of different lead frames or PCB substrates and can reduce the production cost.Type: GrantFiled: April 30, 2014Date of Patent: October 20, 2015Assignee: PRAM TECHNOLOGY INC.Inventor: Wen-Long Liu
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Patent number: 9105483Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.Type: GrantFiled: February 24, 2012Date of Patent: August 11, 2015Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Publication number: 20150144682Abstract: A wire bonding system is provided. The system includes a bond head, a bonding tool carried by the bond head, a wire supply configured for bonding by the bonding tool, and a wire shaping tool carried by the bond head. The wire shaping tool is independently moveable with respect to the bond head and the bonding tool.Type: ApplicationFiled: January 28, 2015Publication date: May 28, 2015Applicant: Orthodyne Electronics CorporationInventor: Jonathan Michael Byars
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Patent number: 9021682Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.Type: GrantFiled: June 19, 2012Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
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Publication number: 20150098170Abstract: The invention relates to a wire, preferably a bonding wire for bonding in microelectronics, containing a copper core with a surface and a coating layer containing aluminum superimposed over the surface of the core. In any cross-sectional view of the wire, the area share of the coating layer is from 20 to 50% based on the total area of the cross-section of the wire, and the aspect ratio between longest and shortest paths through the wire is from larger than 0.8 to 1.0. The wire has a diameter of from 100 ?m to 600 ?m. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.Type: ApplicationFiled: May 7, 2013Publication date: April 9, 2015Applicant: HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KGInventors: Eugen Milke, Peter Prenosil, Sven Thomas
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Patent number: 8998063Abstract: A wire bonding system is provided. The system includes a bond head, a bonding tool carried by the bond head, a wire supply configured for bonding by the bonding tool, and a wire shaping tool carried by the bond head. The wire shaping tool is independently moveable with respect to the bond head and the bonding tool.Type: GrantFiled: January 22, 2013Date of Patent: April 7, 2015Assignee: Orthodyne Electronics CorporationInventor: Jonathan Michael Byars
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Patent number: 8991681Abstract: A die bonder and a bonding method are disclosed which make it possible to provide high-quality products, particularly even if a die is rotated through predetermined degrees relative to an already-bonded die and then laminated. In the die bonder and bonding method in which a die is picked up from a wafer by a pick-up head which then places the die on an alignment stage, and the die is picked up from the alignment stage by a bonding head which then bond the die onto a substrate or an already-bonded die, a posture of the die is rotated through predetermined degrees on a plane parallel to a plane on which the bonding is performed, before the bonding head picks up the die from the alignment stage.Type: GrantFiled: March 6, 2012Date of Patent: March 31, 2015Assignee: Hitachi High-Tech Instuments Co., Ltd.Inventors: Hiroshi Maki, Masayuki Mochizuki, Yukio Tani, Takehito Mochizuki
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Publication number: 20150061706Abstract: The present invention relates to a process for preparing a humidity sensor based on resistive type porous Magnesium Ferrite (MgFe2O4) pellets and a humidity sensor thereof. More particularly, the present invention includes a synthesis process of preparing 30 to 40% porous MgFe2O4 pellets. The process further includes making Ohmic contacts on the porous MgFe2O4 pellets. The process is very cost effective and optimized to keep the resistance of the porous MgFe2O4 pellets in the range 200-300M?. Further, the response and recovery time of the porous MgFe2O4 pellets to humidity is in the range of few seconds only. Further, the porous MgFe2O4 pellets can be used for humidity sensing for more than 12 months. Due to resistance stability even after long-term exposure in humidity, the porous MgFe2O4 pellets do not require flash heating.Type: ApplicationFiled: August 22, 2014Publication date: March 5, 2015Inventors: Ravinder Kumar KOTNALA, Jyoti SHAH, Hari KISHAN, Bhikham SINGH
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Publication number: 20150037603Abstract: Methods of effecting bond adhesion between metal structures, methods of preparing articles including bonded metal structures, and articles including bonded metal structures are provided herein. In an embodiment, a method of effecting bond adhesion between metal structures includes forming a first metal structure on a substrate. The first metal structure includes grains that have a {111} crystallographic orientation, and the first metal structure has an exposed contact surface. Formation of an uneven surface topology is induced in the exposed contact surface of the first metal structure after forming the first metal structure. A second metal structure is bonded to the exposed contact surface of the first metal structure after inducing formation of the uneven surface topology in the exposed contact surface.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Ernesto Gene de la Garza, Martin O'Toole
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Publication number: 20150021376Abstract: A method for bonding a wire to a substrate includes forming a wire ball at a working tip of a capillary and contacting the wire ball to a substrate via the capillary. The method also includes driving a protrusion at the working tip of the capillary into contact with a region of the substrate surrounding the wire ball. A capillary for wire bonding includes a working face, an annular chamfer section, and a cylindrical bore offsetting the annular chamfer section from the working face. A capillary for wire bonding includes a capillary body comprising a working tip having a working face. The capillary body defines an axial passage extending from the working face along a longitudinal axis of the capillary. The axial passage includes a cylindrical bore extending internally from the working face, and a first annular chamfer having a major diameter defined by the cylindrical bore.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Trent Uehling, Ilko Schmadlak
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Patent number: 8936187Abstract: A connecting method of a single core electric wire to a stranded electric wire which can prevent a contact resistance from increasing is provided. The connecting method includes a tube inserting process that a single core wire and a twisted wire are respectively inserted from openings and of a tubular joint terminal having a single core wire inserting part from an end part to a prescribed position in an interior side and a twisted wire inserting part from the other end part to the single core wire inserting part in the interior side, and a metallic bond process that an end face contacts under pressure with an end face and the single core electric wire is rotated in a twisting direction of the twisted wire to metallically bond the end faces.Type: GrantFiled: March 25, 2014Date of Patent: January 20, 2015Assignee: Yazaki CorporationInventor: Fumie Hino
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Patent number: 8936730Abstract: An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface.Type: GrantFiled: August 6, 2013Date of Patent: January 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu, Yi-Li Hsiao
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Patent number: 8931684Abstract: The described embodiment relates generally to the field of inductive bonding. More specifically an inductive heater designed for use in assembling electronics is disclosed. A number of methods for shaping a magnetic field are disclosed for the purpose of completing an inductive bonding process without causing harm to unshielded adjacent electrical components.Type: GrantFiled: March 7, 2014Date of Patent: January 13, 2015Inventors: Michael Nikkhoo, Amir Salehi
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Patent number: 8931685Abstract: An electric wire connecting method for connecting together a wire having a conductor and a stranded wire having a plurality of strands which are twisted, the electric wire connecting method is provided. The electric wire connecting method includes a forming step and a welding step. In the forming step, the conductor is formed into a plate element by pressing the conductor. In the welding step, the strands are welded to the plate element in a state where the strands are superposed on the plate element.Type: GrantFiled: December 30, 2013Date of Patent: January 13, 2015Assignee: Yazaki CorporationInventor: Masayuki Kataoka
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Patent number: 8919632Abstract: Disclosed is a method of detecting a bonding failure of a wire bonder, which comprises a bonding tool operative to form an electrical connection between a semiconductor die and a substrate using a bonding wire. The method comprises the steps of: forming a first wire bond on a first surface located on the semiconductor die using the bonding tool and the bonding wire; forming a second wire bond on a second surface located on the substrate using the bonding tool and the bonding wire such that a wire loop connects the first and second wire bonds, wherein the first surface is not electrically-conductive; moving the bonding tool in a direction away from the second wire bond to break the bonding wire from the second wire bond; detecting whether the second wire bond remains bonded to the substrate; and determining an occurrence of the bonding failure if the second wire bond is no longer bonded to the substrate.Type: GrantFiled: November 9, 2012Date of Patent: December 30, 2014Assignee: ASM Technology Singapore Pte. Ltd.Inventors: Wei Liu, Qian Zhang, Joon Ho Lee, Jung Min Kim
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Publication number: 20140374467Abstract: A capillary bonding tool for wire bonding includes a first section, a second section and a bonding section. The first section has a first outer peripheral sidewall, an opposing first inner sidewall that extends generally parallel to the central longitudinal axis, and a first opening surrounded by the first inner sidewall. The second section has a second outer peripheral sidewall, an opposing second inner sidewall that extends at an angle with respect to the central longitudinal axis, and a second tapered opening surrounded by the second inner sidewall. The bonding section has a peripheral ridge extending axially outwardly from the second inner sidewall of the second section. The peripheral ridge has a third outer peripheral sidewall, a third inner tubular sidewall that extends generally parallel to the central longitudinal axis and radially outwardly of the first inner sidewall, and a third opening surrounded by the third inner tubular sidewall.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Jia Lin Yap, Yin Kheng Au, Lai Cheng Law
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Patent number: 8899469Abstract: A method of performing a wire bonding operation is provided. The method includes the steps of: (a) performing a wire bonding operation between a portion of wire and a bonding location using a bonding tool; (b) raising the bonding tool to a desired height; (c) performing a test to determine if the portion of wire is sufficiently bonded to the bonding location; and (d) automatically performing another wire bonding operation between the portion of wire and the bonding location using the bonding tool if, during step (c), it is determined that the portion of wire was not sufficiently bonded to the bonding location in step (a).Type: GrantFiled: February 19, 2014Date of Patent: December 2, 2014Assignee: Kulicke and Soffa Industries, Inc.Inventors: Gary S. Gillotti, John Foley
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Patent number: 8893953Abstract: A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.Type: GrantFiled: January 30, 2013Date of Patent: November 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Joon-gil Lee
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Publication number: 20140339290Abstract: Provided is a wire bonding method. The method includes: positioning a capillary having a wire inserted on a substructure including at least three connection terminals spaced apart from each other; forming an adhesive ball at a tip of the wire; bonding the adhesive ball to one of the connection terminals by lowering the capillary; and connecting the other connection terminals to the same wire by moving the capillary.Type: ApplicationFiled: May 15, 2014Publication date: November 20, 2014Inventors: Won-Gil HAN, Byongjoo KIM, Sangyoung KIM, Tae-Gyeong CHUNG, Sungbok HONG
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Patent number: 8881966Abstract: An improvement in the quality of wire bonding is achieved by reducing the vibration of a lead frame or a wiring substrate after wire bonding. Over a heat block in a wire bond portion of a wire bonder, there is provided a cooling blower for cooling a wire-bonded matrix frame so that the temperature thereof may decrease stepwise. After wire bonding, cold air is blown from the cooling blower to the matrix frame, and temperature control of the matrix frame is performed so that the temperature of the matrix frame after wire bonding may decrease stepwise. Or, the wire-bonded matrix frame is fixed with a holding tool such as a frame holding member, a guide member, a roller means, or an elastic means until cooling is completed.Type: GrantFiled: December 9, 2009Date of Patent: November 11, 2014Assignee: Renesas Electronics CorporationInventors: Kazuyuki Misumi, Hideyuki Arakawa, Shunji Yamauchi, Mitsuru Aoki