Adherent Solid Layer Or Coating (e.g., Pretinned) Patents (Class 228/254)
  • Patent number: 10951005
    Abstract: In general the present disclosure is directed to a temperature control device, e.g., a TEC, that includes a top plate with at least first and second contact pads to allow for a soldering process to attach optical components to the first contact pad without causing one or more layers of the second contact pad to reflow and solidify with an uneven mounting surface. Thus, optical components such as a focus lens can be mounted to the second contact pad via, for instance, thermal epoxy. This avoids the necessity of a submount to protect the focus lens from the relatively high heat introduced during a soldering process as well as maintain the flatness of the second contact pad within tolerance so that the mounted focus lens optically aligns by virtue of its physical location/orientation with other associated optical components coupled to the first contact pad, e.g., a laser diode.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 16, 2021
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Chong Wang, Kai-Sheng Lin, YongXuan Liang
  • Patent number: 10910508
    Abstract: A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: February 2, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Randolph R. Kay, Seethambal S. Mani, Andrew Pomerene, Andrew Lea Starbuck, Reinhard Brock, Douglas Chandler Trotter, Adam Jones
  • Patent number: 10900918
    Abstract: A test system and method for thermoelectric module. The test system includes an electrical performance test unit, a heat flux detection unit, and a processor. The electrical performance test unit connects with the thermoelectric module under power generation state to test output power of the thermoelectric module and working current and internal resistance under this output power. The heat flux detection unit includes a heat flux sensor installed at a cold-end of the thermoelectric module to detect the heat flux. The processor electrically connects with the electrical performance test unit and the heat flux detection unit to calculate the thermoelectric conversion efficiency ? of thermoelectric module. By using the technical scheme of the invention, the detection of the thermoelectric conversion efficiency of the thermoelectric module is accomplished.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: January 26, 2021
    Inventor: Anjun Jin
  • Patent number: 10578570
    Abstract: A test system and method for thermoelectric module. The test system includes an electrical performance test unit, a heat flux detection unit, and a processor. The electrical performance test unit connects with the thermoelectric module under power generation state to test output power of the thermoelectric module and working current and internal resistance under this output power. The heat flux detection unit includes a heat flux sensor installed at a cold-end of the thermoelectric module to detect the heat flux. The processor electrically connects with the electrical performance test unit and the heat flux detection unit to calculate the thermoelectric conversion efficiency ? of thermoelectric module. By using the technical scheme of the invention, the detection of the thermoelectric conversion efficiency of the thermoelectric module is accomplished.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: March 3, 2020
    Inventors: Anjun Jin, Dawei Liu, Qiming Li, Wenbo Peng, Shisen Xu
  • Patent number: 10376997
    Abstract: Processes of joining substrates via transient liquid phase bonding (TLPB). The processes include providing an interlayer of a low melting temperature phase (LTP) that includes Sn and Bi between and in contact with at least two substrates, and heating the substrates and the interlayer therebetween at a processing temperature equal to or above 200° C. such that the interlayer liquefies and the LTP interacts with high melting temperature phases (HTPs) of the substrates to yield isothermal solidification of the interlayer. The processing temperature is maintained for a duration sufficient for the interlayer to be completely consumed and a solid bond is formed between the substrates. Also provided are assemblies formed by the above noted processes.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 13, 2019
    Assignee: Purdue Research Foundation
    Inventors: Carol A. Handwerker, John Ryan Holaday
  • Patent number: 10305113
    Abstract: A core-shell catalyst with high platinum mass activity for a short period of time. The method for producing a core-shell catalyst may comprise a core containing palladium and a shell containing platinum and coating the core, the method comprising: a step of preparing a copper-coated palladium-containing particle dispersion in which copper-coated palladium-containing particles are dispersed, the particles being palladium-containing particles coated with copper; a step of preparing a platinum ion-containing solution; a step of preparing a microreactor; and a substitution step of forming the shell by substituting the copper on the copper-coated palladium-containing particle surface with platinum by mixing the copper-coated palladium-containing particle dispersion and the platinum ion-containing solution in the microreactor.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 28, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshihiro Hori, Shotaro Ishikawa
  • Patent number: 9514858
    Abstract: An elongate electrically conductive element has a core made of copper or copper alloy and at least one white-bronze layer encircling the core made of copper or copper alloy, wherein the white-bronze layer is the outermost layer of the elongate electrically conductive element.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: December 6, 2016
    Assignee: NEXANS
    Inventor: Christophe Brismalein
  • Patent number: 9449948
    Abstract: The present invention relates to a chip support substrate including a lyophilic region 4 that is formed on the substrate and that absorbs a chip 3A, and an electrode 6 that is formed on the substrate and in the lyophilic region and that generates electrostatic force in the chip, and to a chip support method including the steps of arranging the chip onto the lyophilic region of the chip support substrate with a liquid 15, the chip support substrate comprising the lyophilic region that is formed on the substrate, and the electrode that is formed on the substrate and in the lyophilic region, and generating the electrostatic force in the chip corresponding to the electrode by applying a voltage to the electrode.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 20, 2016
    Assignee: TOHOKU UNIVERSITY
    Inventors: Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima
  • Patent number: 9443821
    Abstract: A method of forming an electronic device, comprising providing a semiconductor substrate having a first contact and an undoped electroplated lead-free solder bump formed on the first contact. The method also comprises providing a device package substrate having a second contact and a doped lead-free solder layer on the second contact comprising a fourth row transition metal dopant. The method further comprises melting the solder bump and the solder layer while the solder layer and the solder bump are in contact, thereby forming a doped solder bump consisting essentially of Sn, one or both of Ag and Cu, and the fourth row transition metal dopant.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 13, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mark Bachman, John W. Osenbach
  • Patent number: 9431366
    Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Katsuyuki Sakuma
  • Patent number: 9308603
    Abstract: A solder and a solder joint structure formed by the solder are provided. The solder includes a zinc-based material, a copper film, and a noble metal film. The copper film completely covers the surface of the zinc-based material. The noble metal film completely covers the copper film. The solder joint structure includes a zinc-based material and an intermetallic layer. The intermetallic layer consists of zinc and noble metal and completely covers the surface of the zinc-based material.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: April 12, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen
  • Patent number: 9258905
    Abstract: A first solder is lead-free solder that contains no lead (Pb). The first solder includes a first metal that contains at least Sn; and a second metal that contains at least a Ni—Fe alloy. An electronic component built-in module may include an electronic component and a substrate on which the electronic component is installed, where a terminal of the electronic component and a terminal of the substrate are joined together by using the lead-free solder.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: February 9, 2016
    Assignee: TDK CORPORATION
    Inventors: Tsutomu Yasui, Hisayuki Abe, Kenichi Kawabata, Tomoko Kitamura
  • Patent number: 9149883
    Abstract: Provided are a soldering device and a soldering method which allow for soldering at low cost with high yield and high reliability. The soldering device has: first organic fatty acid-containing solution bath 21 in which workpiece member 10 having a copper electrode is immersed in organic fatty acid-containing solution 31a; space section 24 having a steam atmosphere of organic fatty acid-containing solution 31b, the space section horizontally having ejection unit 33 to spray a jet stream of a molten solder to the copper electrode provided on workpiece member 10 and ejection unit 34 to spray a liquid to an excess of the molten solder for removal; and second organic fatty acid-containing solution bath 23 in which workpiece member 10 from which the excess of the molten solder is removed in space section 24 is immersed again in organic fatty acid-containing solution 31c.
    Type: Grant
    Filed: April 14, 2012
    Date of Patent: October 6, 2015
    Assignee: TANIGUROGUMI CORPORATION
    Inventor: Katsumori Taniguro
  • Patent number: 9105629
    Abstract: A method of forming a 3D package including joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat, a first selective non-uniform cooling, and first uniform pressure, joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure, heating the 3D package and the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where a temperature of the first and second selective non-uniform heat is less than the reflow temperature of the first and second pluralities of solder bumps, respectively.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Katsuyuki Sakuma
  • Patent number: 9070754
    Abstract: The present invention prevents bumps on semiconductor chips from sticking to probe needles and coming off from the semiconductor chips. A wafer has effective areas where a plurality of bumps (first bumps) are formed. The bumps are formed on the side of an active surface of the semiconductor chips. The wafer further has non-effective areas where a plurality of dummy bumps are formed. Among the dummy bumps, some positioned at the outermost circumference are dummy bumps (second bumps) that are smaller than the other bumps. The dummy bumps (second bumps) intersect the inner peripheral edge of a shielding member as viewed in a plan view. The dummy bumps (second bumps) are formed over third pad electrodes. A bump-formation insulating film is removed from over the entire third pad electrodes.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 30, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akinori Yutani, Kouji Soejima
  • Patent number: 9004343
    Abstract: In a reflow soldering apparatus, air heated by heaters is blown by fans onto a printed circuit board. Temperature controllers that control temperature of the heaters supply operation amount thereof to a calculation unit that calculates consumed electric energy of soldering apparatus. Inverters that control revolution of fans supply a value of current to the calculation unit. A control unit supplies a coefficient of the consumed electric energy to the calculation unit. The calculation unit calculates a total amount of consumed electric energy of the reflow soldering apparatus based on the operation amount, value of current and coefficient of the consumed electric energy thus obtained. A display unit displays on an operation screen the total amount of consumed electric energy of the reflow soldering apparatus, which has been calculated by the calculation unit.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: April 14, 2015
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyuki Inoue, Tadayoshi Ohtashiro
  • Patent number: 8991869
    Abstract: A method for forming a fluid tight seal is disclosed. The method may make use of a first component having a first sealing surface, and a second component having a second sealing surface. The method may further involve coating one of the first and second sealing surfaces with a metallic film layer adapted to transform into a liquefied metallic layer when a temperature of one of the first and second surfaces exceeds a melting temperature of a metal used to form the metallic film layer. Once it becomes liquefied, the liquefied metallic layer forms a pressure-tight seal between the sealing surfaces.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 31, 2015
    Assignee: The Boeing Company
    Inventors: Lawrence J. Pionke, Michael H. Curry
  • Patent number: 8960525
    Abstract: A brazing process and plate assembly are disclosed. The brazing process includes positioning a braze foil on a first workpiece, then securing the braze foil to the first workpiece to form a brazable component, then positioning a second workpiece proximal to the brazable component, and then brazing the second workpiece to the brazable component. Additionally or alternatively, the brazing process includes positioning the braze foil on a tube, then securing the braze foil to the tube to form a brazable tube, then positioning a plate of a plate assembly proximal to the brazable tube, and then brazing the plate to the brazable tube. The plate assembly includes a plate and a tube brazed to the plate by a braze foil secured to the tube.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 24, 2015
    Assignee: General Electric Company
    Inventors: David Edward Schick, Srikanth Chandrudu Kottilingam, Johnie Franklin McConnaughhay, Brian Lee Tollison, Yan Cui
  • Patent number: 8963057
    Abstract: Apparatus and method are provided for an electric induction brazing process in an inert atmosphere using a substantially oxygen-free copper alloy filler or preform under an inert atmosphere within a brazing chamber minimally sized for containment of the brazed joint region and an induction coil. The inert atmosphere may be nitrogen gas supplied from a liquid nitrogen source. For brazing of an open-interior fitting around a hole in a tubular material a nesting area is provided around the hole for seating of the filler or preform and the fitting.
    Type: Grant
    Filed: October 26, 2008
    Date of Patent: February 24, 2015
    Assignee: Radyne Corporation
    Inventors: Brian R. Gramoll, Robert P. Frank
  • Patent number: 8939348
    Abstract: After a microcrystalline layer having a grain size that is finer than that of a base member is formed on the surface of at least one of a first bonding portion and a second bonding portion, the gap between the first bonding portion and the second bonding portion is filled with a solution into which copper oxide can be eluted, so as to deposit copper oxide contained in the surface oxide film into the solution. By applying pressure and by heating at a temperature of at most the copper recrystallization temperature, the components contained in the solution are removed except for copper, so as to elute copper oxide, thereby bonding the first bonding portion and the second bonding portion via the copper thus deposited. Subsequently, the copper is solid-phase diffused into the first bonding portion and the second bonding portion.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: January 27, 2015
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Koichi Saito
  • Patent number: 8777088
    Abstract: Methods of attaching cutting elements to earth-boring tools, comprising abutting a portion of a cutting element against at least one surface of an earth-boring tool with a braze material disposed therebetween; and brazing the cutting element to the earth-boring tool by applying high-frequency vibrations to cause the braze material to become flowable. Methods of securing cutting elements to earth-boring tools may comprise at least partially coating a cutting element with a braze material. The cutting element may be at least partially disposed in a pocket formed in a body of an earth-boring tool with the braze material adjacent surfaces defining the pocket. The cutting element and the braze material may be ultrasonically torsionally oscillated to braze the cutting element within the pocket.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Baker Hughes Incorporated
    Inventors: Tu Tien Trinh, Eric C. Sullivan, Xiaomin Chris Cheng
  • Patent number: 8763884
    Abstract: The present invention relates to a joint (10) that includes a first member (11) to be jointed, a second member (12) to be jointed and a jointing layer (13) located between the first member (11) and the second member (12). The jointing layer (13) is made of Sn metal and a metallic material with a melting point higher than the melting point of the Sn metal. The present invention relates also to a method of joining this first member (11) to the second member (12).
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Takahashi, Tatsuoki Kono, Mitsuhiro Oki, Akiko Suzuki
  • Patent number: 8733620
    Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Susheel G. Jadhav
  • Patent number: 8701973
    Abstract: A method of forming solder bumps on electrodes of a circuit board without producing bridging using a solder transfer sheet which does not require alignment includes superposing a circuit board and a solder transfer sheet having a solder layer adhered to at least one side of a supporting substrate, performing heating under pressure to a temperature lower than the solidus temperature of the solder to selectively perform solid phase diffusion bonding of the solder layer to electrodes, and peeling the transfer sheet from the circuit board. The solder layer is in the form of a continuous solder coating or in the form of a monoparticle layer of solder particles which are adhered to the supporting substrate by an adhesive layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: April 22, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Takeo Kuramoto, Kaichi Tsuruta, Takeo Saitou
  • Publication number: 20140008421
    Abstract: An apparatus for dispensing flux-free solder comprises a dispenser head with a stamp to which ultrasound can be applied. Solder is dispensed by: A) moving the dispenser head above a next substrate place, B) lowering the stamp until the working surface of the stamp touches the substrate place or is located at a predetermined height above the substrate place, C) dispensing solder by: C1) advancing the solder wire until the solder wire touches the substrate place, in such a manner that the tip of the solder wire touches the substrate place within a recess of the stamp, C2) further advancing of solder wire to melt a predetermined quantity of solder, and C3) retracting the solder wire, D) moving the dispenser head to distribute the solder on the substrate place, and simultaneously applying ultrasound to the stamp, and E) raising the stamp.
    Type: Application
    Filed: June 12, 2013
    Publication date: January 9, 2014
    Inventors: Heinrich Berchtold, Rene Betschart
  • Patent number: 8601683
    Abstract: The present invention provides method of manufacture for a printed wiring board. The printed wiring board constructed according to the teachings of the present invention includes a printed wiring board dielectric layer having conductive foils located on at least two sides thereof. The printed wiring board further includes a solid core conductive material interconnecting the conductive foils.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: December 10, 2013
    Assignee: Agere Systems LLC
    Inventors: Charles Cohn, Jeffrey M Klemovage
  • Patent number: 8573469
    Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 5, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Hsin-Hua Hu, Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law
  • Patent number: 8524593
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 3, 2013
    Assignee: Semigear Inc
    Inventors: Chunghsin Lee, Jian Zhang
  • Patent number: 8517249
    Abstract: A soldering structure using Zn includes a bonding layer which contains Zn; and a lead-free solder which bonds and reacts to the bonding layer. The bonding layer can be a Zn alloy layer or a multilayer including a Zn layer. Accordingly, the characteristics of the soldering structure can be improved by involving the high reactive Zn to the interfacial reaction of the soldering.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-kyoung Choi, Chang-youl Moon, Yoon-chul Son, Young-ho Kim, Hee-ra Roh, Chang-yul Oh
  • Patent number: 8505806
    Abstract: Method for producing coated assembly parts for chemical device elements including the following series of steps: (a) the formation of an initial assembly including a steel support part, typically a plate, a zirconium or zirconium alloy coating, typically a sheet having dimensions similar to those of the steel plate, and at least one brazing material between the support part and the coating, wherein said brazing material is an alloy including silver and copper; (b) the insertion of the initial assembly into a brazing chamber with a controlled atmosphere; (c) the formation of a controlled atmosphere in said chamber; (d) the reheating of said assembly to a temperature at least equal to the melting temperature of said brazing material; wherein, prior to the formation of said initial assembly, the deposition of a titanium or titanium alloy layer on said zirconium (or zirconium alloy) coating is performed, and in that said coating is placed so that its titanium- or (titanium alloy-) coated surface is in contact w
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: August 13, 2013
    Assignee: Mersen France PY SAS
    Inventors: Ernest Totino, Emmanuel Kelbert
  • Patent number: 8492005
    Abstract: In joining a magnesium alloy material 1 (first material) and a steel material (second material), a zinc-plated steel plate 2 plated with zinc (metal C) is used as a steel material, Al (metal D) is added to the magnesium alloy material 1. Next, eutectic melting of Mg and Zn is caused so as to remove a product produced by the eutectic melting with an oxide film 1f and impurities from a joint interface. Moreover, an Al—Mg system intermetallic compound such as Al3Mg2 and an Fe—Al system intermetallic compound such as FeAl3 are produced, whereby regenerated surfaces of both materials 1 and 2 are joined via a compound layer 3 containing those intermetallic compounds.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: July 23, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeyuki Nakagawa, Kenji Miyamoto, Minoru Kasukawa, Masao Aihara, Sadao Yanagida, Akio Hirose
  • Patent number: 8479390
    Abstract: A method for producing a connector has first to fifth processes. In the first process, a contact unit having a plurality of contacts and a tying part, is formed with the contacts tied at each axial direction middle part of the contacts by the tying part and with the contacts arranged parallel to each other. In the second process, a plating layer is formed on a part of the contact unit by soaking the contact unit in a plating bath from an axial direction one end side of the contact unit to an axial direction middle part of the tying part. In the third process, the contacts are isolated by cutting the tying part. In the fourth process, a part where the plating layer is formed, of the contact is inserted into a hole of a circuit board. In the fifth process, the contacts are soldered to the circuit board.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 9, 2013
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Teruyuki Ohnishi, Shinichi Isobe, Kohtaro Shiino
  • Patent number: 8424746
    Abstract: To easily bond substrates even made of materials whose linear expansion coefficients are different from each other when manufacturing an optical component used by transmitting light through an inside thereof. Buffer layers made of an amorphous inorganic substance causing a brittle fracture are formed on bonding surfaces of a plurality of substrates having linear expansion coefficients different from one another, and the substrates to be bonded are stacked so that the buffer layers are faced to each other. Then, a heat treatment is performed for a stack, and thereby direct bonding via an atom is formed between the buffer layers.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: April 23, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Kazumasa Adachi, Motoo Takada, Kozo Ono
  • Patent number: 8413877
    Abstract: A layered structure comprising a base structure having a major surface, and a brazing layer secured to the major surface of the base structure, where the brazing layer is applied to the major surface prior to positioning the layered structure in contact with a turbine engine component.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 9, 2013
    Assignee: United Technologies Corporation
    Inventors: Christopher J. Bischof, Michael J. Minor, Paul M. Pellet, Jason E. Huxol
  • Patent number: 8403203
    Abstract: A method of attaching a component to a substrate, including providing a component guide attached to a substrate, the component guide having a cavity substantially conforming to contours of a portion of a component, attaching a first solder pad to the component, inserting the component into the guide cavity, providing a second solder pad, offset from the first solder pad and near the cavity, and inserting the component, the component guide and the substrate into an oven heating the solder pads, wherein the component is drawn further into the guide cavity by a capillary effect of the heated solder pads.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 26, 2013
    Assignee: Neonoda Inc.
    Inventors: Magnus Goertz, Thomas Eriksson, Joseph Shain, Anders Jansson, Niklas Kvist, Robert Pettersson, Lars Sparf, John Karlsson
  • Patent number: 8381964
    Abstract: A Sn—Ag bonding and a method thereof are revealed. By means of a bonding layer formed by tin and silver between wafers, the stress released by diffusion and bonding between tin(Sn) and silver(Ag) is larger than the stress released by diffusion and bonding of conventional gold-silver bonding. Moreover, a Sn—Ag bonding method of the present invention forms Sn—Ag bonding at low temperature and releases more stress so as to reduce thermal stress generated during wafer bonding effectively. And after wafer bonding, the high temperature processes can be performed.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 26, 2013
    Assignee: National Central University
    Inventors: Cheng-Yi Liu, Ming-Chung Kuo
  • Patent number: 8322596
    Abstract: A wiring substrate manufacturing method includes: preparing a wiring substrate including a core layer having a principal surface, a resin insulating layer and a conductor layer alternately laminated to form at least one laminated layer on the one principal surface of the core layer, a solder resist layer including opening portions and formed on an outermost surface of the at least one laminated layer such that respective portions of an outermost conductor layer are exposed from the opening portions; forming a Sn-containing underlying layer on the respective portions of the outermost conductor layer by a plating process; and fusing the Sn-containing underlying layer to the respective portions of the outermost conductor layer by a heating process, then mounting solder balls directly on respective portions of the Sn-containing underlying layer, and then connecting the solder balls to the respective portions of the Sn-containing underlying layers.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 4, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Takahiro Hayashi, Satoru Watanabe, Hajime Saiki, Koji Sakuma
  • Patent number: 8317233
    Abstract: A coupling apparatus that may have a first component having a first sealing surface and a second component having a second sealing surface. The first and second sealing surfaces are in facing relationship with one another when the first and second components are coupled together. One of the first and second sealing surfaces has a metallic film layer that transforms into a liquefied metal layer when the metallic film layer is exposed to a temperature that exceeds a melting temperature of a metal from which the metallic film layer is formed. The liquefied metal layer forms a seal between the sealing surfaces.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: November 27, 2012
    Assignee: The Boeing Company
    Inventors: Lawrence J. Pionke, Michael H. Curry
  • Patent number: 8226750
    Abstract: A hydrogen purifier utilizing a hydrogen-permeable membrane to purify hydrogen from mixed gases containing hydrogen is disclosed. Improved mechanical support for the permeable membrane is described, enabling forward or reverse differential pressurization of the membrane, which further stabilizes the membrane from wrinkling upon hydrogen uptake.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: July 24, 2012
    Assignee: Genesis Fueltech, Inc.
    Inventor: Peter David DeVries
  • Publication number: 20120171881
    Abstract: A permanent adapter for incandescent lighting fixtures can removably receive LEDs but cannot itself be removed from the fixture.
    Type: Application
    Filed: January 3, 2011
    Publication date: July 5, 2012
    Inventor: Scott Riesebosch
  • Patent number: 8132775
    Abstract: Solder mold plates and methods of manufacturing the solder mold plates are provided herein. The solder mold plates are used in controlled collapse chip connection processes. The solder mold plate includes a plurality of cavities. At least one cavity of the plurality of cavities has a different volume than another of the cavities in a particular chip set site. The method of manufacturing the solder mold plate includes determining susceptible white bump locations on a chip set. The method further includes forming lower volume cavities on the solder mold plate which coincide with the susceptible white bump locations, and forming higher volume cavities on the solder mold plate which coincide with less susceptible white bump locations.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventor: Lewis S Goldmann
  • Patent number: 8110022
    Abstract: A hydrogen purifier utilizing a hydrogen permeable membrane, and a gas-tight seal, where the seal is uses a low temperature melting point metal, which upon heating above the melting point subsequently forms a seal alloy with adjacent metals, where the alloy has a melting point above the operational temperature of the purifier. The purifier further is constructed such that a degree of isolation exists between the metal that melts to form the seal and the active area of the purifier membrane, so that the active area of the purifier membrane is not corrupted. A method of forming a hydrogen purifier utilizing a hydrogen permeable membrane with a seal of the same type is also disclosed.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: February 7, 2012
    Assignee: Genesis Fueltech, Inc.
    Inventor: Peter David DeVries
  • Patent number: 8091766
    Abstract: A solder ball loading apparatus for loading solder balls onto pads of a printed wiring board includes a holding device for holding a printed wiring board having pads and holding a ball array mask having of openings that correspond to pads of the printed wiring board, one or more cylinder members positioned over the holding device such that an opening portion of the cylinder member faces the holding device, the cylinder member gathering solder balls on the surface of the ball array mask under the cylinder member by suctioning air through the opening portion of the cylinder member, and a conveyor mechanism for moving the ball array mask and the printed wiring board relative to the cylinder member such that solder balls gathered under the opening portion of the cylinder member can be loaded onto the pads of the printed wiring board through the openings of the ball array mask held by the holding device.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: January 10, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Katsuhiko Tanno, Youichirou Kawamura
  • Patent number: 8042726
    Abstract: To form high performance bonding connections suitable for producing micro-structured components made of a plurality of individual layers, bonding by the steps; providing at least two work pieces; forming a metal bonding layer on at least one side of at least one of said at least two work pieces by chemical or electrolytic metal plating method; the metal bonding layer being a nickel/phosphorous alloy having a prescribed phosphorous content and prescribed thickness; forming a bonding arrangement comprising said work pieces so that there is at least one metal bonding layer between said at least two respective work pieces; heating at a prescribed heating rate to a temperature above the melting temperature of the bonding layer; bonding the two work pieces by applying contact pressure within a prescribed range; and cooling at a prescribed rate.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: October 25, 2011
    Assignee: Atotech Deutschland GmbH
    Inventors: Ralph Herber, Olaf Kurtz, Johannes Etzkorn, Christian Madry, Carsten Schwiekendick, Gerd Schafer
  • Patent number: 8002166
    Abstract: A method of manufacturing metal to glass, metal to metal and metal to ceramic connections to be used in SOFC applications, said connections being produced as a mixture of a base glass powder and a metal oxide powder. As a result, the inherent properties of the glass used in the composite seals may be altered locally in the metal-coating interface by adding e.g. MgO in order to control the viscosity and wetting, and at the same time maintain the bulk properties such as high coefficient of thermal expansion of the basic glass towards the seal components.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: August 23, 2011
    Assignee: Technical University of Denmark
    Inventors: Karsten Agersted Nielsen, Mette Solvang, Peter Halvor Larsen
  • Patent number: 7982320
    Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Semigear Inc.
    Inventors: Chunghsin Lee, Jian Zhang
  • Patent number: 7980448
    Abstract: A method of forming a bonded body comprised of a first base member, a second base member, and a first bonding film and a second bonding film provided between the first base member and the second base member is provided. The first bonding film and the second bonding film are constituted of copper and an organic component, and an amount of copper contained in each of the first bonding film and the second bonding film is 80 atom % or higher but lower than 90 atom % at an atomic ratio.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: July 19, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuru Sato, Takatoshi Yamamoto
  • Patent number: 7967185
    Abstract: A method of forming a bonded body comprised of a first base member, a second base member, and a first bonding film and a second bonding film provided between the first base member and the second base member is provided. The first bonding film and the second bonding film are constituted mainly of copper. The method is comprised of: forming the first bonding film on the first base member by using a chemical vapor-film formation method; forming the second bonding film on the second base member by using a chemical vapor-film formation method; bringing the first bonding film formed on the first base member into contact with the second bonding film formed on the second base member so that the first bonding film faces the second bonding film; and applying a compressive force to the first base member and the second base member so that the first bonding film and the second bonding film are bonded together to thereby obtain the bonded body.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuru Sato, Takatoshi Yamamoto
  • Patent number: 7963435
    Abstract: A method of forming a bonded body comprised of a first base member, a second base member, and a first bonding film and a second bonding film provided between the first base member and the second base member is provided. The first bonding film and the second bonding film are constituted of copper and an organic component, and an amount of copper contained in each of the first bonding film and the second bonding film is 90 atom % or higher but lower than 99 atom % at an atomic ratio.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: June 21, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuru Sato, Takatoshi Yamamoto
  • Publication number: 20110138621
    Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: an insulation layer including a first metal layer formed on one side or both sides thereof; a second metal layer formed on one side of the first metal layer; and a third metal layer formed on one side of the second metal layer, wherein the second metal layer has a lower melting point than the first metal layer or the third metal layer. The carrier is advantageous in that a build up layer can be separated from a carrier by heating, so that a routing process is not required, with the result that the size of a substrate does not change when the build up layer is separated from the carrier, thereby reusing the carrier and maintaining the compatibility between the substrate and manufacturing facilities.
    Type: Application
    Filed: March 9, 2010
    Publication date: June 16, 2011
    Inventors: Seong Min CHO, Keung Jin SOHN, Tae Kyun BAE, Hyun Jung HONG, Kyung Ah LEE, Chang Gun OH