Abstract: Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.

Abstract: A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.

Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Abstract: An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is realized without increasing the number of masks and the number of processes. In this display unit, a first wiring arranged between a semiconductor film and a substrate through a first insulating film is overlapped with this semiconductor film and is used as a light interrupting film. Further, a second insulating film used as a gate insulating film is formed on the semiconductor film. A gate electrode and a second wiring are formed on the second insulating film. The first and second wirings cross each other through the first and second insulating films. A third insulating film is formed as an interlayer insulating film on the second wiring, and a pixel electrode is formed on this third insulating film.

Abstract: A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The periphery region includes an utmost outer and an utmost inner periphery pairs. The utmost outer periphery pair has a difference between the second and the first impurity amounts, which is smaller than a maximum difference in the periphery region. The utmost inner periphery pair has a difference between the second and the first impurity amounts, which is larger than a difference in the center region.

Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.

Abstract: A multiple-layer serial diode cell and a nonvolatile memory device using the same enable reduction in the number of cell arrays by configuring cell arrays including a nonvolatile ferroelectric capacitor and a serial diode cell as multiple layers. In the nonvolatile memory device, a unit serial diode cell comprising a nonvolatile ferroelectric capacitor and a serial diode switch which does not require an additional gate control signal is positioned between a word line and a bit line, thereby embodying a cross point cell array, which is configured as a multiple layer to reduce the whole chip size.

Abstract: The present invention is directed to electronic devices comprising high-purity molybdenum oxide in at least a part of the devices. The devices according to the present such a bipolar transistor, a field effect transistor and a thyristor have a high withstand voltage. The present invention is directed also hostile-environment electron devices formed using high-purity molybdenum oxide. The devices according the present invention can be fabricated at a relatively lower temperature such as 700° C. than that at which GaN or SiC devices are fabricated, the at is a temperature higher than 1000° C.

Abstract: A semiconductor memory device includes a substrate having a semiconductor element formed thereon, an interlayer dielectric layer formed above the substrate, a plug formed in the interlayer dielectric layer, an adhesion layer formed in a region including a region above the plug, and a ferroelectric capacitor formed above the adhesion layer and having a lower electrode, a ferroelectric layer and an upper electrode, wherein an oxidized layer is formed in a part of the adhesion layer at a side wall thereof.

Abstract: Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor, whose drain is connected to the bit line of the device, and which is gated by a first word line. A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0.’ Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.

Abstract: The invention concerns a voltage-controlled triac-type component, formed in a N-type substrate (1) comprising first and second vertical thyristors (Th1, Th2), a first electrode (A2) of the first thyristor, on the front side of the component, corresponding to a first N-type region (6) formed in a first P-type box (5), the first box corresponding to a first electrode (A2) of the second thyristor, the first box containing a second N-type region (8); and a pilot structure comprising, above an extension of a second electrode region (4) of the second thyristor, a second P-type box (11) containing third and fourth N-type regions, the third region (12) and a portion of the second box (11) being connected to a gate terminal (G), the fourth region (13) being connected to the second region (8).

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Abstract: An apparatus and method for electrically connecting semi-conductor devices is disclosed. The apparatus and method employs a vacuum chamber and first and second semi-conductor components. The first and second semi-conductor components are coupled to a vacuum chamber and free space electron transmitters and receivers. The transmitters are configured to transmit a signals between the semi-conductor components.

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.

Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.

Abstract: A semiconductor device including a semiconductive body having formed therein an active region and a termination feature which includes spaced field rings disposed around the active region and diffusion rings of the same conductivity type as, but different conductivity than the semiconductive body formed between each pair of field rings.

Abstract: The invention concerns a pulsed bistable bidirectional electronic switch comprising a monolithic semiconductor circuit formed from a substrate (1) whereof the rear surface (A2) is coated with a metallization connected to earth. Said circuit comprises a vertical bidirectional switch (T1, T2) provided with a first gate terminal (M3), whereof the main electrode (A1) on the side of the front surface is connected to a load and an alternating current supply; a horizontal thyristor (T3) comprising an upper layer (4) of the vertical bidirectional switch, a first P-type region (11), and a second N-type region (12) formed in the first region; a second gate terminal (G1) connected to one of the first and second regions, the other being connected to earth. A capacitor (C) is connected to the first gate terminal (G3) and to the alternating current supply (VAC).

Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, the junction area between a base region and an adjacent emitter region of a thyristor is increased, relative to the junction area between other regions in the thyristor. In one implementation, the base region is formed extending on two sides of the emitter region. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure, with the base region having a first portion laterally adjacent to the emitter region and having a second portion between the emitter region and the buried insulator.

Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 ·D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.

Abstract: In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: An apparatus and method for electrically connecting semi-conductor devices is disclosed. The apparatus and method employs a vacuum chamber and first and second semi-conductor components. The first and second semi-conductor components are coupled to a vacuum chamber and free space electron transmitters and receivers. The transmitters are configured to transmit a signals between the semi-conductor components.

Abstract: A semiconductor chip package comprises a semiconductor chip with a metal layer formed over the backside surface thereof and a package body encapsulating the chip in a manner that the metal layer on the backside surface of the chip is exposed from the bottom surface of the package body. The package body has a plurality of protruding potions projecting from the bottom surface of the package body. A plurality of bonding wires each has one end electrically connected to the semiconductor chip and the other end exposed from one of the protruding portions of the package body for electrical coupling to an outside circuit. Preferably, the exposed end of each bonding wire has a longitudinal length at least four times larger than the diameter of the bonding wire. The present invention further provides manufacturing methods of the semiconductor chip package.

Abstract: In a Bi-CM0S ESD protection structure, the holding voltage is increased by a desired amount by including a NBL of chosen length. The positioning of the NBL may be adjusted to adjust the I-V characteristics of the structure. Dual voltage capabilities may be achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. Over and above the NBL position being adjusted relative to the p-regions, the two p-regions may vary in doping level, and dimensions to achieve different I-V characteristics for the device in the positive and negative directions.

Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.

Abstract: A thyristor for switching microwave signals includes semiconductor layers disposed on a substrate. A first surface of the thyristor defines an anode, and a second surface of the thyristor defines a cathode. The semiconductor layers include at least one semi-insulating layer. The thyristor transmits a microwave signal between the anode and the cathode in an ON state and blocks the microwave signal between the anode and the cathode in an OFF state.

Abstract: The invention concerns at diac comprising a highly-doped substrate (20) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity including in the neighbourhood of the substrate (20) a more highly-doped part (21), a highly-doped region (24) of the first type of conductivity on the side of the upper surface of the epitaxial layer, a region (23) of the second type of conductivity more doped than the epitaxial layer beneath the region (24) of the first type of conductivity and not overlapping relative thereto, a channel retaining ring (25) of the second type of conductivity more highly doped than the epitaxial layer, outside the first region, a wall (26) of the first type of conductivity outside said ring, joining the substrate.

Abstract: The invention concerns an asymmetric diac comprising a highly-doped substrate (21) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity on the upper surface of the substrate (21), a highly-doped region (24) of the first type of conductivity on the side of the upper surface of the epitaxial layer, a region (23) of the second type of conductivity more doped than the a epitaxial layer beneath the region (24) of the first type of conductivity and not overlapping relative thereto, a channel retaining ring (25) of the second type of conductivity more doped than the epitaxial layer, outside the first region, and a wall (26) of the first type of conductivity outside said ring, joining the substrate.

Abstract: An apparatus for switching microwave signals includes a plurality of input lines, a plurality of output lines; and a plurality of thyristors. Each thyristor has a lower conducting surface that is electrically connected to one of the input lines and an upper conducting surface that is electrically connected to one of the output lines. A selected thyristor transmits a microwave signal between a selected input line and a selected output line in an ON state and blocks the microwave signal between the selected input line and the selected output line in an OFF state.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: A semiconductor device includes a p type semiconductor substrate, a first n type region formed at the semiconductor substrate, a first n channel DMOS transistor formed in the first n type region, a second n type region formed at the semiconductor substrate, a vertical type pnp bipolar transistor formed in the second n type region, and a second n channel DMOS transistor formed in the second n type region. The first n channel DMOS transistor has a drain for receiving a high power supply voltage (Vdc) and a source for supplying an output voltage (Vout). The bipolar transistor has a base connected to the gate of the first n channel DMOS transistor, an emitter connected to the source of the first n channel DMOS transistor, and a collector connected to the ground. The second n channel DMOS transistor has a drain connected to the gate of the first n channel DMOS transistor and a source connected to the ground.

Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a n-type nitride semiconductor layer 11 and an p-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.

Abstract: A low voltage thyristor is disclosed that can be used to provide protection during electrostatic discharge event. The thyristor is connected between voltage reference nodes having a common potential, such as ground nodes, that are isolated from one another during normal operating conditions. During an ESD event on one of the voltage reference nodes, the low voltage thyrister triggers, at a voltage of less than ten volts, to help discharge the ESD current through the otherwise isolated ground node.

Abstract: There is provided is a semiconductor laser device capable of simplifying fabricating processes with a simple construction and easily mounting two semiconductor laser elements and a monitoring PD on a compact package and a wire bonding method for the semiconductor laser device. There are provided a stem 100 provided with a plurality of lead pins 121 through 124, a sub-mount 160 that is die-bonded onto the stem 100 and has its surface formed integrally with a monitoring PD 140 and two semiconductor laser elements 131 and 132 that are die-bonded onto the sub-mount 160 and have emission light monitored by the monitoring PD 140. A first bonding surface i.e. anode electrode 183 of the monitoring PD 140 and a second bonding surface i.e. end surface 123a of a lead pin 123 that is approximately perpendicular to the first bonding surface are wire-bonded to each other.

Abstract: An apparatus for switching microwave signals includes a plurality of input lines, a plurality of output lines; and a plurality of thyristors. Each thyristor has a lower conducting surface that is electrically connected to one of the input lines and an upper conducting surface that is electrically connected to one of the output lines. A selected thyristor transmits a microwave signal between a selected input line and a selected output line in an ON state and blocks the microwave signal between the selected input line and the selected output line in an OFF state.

Abstract: To make it possible to control turn-off operation even after switch over to transistor operation after commutation of the main current from cathode electrode to gate electrode in turn-off operation, a semiconductor device according to the invention comprises a first electrode, a first region of first conduction type provided on the first electrode, a second region of second conduction type provided on the first region, a third region and a fourth region of first conduction type respectively provided on the second region with a predetermined distance from each other to allow formation of a channel region on the second region, a fifth region of second conduction type provided on the third region, a second electrode provided on the fifth region, a gate electrode established in contact with the fourth region and a control electrode provided on a separate region between the third and fourth regions on the second region to control the channel region through an insulation layer.

Abstract: A gate turn-off thyristor includes a substrate formed of n-type silicon carbide; a growth buffer formed of n-type silicon carbide and positioned to overlie said substrate; a field buffer region formed of p-type silicon carbide and positioned to overlie said growth buffer; a drift region formed of p-type silicon carbide and positioned to overlie said field buffer region; a gated base region formed of n-type silicon carbide and positioned to overlie said drift region; a modified anode region formed of first, second and third layers of silicon carbide and positioned to overlie said gated base region, said first layer comprising p-type silicon carbide and disposed adjacent said gated base region, said second layer comprising n-type silicon carbide and disposed adjacent said first layer, said third layer comprising p-type silicon carbide and disposed adjacent said second layer; an anode contact disposed on said third layer of said modified anode region; a cathode contact disposed on said substrate; and a gate cont

Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

Abstract: An apparatus for switching microwave signals includes a plurality of input lines, a plurality of output lines; and a plurality of thyristors. Each thyristor has a lower conducting surface that is electrically connected to one of the input lines and an upper conducting surface that is electrically connected to one of the output lines. A selected thyristor transmits a microwave signal between a selected input line and a selected output line in an ON state and blocks the microwave signal between the selected input line and the selected output line in an OFF state.

Abstract: The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer (60). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction (54) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region (64) extending from the top surface into the control layer (60). A conductive tub region (62), spaced apart from the top conductive region (64), extends from the top surface at least through the control layer (60). A field effect region (80) is disposed in the control layer (60) between the top conductive region (64) and tub region (62). A gate contact (18) is formed over the field effect region (80) causing the creation and interruption of a conductive channel (82) between the top conductive region (64) and conductive tub region (62) so as to turn the device on and off.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: A switching device is described having a semiconductor substrate with a front side and a back side. The switching device includes a first transistor which includes a first region adjacent the front side, a second region within the first region, the semiconductor substrate, and at least one island region adjacent the backside. The switching device also includes a second transistor which includes the first region, the second region, the semiconductor substrate, and a third region coupled to the at least one island region.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. A layer of the top surface forms a control layer. A semiconductor layer junction, remote from top and bottom device surfaces, forms a blocking p-n junction capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region extending from the top surface into the control layer. A conductive tub region, spaced apart from the top conductive region, extends from the top surface at least through the control layer. A field effect region is disposed in the control layer between the top conductive region and tub region. A gate contact is formed over the field effect region causing the creation and interruption of a conductive channel between the top conductive region and the conductive tub region so as to turn the device on and off.