More Than Four Semiconductor Layers Of Alternating Conductivity Types (e.g., Pnpnpn Structure, 5 Layer Bidirectional Diacs, Etc.) Patents (Class 257/110)
  • Patent number: 10971623
    Abstract: A semiconductor device includes a semiconductor body, first and second electrodes and a control electrode. The semiconductor body is positioned between the first and second electrodes. The control electrode is provided between the semiconductor body and the first electrode. The semiconductor body includes a first layer of a first conductivity-type and a second layer of a second conductivity-type alternately arranged along the first electrode. The first and second layers include first and second low-concentration portions, respectively. The first low-concentration portion has a first conductivity-type impurity concentration lower than that in other portion of the first layer. The second low-concentration portion has a second conductivity-type impurity concentration lower than that in other portion of the second layer. The first low-concentration portion is positioned at a level same as a level of the second low-concentration portion in a direction directed toward the first electrode from the second electrode.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: April 6, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Takuo Kikuchi
  • Patent number: 10825858
    Abstract: In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 3, 2020
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Yasushi Tateshita, Kazunobu Ota
  • Patent number: 10661383
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: May 26, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Jungrae Park, Ajay Kumar, Brad Eaton
  • Patent number: 10622347
    Abstract: An electrostatic discharge protection (ESD) structure for protecting a core circuit of an integrated circuit from an ESD event received by a conductive pad of the integrated circuit is provided. The ESD protection structure includes a first conductive layer, a clamp device, a first electrical connection part and a second electrical connection part. The first conductive layer is formed below the conductive pad, and includes a first conductive portion, an insulating portion and a second conductive portion. The insulating portion is surrounded by the first conductive portion and the second conductive portion. The first conductive portion is electrically connected between the conductive pad and the second conductive portion. The clamp device is arranged for clamping the ESD event. The first electrical connection part is coupled between the first conductive portion and the clamp device. The second electrical connection part is coupled between the second conductive portion and the core circuit.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 14, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Yi Chen, Ching-Ling Tsai
  • Patent number: 10424640
    Abstract: A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm?3 and not higher than 5×1022 cm?3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 24, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima, Johji Nishio, Teruyuki Ohashi
  • Patent number: 10256307
    Abstract: A semiconductor device is provided. The semiconductor device includes a first doped region and a second doped region of a first conductive type and a third doped region of a second conductive type located in a substrate. The second doped region is located at a side of the first doped region. A top-view pattern of the second doped region has at least one recess portion. The third doped region is located between the first doped region and the second doped region. A top-view pattern of the third doped region has at least one protruded portion corresponding to the at least one recess portion.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 9, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yu-Chin Chien, Ching-Lin Chan, Cheng-Chi Lin
  • Patent number: 9876072
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 23, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 9853420
    Abstract: A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 26, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Mathew Schmidt, Christiane Poblenz
  • Patent number: 9786736
    Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa
  • Patent number: 9722047
    Abstract: The high-voltage transistor device comprises a semiconductor substrate (1) with a source region (2) of a first type of electrical conductivity, a body region (3) including a channel region (4) of a second type of electrical conductivity opposite to the first type of conductivity, a drift region (5) of the first type of conductivity, and a drain region (6) of the first type of conductivity extending longitudinally in striplike fashion from the channel region (4) to the drain region (6) and laterally confined by isolation regions (9). The drift region (5) comprises a doping of the first type of conductivity and includes an additional region (8) with a net doping of the second type of conductivity to adjust the electrical properties of the drift region (5). The drift region depth and the additional region depth do not exceed the maximal depth (17) of the isolation regions (9).
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 1, 2017
    Assignee: AMS AG
    Inventor: Martin Knaipp
  • Patent number: 9472545
    Abstract: One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Hui Chen, Wei Yu Ma, Kuo-Ji Chen
  • Patent number: 9356134
    Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 31, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 9343568
    Abstract: Provided is a semiconductor device including a metal oxide semiconductor transistor, a Zener diode, and a resistor. The metal oxide semiconductor transistor includes a gate, a source and a drain. The resistor has one end electrically connected to the drain, wherein the resistor includes a high resistance which is sufficient for flowing most of current to pass the metal oxide semiconductor transistor. The Zener diode includes a cathode and an anode, in which the cathode is electrically connected the gate and another end of the resistor, and the anode is electrically connected to a gate body.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 17, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Wing-Chor Chan
  • Patent number: 9343459
    Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 17, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 9129806
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: September 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Rouying Zhan, Chai Ean Gill, Wen-Yi Chen, Michael H. Kaneshiro
  • Patent number: 9064840
    Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 23, 2015
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Patent number: 8946766
    Abstract: Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 8906714
    Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 8901661
    Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers
  • Publication number: 20140346560
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Inventors: Rouying ZHAN, Chai Ean GILL, Wen-Yi CHEN, Michael H. KANESHIRO
  • Patent number: 8860078
    Abstract: An electronic or electro-optic device includes a p-type semiconductor layer, an n-type semiconductor layer having a region of contact with the p-type semiconductor layer to provide a p-n junction, a first electrical lead in electrical connection with the p-type semiconductor layer, and a second electrical lead in electrical connection with the n-type semiconductor layer. At least one of the p-type and n-type semiconductor layers includes a doped topological-insulator material having an electrically conducting surface, and one of the first and second electrical leads is electrically connected to the electrically conducting surface of the topological-insulator material.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 14, 2014
    Assignee: The Johns Hopkins University
    Inventors: Tyrel M. McQueen, Patrick Cottingham, John P. Sheckelton, Kathryn Arpino
  • Patent number: 8841696
    Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jam-Wem Lee, Yi-Feng Chang
  • Patent number: 8829491
    Abstract: According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-won Lee, Jun-youn Kim, Young-jo Tak
  • Patent number: 8772880
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Publication number: 20140061716
    Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Rouying Zhan, Chai Ean c. Gill, Changsoo Hong
  • Patent number: 8664690
    Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8654537
    Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: February 18, 2014
    Assignee: Apple Inc.
    Inventors: Joseph Fisher, Jr., Sean Mayo, Dennis R. Pyper, Paul Nangeroni, Jose Mantovani
  • Patent number: 8592881
    Abstract: An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-gyu Lee, Byoung-deog Choi, Hye-hyang Park, Ki-ju Im
  • Patent number: 8587027
    Abstract: A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 3 and 7, undoped AlGaAs spacer layers 4 and 6, and an undoped InGaAs channel layer 5) formed above a semi-insulating GaAs substrate, an upper semiconductor layer made up of at least one semiconductor layer and formed above the channel layer of the first conductivity type, a semiconductor layer of a second conductivity type (C-doped p+-GaAs layer 18) formed in a recess made in the upper semiconductor layer or formed above the upper semiconductor layer, a gate electrode placed above and in contact with the semiconductor layer of the second conductivity type, and a gate insulating film including a nitride film formed above and in contact with the upper semiconductor layer and an oxide film formed above the nitride film and having a larger thickness than the nitride film.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasunori Bito
  • Patent number: 8564047
    Abstract: A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8519431
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Patent number: 8482029
    Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body also includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 9, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers
  • Patent number: 8476673
    Abstract: A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: July 2, 2013
    Assignee: DENSO CORPORATION
    Inventors: Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Shinya Sakurai, Takashi Suzuki
  • Patent number: 8395204
    Abstract: According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: March 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Kawaguchi
  • Patent number: 8330184
    Abstract: In one embodiment, a bidirectional voltage-regulator diode includes first to fifth semiconductor layers formed on an inner surface of a first recess formed in a semiconductor substrate of an N-type in the order. The first semiconductor layer of the N-type has a first impurity concentration lower than an impurity concentration of the semiconductor substrate. The second semiconductor layer of a P-type has a second impurity concentration. The third semiconductor layer of the P-type has a third impurity concentration higher than the second impurity concentration. The fourth semiconductor layer of the P-type has a fourth impurity concentration lower than the third impurity concentration. The fifth semiconductor layer of the N-type has a fifth impurity concentration.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 11, 2012
    Assignee: Kabushiki kaisha Toshiba
    Inventor: Tetsuro Nozu
  • Patent number: 8330198
    Abstract: A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: December 11, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Shin Bin Huang, Chung-Lin Huang, Ching-Nan Hsiao, Tzung Han Lee
  • Patent number: 8212320
    Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: July 3, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 8049250
    Abstract: Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsiang Song, Jam-Wem Lee
  • Patent number: 8049247
    Abstract: The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: November 1, 2011
    Assignee: Amazing Microelectronic Corp.
    Inventors: Tang-Kuei Tseng, Che-Hao Chuang, Ryan Hsin-Chin Jiang, Ming-Dou Ker
  • Patent number: 8035115
    Abstract: A semiconductor apparatus includes a substrate; and a plurality of semiconductor thin films formed on said substrate, each of said semiconductor thin films having a pn-junction, and electrodes of p-type and n-type for injecting carriers to the pn-junction, wherein said semiconductor thin films are formed so that all or a part of said pn-junctions are connected serially. As different from a semiconductor thin film constituted of a single pn-junction, the light emission with the invented semiconductor apparatus is the summation of the light emission intensities of the entire pn-junctions, so that the light emitting intensity can be increased largely.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: October 11, 2011
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Takahito Suzuki, Hiroshi Kurokawa, Taishi Kaneto
  • Patent number: 7936020
    Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: May 3, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 7859010
    Abstract: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity type is formed in the first anode region. A first semiconductor region of the first conductivity type is formed in contact with the semiconductor substrate. A second semiconductor region of the second conductivity type is formed adjacent to the first semiconductor region and in contact with the cathode layer. An intermediate electrode is formed on the surfaces of the first semiconductor region and the contact region.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoki Inoue
  • Patent number: 7804150
    Abstract: A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 28, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chang-ki Jeon, Gary Dolny
  • Patent number: 7786504
    Abstract: The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semico
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: August 31, 2010
    Assignee: Amazing Microelectronic Corp.
    Inventors: Wen-Yi Chen, Ryan Hsin-Chin Jiang, Ming-Dou Ker
  • Patent number: 7700970
    Abstract: An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignees: STMicroelectronics S.r.l., STMicroelectronics S.A.
    Inventors: Mario Giuseppe Saggio, Antonino Longo Minnolo, Rosalia Germana'
  • Patent number: 7659140
    Abstract: An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee, BoHan Yoon
  • Patent number: 7554155
    Abstract: A power semiconductor device has a first main electrode formed along a surface of a substrate, a first semiconductor layer of first conductive type electrically connected to the first main electrode, a cyclic structure section which is formed on the first semiconductor layer and has second semiconductor layers of first conductive type and third semiconductor layers of second conductive type alternately and cyclically formed along the surface of the substrate, a fourth semiconductor layer of second conductive type selectively formed on a part of the second and third semiconductor layers, a fifth semiconductor layer of first conductive type selectively formed on the fourth semiconductor layer, a second main electrode contacted the fourth and fifth semiconductor layers, a control electrode disposed adjacent via a first insulating film on the second, fourth and fifth semiconductor layers, and a depletion layer blocking section which is formed outside of the cyclic structure section and prevents a depletion layer
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: June 30, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura
  • Patent number: 7511316
    Abstract: A semiconductor device is provided which comprises a periphery region 23a extending downward from a third semiconducting region 23, enveloping an outer surfaces 21a and 22b of first and second semiconducting regions 21 and 22. A PN junctions is formed between second and third semiconducting regions 22, 23 inside of periphery region 23a perfectly away from side surfaces 28 of semiconductor substrate 27 to exert no adverse effect on breakdown by crystal defect in and foreign matters attached to side surfaces of semiconductor substrate 27. As periphery region 23a has the thinner diffusion concentration of impurity with the deeper area of periphery region 23a to widely spread depletion layer on boundary of the periphery region 23a with increase electric resistance.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: March 31, 2009
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Hideyuki Andoh
  • Publication number: 20090032837
    Abstract: The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.
    Type: Application
    Filed: May 1, 2008
    Publication date: February 5, 2009
    Inventors: Tang-Kuei Tseng, Che-Hao Chuang, Ryan Hsin-Chin Jiang, Ming-Dou Ker
  • Patent number: 7452787
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata