Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.

Abstract: A light emitting diode with strained layer superlatices (SLS) crystal structure is formed on a substrate. A nucleation layer and a buffer layer are sequentially formed on the substrate, so as to ease the crystal growth for the subsequent crystal growing process. An active layer is covered between an upper and a lower cladding layers. The active later include III-N group compound semiconductive material. A SLS contact layer is located on the upper cladding layer. A transparent electrode is located on the contact later to serve as an anode. Another electrode layer has contact with the buffer layer, and is separated from the lower and upper cladding layers.

Abstract: A method of forming an avalanche trench optical detector device on a semiconductor substrate, comprising forming a first set and a second set of trenches in the substrate, wherein trenches of the first set are alternately disposed with respect to trenches of the second set, filling the trenches with a doped sacrificial material, and annealing the device to form a multiplication region in the substrate. The method comprises etching the doped sacrificial material from the first set of trenches, filling the first set of trenches with a doped material of a first conductivity, etching the doped sacrificial material from a second set of trenches, and filling the second set of trenches with a doped material of a second conductivity. The method further comprises providing separate wiring connections to the first set of trenches and the second set of trenches.

Abstract: Methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment and semiconductor device packages formed in accordance with such methods. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The method provides increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.

Abstract: A surface light-emitting element having improved external light emission efficiency and a self-scanning light-emitting device using this surface light-emitting element are provided. To improve external light-emission efficiency, the light-emitting center is shifted to an area where there is no light shielding layer thereon. When the surface light-emitting element is a surface light-emitting thyristor of the PNPN structure, it is necessary to have such a construction that part of the injected current is prevented from flowing toward the gate electrode to improve external light emission efficiency. The self-scanning light-emitting device of this invention is accomplished by using this type of surface light-emitting element.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: An optical trigger thyristor having a light receiving portion 8 constructed of an n-type base layer front surface portion 5, a p-type semiconductor region 6, and a p-type front surface layer 7. The p-type front surface layer 7 is disposed so that it connects the front surfaces of the p-type semiconductor region 6 and a p-type base layer 3 and covers the exposed surface of the n-type base layer front surface portion 5. As a result, the n-type base layer front surface portion, which tends to be easily contaminated, is covered by the p-type front surface layer. Thus, contamination of the n-type base layer front surface is prevented. Consequently, the concentration of impurities in the front surface portion of the n-type base layer does not vary. Thus, there is high arc sensitivity without deterioration of the voltage blocking characteristic.

Abstract: An optically-triggered silicon controlled rectifier (SCR) (21) having a number of semiconductor layers (23, 24, 31) diffused into an N type substrate (22). Specifically, the SCR is formed by diffusing a first P+ layer (23) into an upper surface of the substrate. Then, an N+ layer (24) is diffused into a portion of an upper surface of the first P+ layer. An oxide layer (25) which is permeable to optical radiation is formed on the first P+ layer. A conductive cathode terminal (26) is then deposited on the N+ layer. Therefore, a trench (30) is etched in the lower surface of the substrate. The trench is defined by a depth and a surface. A second P+ layer (31) is diffused into the surface of the trench. The depth of the trench substantially defines a spacing between the first and second P+ layers. The chip is soldered onto a pedestal (33) formed on a lead frame (34). The solder is deposited in the trench and contacts the second P+ layer to form an anode terminal (36).

Abstract: A serial arrangement of photosensitive components of the planar-type has a first main surface on which a first photosensitive junction appears at the surface and a second main surface. The components are piled so that the second main surface of a component contacts the first main surface of the adjacent component. The second main surface of each component has a notch at its periphery along a lateral length corresponding at least to the distance between the photosensistive junction and the periphery.

Abstract: An object of the present invention is to enhance the transmission efficiency of light signals. An output end of a light guide is coupled to a light receiving portion of a semiconductor substrate with an optical coupling agent. Reflection preventing films of silicon dioxide are formed on both the output end and the input end of the light guide. Similar reflection preventing films are formed on both surfaces of a light introducing window provided at the input end of the light guide, too. The light introducing window is provided to maintain the inside of the device airtight while enabling passage of light signals. Since the reflection preventing films are formed, the transmission efficiency of light signals is high, so that the sensitivity of the device increases.

Abstract: A semiconductor package includes a semiconductor chip, an interconnection substrate having the semiconductor chip mounted on one surface of the interconnection substrate, and a package base having the interconnection substrate mounted on one surface of the package base. An optical transmission medium is provided on the package base at a location corresponding to an optical device provided on the interconnection substrate. On the other surface of the package base is provided a receptacle for making an optical connection between an optical fiber cable and the optical transmission medium. Signals are input and/or output via the optical fiber cable connected to the receptacle.

Abstract: Optoelectronic semiconductor devices which have a groove-shaped waveguide in an oxide layer provided on a silicon substrate are compact, easy to manufacture, and--when the waveguide comprises a non-linear optical material--applicable inter alia for frequency doubling of laser radiation. In known devices, scattering losses occur in the waveguide owing to the roughness of the groove which arises during etching of the groove. Here, the groove and a portion of the oxide layer are formed by local, preferably thermal, oxidation of the silicon substrate. The groove formed at the area of the oxidation mask has a smoother surface and as a result the waveguide has lower losses. When the device includes a GaAs/AlGaAs diode laser, it forms an efficient, compact, inexpensive and blue-emitting laser source which is suitable for use in an optical disc system. Preferably, the diode laser is situated in a deeper and wider further groove in the oxide layer.