Abstract: The present invention relates to minimizing a leakage current in a floating island region formed in a thin film transistor, and to maintaining a large ON-current required for an operation of the TFT. More specifically, the present invention is directed to a thin film transistor includes: a gate electrode 18 disposed above an insulating substrate and formed in a predetermined pattern; an a-Si film 16 formed in accordance with the pattern of the gate electrode 18; a source electrode 14 formed via the a-Si film 16; and a drain electrode 15 disposed at a predetermined interval from the source electrode 14.

Abstract: A thyristor includes a semiconductor body having a first emitter layer and a first base layer on an anode side, a second base layer and a second emitter layer on a cathode side, a cathode contact, and an electrically insulating insulation layer having openings. The insulation layer is disposed between the second emitter layer and the cathode contact. The openings have dimensions and spacings making the insulation layer form an electrical resistor for reducing current filamentation. A series resistor is incorporated on the cathode side and is formed by the pierced insulation layer between the cathode side metallizing, forming the terminal contact, and the doped semiconductor material of the emitter on the cathode side. The openings are preferably cylindrical. In a silicon component element, the insulation layer preferably is SiO2 or Si3N4, or a layered succession of SiO2 and Si3N4.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: The present invention is directed to a micro electromechanical system (MEMS) relay having a movable actuator member part that moves laterally in a wafer surface recess into contact with a power terminal. In a preferred embodiment, the movable actuator member is a planar single body comprised of two flat intersecting flexible “S” shaped portions when seen in plan view. A power terminal makes contact with the middle part of one “S”, where it intersects with the other “S”. A pair of electrostatic electrodes are located at each end of the one “S”, to respectively move the middle part of that “S” into and away from contact with a power terminal in the recess. The other “S” serves as a flexible connection to the middle part of the other “S”. Means are provided to electrically isolate the ends of the first “S from its middle part.

Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.

Abstract: A switched variable capacitor (20), and binary-weighted array (40) of such capacitors (20), are disclosed. The switched variable capacitor (20) includes a switching transistor (14) connected in series with first and second capacitors (12), between the two terminals (A,B). Bias transistors (18) are provided, and of opposite conductivity type as the switching transistor (14) but with their gates connected to the gate of the switching transistor (14). The bias transistors (18), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (14), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (20). A binary-weighted array (40) of switched variable capacitors (20) is also disclosed, as is a voltage-controlled oscillator (50) incorporating such an array (40).

Abstract: A monolithic power switch with a controlled di/dt including the parallel assembly of a MOS or IGBT type component with a thyristor type component, including means for inhibiting the thyristor type component during the closing phase of the switch, which is ensured by the IGBT type component. The IGBT type component has a vertical multicell structure and the component of thyristor type has a vertical monocell structure.

Abstract: A thyris a thyristor is provided in which a lifetime of a minority carrier is controlled to improve the trade-off relationship between an ON-state voltage and a turn-off time and attain a high frequency and a low loss. Shielding members formed of metal plates are provided respectively in spaces above a plane on which a cathode electrode is provided and a plane on which an anode electrode is provided.

Abstract: A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

Abstract: A semiconductor device having a dielectric isolation (DI) structure using an SOI substrate or the like. An active region as a main current path of the semiconductor device is sandwiched between DI grooves having a side wall substantially vertical to the main surface of the substrate, and the width W of the main current path between the DI grooves is set to 5 .mu.m or narrower to reduce excessive carriers. The reverse recovery charge Q.sub.rr prolonging the turn-off time can be shortened, which enables high speed switching.

Abstract: In a semiconductor device having a low ON resistance, an n.sup.- -type epitaxial layer (1) is formed on an upper surface of an n.sup.+ -type substrate (8) and p-type diffusion regions (2) are selectively formed on its upper surface, while n-type diffusion regions (3) are further formed on upper surfaces thereof. A gate electrode (5) wrapped up in an oxide film (4) is provided on the upper surface of the n.sup.- -type epitaxial layer (1) and above portions of the p-type diffusion regions (2) held between the n.sup.- -type epitaxial layer (1) and the n.sup.+ -type diffusion regions (3). Grooves (9) are formed in the upper surface of the n.sup.- -type epitaxial layer (1) located under a gate electrode (5) to extend perpendicularly to junction planes between the n.sup.- -type epitaxial layer (1) and the p-type diffusion regions (2).

Abstract: An overvoltage protection device having multiple shorting dots in the emitter region and multiple buried regions substantially aligned with these shorting dots. The placement, number, and area of these buried regions reduce and more accurately set the overshoot voltage value of the device while maintaining the high surge capacities of the device. Further, doping types and concentrations have been modified from that known in the prior art to reduce overshoot providing a more accurate and sensitive overvoltage protection device than that known previously in the prior art.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: A voltage controlled thyristor includes an intrinsic layer of material between an anode and a cathode and a gate region between the intrinsic layer and the cathode comprising a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode. In a preferred embodiment, interdigitated ohmic contacts are formed on one surface to the N doped cathode regions and the P doped regions of the control gate. In a preferred embodiment, the anode and cathode emitters have a porous construction in which a lightly doped layer or region has a more heavily doped region or regions therein.

Abstract: In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting. The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting. One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter.

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract: Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.