Abstract: A bidirectional switch element includes: a substrate; an AlzGa1-zN layer; an AlbGa1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Alx1Ga1-x1N layer; a p-type Alx2Ga1-x2N layer; an AlyGa1-yN layer; and an AlwGa1-wN layer. The AlzGa1-zN layer is formed over the substrate. The AlbGa1-bN layer is formed on the AlzGa1-zN layer. The AlyGa1-yN layer is interposed between the substrate and the AlzGa1-zN layer. The AlwGa1-wN layer is interposed between the substrate and the AlyGa1-yN layer and has a higher C concentration than the AlyGa1-yN layer.

Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.

Abstract: In an example, a semiconductor device includes an insulated gate transistor cell, a first region (e.g., a drain region and/or a drift region), a cathode region, a second region (e.g., an anode region and/or a separation region), and a source electrode. The insulated gate transistor cell includes a source region and a gate electrode. The source region and the cathode region are in a silicon carbide body. The gate electrode and the cathode region are electrically connected. The cathode region, the source region, and the first region have a first conductivity type. The second region has a second conductivity type and is between the cathode region and the first region. The source electrode and the source region are electrically connected. The source electrode and the second region are in contact with each other. A rectifying junction is electrically coupled between the source electrode and the cathode region.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: Disclosed herein is a method comprising: forming a first electrically conductive layer on a first surface of a substrate of semiconductor, wherein the first electrically conductive layer is in electrical contact with the semiconductor; bonding, at the first electrically conductive layer, a support wafer to the substrate of semiconductor; thinning the substrate of semiconductor.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.

Abstract: A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Abstract: An RC IGBT includes, in an active region, an IGBT section and at least three diode sections. The arrangement of the diode sections obeys a design rule.

Abstract: Provided is a semiconductor device having improved breakdown resistance during recovery operation. A semiconductor device according to the present application is a semiconductor device in which an insulated gate bipolar transistor region and a diode region are provided adjacent to each other. The insulated gate bipolar transistor region includes an emitter layer having a short-side direction in a first direction in a plan view. The diode region includes carrier injection suppression layer having a short-side direction in a second direction in a plan view. In a plan view, a width of the carrier injection suppression layer in the second direction is smaller than a width of the emitter layer in the first direction.

Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically

Abstract: A semiconductor device is proposed. The semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. Methods of manufacturing the semiconductor device are also proposed.

Abstract: A semiconductor module includes: semiconductor devices; a resin mold that integrally seals the semiconductor devices; and external terminals that are disposed at a lateral side of the resin mold along a direction perpendicular to a thickness direction of the semiconductor devices. Each semiconductor device includes an insulated gate semiconductor device having a gate electrode, a first electrode, and a second electrode. In the insulated gate semiconductor device, carriers move from the first electrode to the second electrode through a channel provided by a voltage applied to the gate electrode. The external terminals include: a gate terminal electrically connected to the gate electrode; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode. The gate terminal and the second terminal, which are electrically connected to an identical semiconductor device, are not adjacent to each other.

Abstract: A power semiconductor device includes: a semiconductor body; a first load terminal structure coupled to the body front side and a second load terminal structure coupled to the body backside; an active area for conducting a load current between the load terminal structures; a drift region having a first conductivity type; a backside region arranged at the backside and including, inside the active area, first and second backside emitter zones. At least one of the backside emitter zones includes: first sectors each having at least one first region of a second conductivity type, the first region arranged in contact with the second load terminal structure and having a smallest lateral extension of at most 50 ?m; and/or second sectors each having a second region of the second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 ?m.

Abstract: The present disclosure relates to an electronic apparatus. The electronic apparatus includes a base substrate through which a hole is defined, a cover portion, a first sensing electrode, a second sensing electrode, a dummy electrode, and a ground line. The cover portion surrounds the hole and includes at least one cover pattern. The first sensing electrode includes first sensing patterns. The second sensing electrode includes second sensing patterns. The dummy electrode includes dummy patterns disposed between the first sensing patterns and the second sensing patterns. The ground line is electrically connected to the cover portion through at least some of the dummy patterns.

Abstract: The electrostatic discharge (ESD) protection apparatus includes a first well, a second well, a first doping region, and a second doping region. The first well is disposed in a substrate having a first conductivity type, wherein the first well has a second conductivity type and the substrate is electrically connected to a first pad. The second well is disposed in the first well, wherein the second well has the first conductivity type. The first doping region is disposed in the second well, wherein the first doping region has the second conductivity type, and the first doping region is electrically connected to a second pad. The second doping region is disposed in the second well, wherein the second doping region has the first conductivity type.

Abstract: A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

Abstract: An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.

Abstract: A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.

Abstract: A semiconductor device according to the present invention includes a substrate having an IGBT region, a diode region, and a high resistance region between the IGBT region and the diode region, a first electrode provided on an upper surface of the substrate and a second electrode provided on a back surface as a surface on an opposite side to the upper surface of the substrate, wherein in the high resistance region, a contact resistance between the upper surface of the substrate and the first electrode or a contact resistance between the back surface of the substrate and the second electrode is higher than in the diode region, and a width of the high resistance region is equal to or greater than a thickness of the substrate.

Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.

Abstract: There are provided a small-sized power semiconductor module and a small-sized power conversion device capable of reducing ringing voltage. A power semiconductor module includes: a positive electrode-side switching element and a positive electrode-side freewheeling diode corresponding to a positive electrode-side power semiconductor element; a negative electrode-side switching element and a negative electrode-side freewheeling diode corresponding to a negative electrode-side power semiconductor element; a positive electrode conductor pattern; a negative electrode conductor pattern; an AC electrode pattern; and a snubber substrate including an insulating substrate having a snubber circuit formed thereon. The snubber substrate includes the insulating substrate and the at least one snubber circuit arranged on the insulating substrate. The snubber substrate is arranged on at least one of the positive electrode conductor pattern, the negative electrode conductor pattern and the AC electrode pattern.

Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.

Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

Abstract: An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

Abstract: A semiconductor device includes a semiconductor layer. The semiconductor layer has bottom and upper surfaces opposite to each other in a first direction. The semiconductor layer includes a first region of a first conductivity type at the bottom surface, a second region of the first conductivity type at the bottom surface surrounding the first region, a third region of the first conductivity type above the first and second regions, and a fourth region of a second conductivity type extending from the upper surface into the third region. In a first cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a first distance. In a second cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a second distance.

Abstract: A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer.

Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

Abstract: The invention provides an inexpensive flywheel diode having a low power loss. A semiconductor substrate side of a gate electrode provided on a surface of an anode electrode side of a semiconductor substrate including silicon is surrounded by a p layer, an n layer, and a p layer via a gate insulating film. The anode electrode is in contact with the p layer with a low resistance, and is also in contact with the n layer or the p layer, and a Schottky diode is formed between the anode electrode and the n layer or the p layer.

Abstract: A semiconductor device is provided, which includes a semiconductor substrate, a transistor section and a diode section. Each of the transistor and diode sections includes a plurality of trench parts, an insulating portion formed on an inner wall of each trench part, a conductive portion provided in each trench part, a plurality of mesa parts, an interlayer dielectric film having contact holes, and a first electrode in contact with the mesa parts via the contact holes. The mesa parts in the transistor section include T-side mesa parts arranged closest to the diode section, the mesa parts in the diode section include D-side mesa parts arranged closest to the transistor section, and a maximum mesa width of mesa parts electrically connected to the first electrode in the transistor section is greater than both a mesa width of the T-side mesa parts and a mesa width of the D-side mesa parts.

Abstract: An object of the present invention is to suppress reduction in a temperature cycle life of a wiring in a two-in-one type chopper module. A two-in-one type chopper module according to the present invention includes: a switching transistor; a first diode inverse-parallelly connected to the switching transistor; a second diode serially connected to the switching transistor and the first diode; a first wiring pattern mounting the switching transistor and the first diode; and a second wiring pattern mounting the second diode, wherein each of the switching transistor and the first diode has a power loss substantially identical with each other at a time of a forward direction current conduction, and an effective area of the second diode is larger than an effective area of the first diode.

Abstract: The present invention provides an ESD protection device with the mechanism of punch through to achieve low trigger voltage. At the same time, the structure of ESD protection device includes parasitic NPN and parasitic PNP. Parasitic NPN and parasitic PNP will form a silicon controlled rectifier (SCR) device with snapback behavior to increase the protection capability of ESD protection device.

Abstract: A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n? drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

Abstract: A semiconductor device includes a single semiconductor substrate on which an IGBT region including an IGBT element and an FWD region including a FWD element are formed. In the semiconductor device, a cathode layer is formed with a carrier injection layer, which is electrically connected to a second electrode and has a PN junction with a field stop layer. When a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current is flowing through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer.

Abstract: Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material.

Abstract: Provided is a semiconductor device including a semiconductor substrate having a drift region; a transistor portion having a collector region; a diode portion having a cathode region; and a boundary portion arranged between the transistor portion and the diode portion at an upper surface of the semiconductor substrate, and having the collector region, wherein the mesa portion of each of the transistor portion and the boundary portion has an emitter region and a base region, the base region has a channel portion, and a density in the upper surface of the mesa portion in the region in which the channel portion is projected onto the upper surface of the mesa portion of the boundary portion may be smaller than the density of the region in which the channel portion is projected onto the upper surface of the mesa portion of the transistor portion.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.

Abstract: A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.

Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.

Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first recess is located between the drain structure and the gate structure.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes: an n-type semiconductor substrate having a cell region and a termination region provided around the cell region; a p-type anode layer provided on an upper surface of the n-type semiconductor substrate in the cell region; an n-type buffer layer provided on a lower surface of the n-type semiconductor substrate; and a p-type layer provided on the lower surface of the n-type buffer layer in the termination region and deeper than the n-type buffer layer.

Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.

Abstract: To provide a semiconductor device, wherein each of a transistor portion and a diode portion that are arrayed along an array direction has: a second-conductivity type base region provided above a first-conductivity type drift region inside a semiconductor substrate; a plurality of trench portions that penetrate the base region from an upper surface of the semiconductor substrate, extend at the upper surface of the semiconductor substrate and in a direction of extension perpendicular to the array direction, and have conductive portions provided therein; and a lower-surface side lifetime control region that lies on a lower-surface side in the semiconductor substrate, and from the transistor portion to the diode portion, and includes a lifetime killer. In the array direction, the transistor portion may have a portion provided with the lower-surface side lifetime control region, and another portion not provided with the lower-surface side lifetime control region.

Abstract: An insulated gate field effect bipolar transistor (IGFEBT) includes a substrate, a deep well (DW) region, a first conductivity type well region, a gate structure, a source region and a drain region located on the first conductivity type well region at both sides of the gate structure, an anode, and a cathode. The source region includes a first doped region and a second doped region between the first doped region and the gate structure, and the drain region includes a third doped region and a fourth doped region formed on the third doped region. The substrate, the first and fourth doped regions are of the first conductivity type, and the DW region, the second and the third doped regions are of a second conductivity type. The anode is electrically coupled to the fourth doped region, and the cathode is electrically coupled to the first and second doped regions.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.