Combined With Other Solid-state Active Device In Integrated Structure Patents (Class 257/140)
  • Patent number: 12237381
    Abstract: A power semiconductor device includes: a semiconductor body having a first surface and a mesa portion that includes a surface part of the first surface and a body region; at least two trenches extending from the first surface into the semiconductor body along a vertical direction, each trench including a trench electrode and trench insulator insulating the trench electrode from the semiconductor body, the mesa portion being laterally confined by the trenches in a first vertical cross-section along a first lateral direction; and a contact plug in contact with the body region. The contact plug and trench electrode of a first trench laterally overlap at least partially in the first vertical cross-section. A protection structure having a portion arranged within the first trench is arranged between the contact plug and trench electrode of the first trench. The protection structure may be an electrically insulation structure or a protective device structure.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: February 25, 2025
    Assignee: Infineon Technologies AG
    Inventor: Alim Karmous
  • Patent number: 12237408
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate and a first electrode provided above an upper surface of the semiconductor substrate. The semiconductor substrate has a first conductive type drift region. The semiconductor substrate has a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate. The semiconductor substrate has a second conductive type contact region with a higher impurity concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate. The semiconductor substrate has a trench contact that has a conductive material in an interior of a groove portion penetrating the contact region, the conductive material being in contact with at least a part of the semiconductor substrate, and connected to the first electrode.
    Type: Grant
    Filed: December 26, 2023
    Date of Patent: February 25, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 12224316
    Abstract: A semiconductor device includes an IGBT in an IGBT portion of a semiconductor body and a diode in a diode portion of the semiconductor body. The diode includes an anode region of a first conductivity type and confined by diode trenches along a first lateral direction. Each of the diode trenches includes a diode trench electrode and a diode trench dielectric. A first contact groove extends into the anode region along a vertical direction from the first surface of the semiconductor body. An anode contact region of the first conductivity type adjoins a bottom side of the first contact groove. A cathode contact region of a second conductivity type adjoins a second surface of the semiconductor body opposite to the first surface. The IGBT includes a gate trench including a gate electrode and a gate dielectric, a source region, an emitter electrode, a drift region, and a second contact groove.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: February 11, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Philipp Sandow, Wolfgang Roesner
  • Patent number: 12224311
    Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: February 11, 2025
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 12206015
    Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: January 21, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tohru Shirakawa
  • Patent number: 12174503
    Abstract: A display panel is disclosed. The display panel includes a photosensitive device. The photosensitive device includes a barrier component and a second active pattern. The second active pattern includes a second lightly-doped part, a second intrinsic part surrounding the second lightly-doped part, and a second heavily-doped part surrounding the second intrinsic part. In a film thickness direction, the barrier component overlaps the second intrinsic part. A dark current of the photosensitive device is reduced by the second intrinsic part, thereby improving sensitivity.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: December 24, 2024
    Inventors: Jiyue Song, Fei Al
  • Patent number: 12166111
    Abstract: We herein describe a semiconductor device comprising a first element portion formed on a substrate, the first element portion being an operating region of an insulated gate bipolar transistor (IGBT) and a second element portion formed on the substrate, the second element portion being an operating region of a diode.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 10, 2024
    Assignees: DYNEX SEMICONDUCTOR LIMITED, ZHUZHOU CRRC TIMES SEMICONDUCTOR CO. LTD.
    Inventors: Luther-King Ekonde Ngwendson, Ian Deviny
  • Patent number: 12148817
    Abstract: A method of manufacturing a semiconductor device comprising a transistor section and a diode section each having a drift region of a first conductivity-type inside a semiconductor substrate, and a base region of a second conductivity-type above the drift region. A particle beam is irradiated from an upper surface of the semiconductor substrate forming a lifetime control region including lifetime killers below the base region from at least a part of the transistor section to the diode section. A threshold value adjusting section is formed for adjusting a threshold value of the transistor section, including a thickened portion Wgi of a gate insulating film in a gate trench section adjacent to the base region, the thickened portion having a dielectric constant less than or equal to 0.9 times a remaining portion of the gate insulating film in the gate trench section.
    Type: Grant
    Filed: December 25, 2023
    Date of Patent: November 19, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motoyoshi Kubouchi
  • Patent number: 12119641
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: October 15, 2024
    Inventor: Darryl G. Walker
  • Patent number: 12113014
    Abstract: An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate. The first conductive line is a first distance from the substrate. The integrated circuit further includes a second conductive line extending parallel to the top surface of the substrate. The second conductive line is a second distance from the substrate. The integrated circuit further includes a third conductive line extending parallel to the top surface of the substrate. The third conductive line is a third distance from the substrate. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a sidewall of a lower portion of the supervia and the substrate is different from a second angle between a sidewall of an upper portion of the supervia and the substrate.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 12113126
    Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of second conductivity type provided on the first semiconductor layer; a second electrode provided on the second semiconductor layer; a first trench reaching the first semiconductor layer from the second semiconductor layer; a first semiconductor region provided in the second semiconductor layer, the first semiconductor region being in contact with the first trench and the first semiconductor region having a higher concentration of impurities of second conductivity type than the second semiconductor layer; and a first insulating film provided in the second semiconductor layer and the first insulating film being in contact with the first semiconductor region.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 8, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kaori Fuse, Keiko Kawamura, Takako Motai, Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 12094889
    Abstract: A display substrate, a method for manufacturing a display substrate and a display device are provided, and the display substrate includes: a base having a first surface, a second surface and a side surface, the base includes a display area and an epitaxial area; a driving functional layer in the display area and first binding electrodes in the epitaxial area on the first surface, the first binding electrodes are coupled with the driving functional layer; second binding electrodes located on the second surface and coupled with the first binding electrodes through side wirings; a portion of each side wiring is located on the side surface; a blocking wall on the first surface and in the epitaxial area, an orthographic projection of the blocking wall on the base at least passes through spacing regions between every two adjacent first binding electrodes along an arrangement direction of the first binding electrodes.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: September 17, 2024
    Assignees: BOE MLED Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Linhui Gong, Chao Liu
  • Patent number: 12087765
    Abstract: A semiconductor device, including a semiconductor substrate, a transistor section and a diode section arranged in a predetermined arrangement direction and provided on the semiconductor substrate, is provided. The diode section includes a drift region of a first conductivity-type provided in the semiconductor substrate, a base region of a second conductivity-type extending to a height of an upper surface of the semiconductor substrate and provided above the drift region, first cathode regions of the first conductivity-type, and second and third cathode regions of the second conductivity-type. The first, second, and third cathode regions extend to a height of a lower surface of the semiconductor substrate in a depth direction and provided below the drift region. The first and second cathode regions are provided in contact with each other, alternating in the arrangement direction, and sandwiched between the third cathode regions in an extension direction orthogonal to the arrangement direction.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: September 10, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 12080707
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type drift region and a second conductivity type base region above the drift region, trench portions at an upper surface of the semiconductor substrate arrayed parallel to one another, each of them penetrating the base region, and mesa portions between respective trench portions. Among the mesa portions, at least one mesa portion includes a first conductivity type first semiconductor region having a higher concentration than the drift region, a second conductivity type second semiconductor region having a higher concentration than the base region, and a first conductivity type accumulation region between the base and drift regions and has a higher concentration than the drift region. The drift region does not extend above the accumulation region. In a longitudinal direction of the trench portions, the accumulation region extends beyond an end portion of the first semiconductor region.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: September 3, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 12080784
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: September 3, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 12074161
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that a includes second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: August 27, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Shinya Umeki
  • Patent number: 12068404
    Abstract: Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: August 20, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Atsushi Shoji, Soichi Yoshida
  • Patent number: 12068310
    Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 20, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Munenori Ikeda, Shinya Soneda, Kenji Harada
  • Patent number: 12062654
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 13, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Yoshida, Kenji Suzuki, Yuki Haraguchi, Hidenori Koketsu
  • Patent number: 12057497
    Abstract: A semiconductor device includes: an inner region including a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region; and well regions having a higher doping concentration than that of the base region, provided from the upper surface of the semiconductor substrate to a depth position greater than a lower end of the base region, and arranged with the inner region interposed therebetween at the upper surface of the semiconductor substrate. The inner region includes a longitudinal side in a predetermined longitudinal direction at the upper surface of the semiconductor substrate and a plurality of trench portions which extend from the upper surface of the semiconductor substrate to the drift region. At least one of the trench portions is separated into two or more partial trenches in the longitudinal direction, in a region which does not overlap the well regions.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 6, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motoyoshi Kubouchi
  • Patent number: 12033999
    Abstract: Provided is an electrostatic discharge protection device, including: a darlington structure formed in a substrate, and a diode string formed in the substrate and including a plurality of diodes connected in series. A first end of the darlington structure is connected to a first voltage, and a second end of the darlington structure is connected to a second voltage. An anode of the diode string is connected to a third end of the darlington structure. A cathode of the diode string is connected to the second voltage.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian Xu
  • Patent number: 12034065
    Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: July 9, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 12002806
    Abstract: The semiconductor substrate has a first principal surface and a second principal surface. The base contact layer is arranged between the base layer and the first principal surface, and forms a part of the first principal surface. The anode contact region is arranged between the anode layer and the first principal surface, forms a part of the first principal surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer. The anode contact region includes a first anode contact layer having a lower net concentration and a higher first conductivity type impurity concentration than the base contact layer.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: June 4, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Nishi, Shinya Soneda, Takahiro Nakatani
  • Patent number: 11973342
    Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: April 30, 2024
    Assignee: Mavagail Technology, LLC
    Inventor: Darryl G. Walker
  • Patent number: 11955477
    Abstract: A semiconductor device according to the embodiment includes: a transistor region including a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, and a third gate electrode provided in the third trench; a diode region including a fifth trench and a conductive layer provided in the fifth trench; a boundary region including a fourth trench and a fourth gate electrode provided in the fourth trench, the boundary region being provided between the transistor region and the diode region; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: April 9, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Ryohei Gejo
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11908954
    Abstract: A semiconductor device includes an insulated gate bipolar transistor region and a diode region adjacent to each other, wherein the insulated gate bipolar transistor region includes base layers of a second conductive type provided on the first main surface side, emitter layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side, multiple gate electrodes provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer, the base layer, and the drift layer via a gate insulating film, carrier injection suppression layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side and sandwiched by the base layers in the first direction.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 20, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahiro Nakatani, Tetsuya Nitta, Kakeru Otsuka
  • Patent number: 11901443
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate having a transistor section and a diode section, wherein both the transistor section and the diode section each have a drift region of a first conductivity-type provided inside the semiconductor substrate, and a base region of a second conductivity-type provided above the drift region inside the semiconductor substrate, inside the semiconductor substrate, a lifetime control region including lifetime killers is provided below the base region from at least a part of the transistor section to the diode section, and in the transistor section, a threshold value adjusting section for adjusting a threshold value of the transistor section is provided overlapping the lifetime control region as seen from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 13, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motoyoshi Kubouchi
  • Patent number: 11855077
    Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 26, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shigeki Sato, Seiji Momota, Tadashi Miyasaka
  • Patent number: 11848358
    Abstract: A drift layer is made of silicon carbide and has a first conductivity type. At least one trench has a first side surface facing a Schottky barrier diode region, and a second side surface extending in a transistor region and contacting a source region, a body region, and the drift layer. A first protective region is provided under the at least one trench, has a second conductivity type, and is higher in impurity concentration of the second conductivity type than the body region. A second protective region extends from the first protective region, reaches at least one of the first side surface and an end region of the second side surface continuous with the first side surface, has an uppermost portion shallower than a lowermost portion of the body region, and is higher in impurity concentration of the second conductivity type than the body region.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 19, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Rina Tanaka, Katsutoshi Sugawara, Yutaka Fukui, Hideyuki Hatta, Yusuke Miyata
  • Patent number: 11848325
    Abstract: A load drive device includes a semiconductor element and a current detection resistor. The semiconductor element includes a first main electrode provided on a front surface side and having a higher potential and a second main electrode provided on a back surface side opposite to the front surface and having a lower potential than the first main electrode. The second main electrode is divided such that the semiconductor element includes a main element that supplies electric power to a load in response to the main element being turned on and a sense element that detects a current. The current detection resistor is connected in series to the sense element and provided between the second main electrode of the sense element and the second main electrode of the main element.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: December 19, 2023
    Assignee: DENSO CORPORATION
    Inventor: Jun Fukuhara
  • Patent number: 11830872
    Abstract: A semiconductor device according to the present disclosure is an RC-IGBT in which an IGBT region 10 and a diode region 20 are provided adjacent to each other. The diode region 20 includes a p-type anode layer 25 provided on a first principal surface side of an n?-type drift layer 1, a p-type contact layer 24 provided on the first principal surface side of the p-type anode layer 25 and at a surface layer of a semiconductor substrate on the first principal surface side and connected with an emitter electrode 6, and an n+-type cathode layer 26 provided at a surface layer of the semiconductor substrate on a second principal surface side. The p-type contact layer 24 contains aluminum as p-type impurities, and the thickness of the p-type contact layer 24 is smaller than the thickness of an n+-type source layer 13 provided in the IGBT region 10.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 28, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuki Kudo, Hidenori Fujii, Tetsuo Takahashi
  • Patent number: 11810952
    Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.
    Type: Grant
    Filed: May 15, 2022
    Date of Patent: November 7, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11804465
    Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 31, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tatsushi Kaneda, Hirotaka Oomori, Ren Kimura, Toru Hiyoshi
  • Patent number: 11799023
    Abstract: A semiconductor device includes: a semiconductor substrate including an upper surface and a lower surface opposing each other and a drift layer of a first conductivity type; a base layer of a second conductivity type; an emitter layer of the first conductivity type and a contact layer of the second conductivity type; an active trench; dummy trenches; a trench gate electrode formed in the active trench; a dummy trench gate electrode formed in each of the dummy trenches; an embedded insulating film formed on the trench gate electrode in the active trench, formed on the dummy trench gate electrode in the dummy trench, and having an upper end lower than the upper surface; and an emitter electrode contacting the emitter layer on the upper surface and an inner wall of the active trench, and contacting the contact layer on the upper surface and an inner wall of the dummy trench.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: October 24, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Nishi, Shinya Soneda
  • Patent number: 11791409
    Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: October 17, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jin Seong Chung, Tae Hoon Lee
  • Patent number: 11776940
    Abstract: Electronic power modules are disclosed. In one example, an electronic power module includes a first aluminum substrate, a second aluminum substrate, and a third aluminum substrate arranged in a common plane. The electronic power module includes first gap separating the first aluminum substrate from the second aluminum substrate. The electronic power module includes a second gap separating the second aluminum substrate from the third aluminum substrate. The electronic power module includes a first semiconductor switching component electrically coupled to the first aluminum substrate and the second aluminum substrate. The electronic power module includes a second semiconductor switching component electrically coupled to the second aluminum substrate and the third aluminum substrate.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Kyocera AVX Components (Salzburg) GmbH
    Inventor: Louis Costa
  • Patent number: 11735584
    Abstract: A semiconductor device, allowing easy hole extraction, including a semiconductor substrate having drift and base regions; and transistor and diode portions, in which trench portions and mesa portions are formed, is provided. The transistor portion includes emitter and contact regions above the base region and exposed to an upper surface of the semiconductor substrate. The emitter region has a higher concentration than the drift region. The contact region has a higher concentration than the base region. The mesa portions include boundary mesa portion(s) at a boundary between the transistor and diode portions. The trench portions include dummy trench portion(s) provided adjacent to a trench portion adjacent to the boundary mesa portion(s) and provided on the transistor portion side relative to the trench portion adjacent to the boundary mesa portion(s). The boundary mesa portion(s) include a base boundary mesa portion in which the base region is exposed to the upper surface.
    Type: Grant
    Filed: August 14, 2022
    Date of Patent: August 22, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11728333
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that includes a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface, a boundary region that includes a second-conductivity-type well region formed in the surface layer portion of
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 15, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Shinya Umeki
  • Patent number: 11721689
    Abstract: A semiconductor device includes: a semiconductor region having charge carriers of a first conductivity type; a transistor cell in the semiconductor region; a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type, wherein a transition between the semiconductor channel region and the semiconductor region forms a first pn-junction; a semiconductor auxiliary region in the semiconductor region and having a second doping concentration of charge carriers of the second conductivity type. A transition between the semiconductor auxiliary region and semiconductor region forms a second pn-junction positioned deeper in the semiconductor region as compared to the first pn-junction.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: August 8, 2023
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Thomas Basler, Philip Christoph Brandt, Maria Cotorogea
  • Patent number: 11715789
    Abstract: A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 1, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Hidenori Fujii, Shigeto Honda
  • Patent number: 11694954
    Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 4, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Minoru Akutsu, Kentaro Chikamatsu
  • Patent number: 11605715
    Abstract: A bidirectional switch element includes: a substrate; an AlzGa1-zN layer; an AlbGa1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Alx1Ga1-x1N layer; a p-type Alx2Ga1-x2N layer; an AlyGa1-yN layer; and an AlwGa1-wN layer. The AlzGa1-zN layer is formed over the substrate. The AlbGa1-bN layer is formed on the AlzGa1-zN layer. The AlyGa1-yN layer is interposed between the substrate and the AlzGa1-zN layer. The AlwGa1-wN layer is interposed between the substrate and the AlyGa1-yN layer and has a higher C concentration than the AlyGa1-yN layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masanori Nomura, Hiroaki Ueno, Yusuke Kinoshita, Yasuhiro Yamada, Hidetoshi Ishida
  • Patent number: 11594622
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11588048
    Abstract: In an example, a semiconductor device includes an insulated gate transistor cell, a first region (e.g., a drain region and/or a drift region), a cathode region, a second region (e.g., an anode region and/or a separation region), and a source electrode. The insulated gate transistor cell includes a source region and a gate electrode. The source region and the cathode region are in a silicon carbide body. The gate electrode and the cathode region are electrically connected. The cathode region, the source region, and the first region have a first conductivity type. The second region has a second conductivity type and is between the cathode region and the first region. The source electrode and the source region are electrically connected. The source electrode and the second region are in contact with each other. A rectifying junction is electrically coupled between the source electrode and the cathode region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 21, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Basler, Hans-Guenter Eckel, Jan Fuhrmann, Dethard Peters, Florian Stoermer
  • Patent number: 11581434
    Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 14, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jin Seong Chung, Tae Hoon Lee
  • Patent number: 11581361
    Abstract: Disclosed herein is a method comprising: forming a first electrically conductive layer on a first surface of a substrate of semiconductor, wherein the first electrically conductive layer is in electrical contact with the semiconductor; bonding, at the first electrically conductive layer, a support wafer to the substrate of semiconductor; thinning the substrate of semiconductor.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 14, 2023
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 11569092
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: January 31, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi
  • Patent number: 11502074
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroko Itokazu, Tomoko Matsudai, Yoko Iwakaji, Takako Motai
  • Patent number: 11495678
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: November 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Harada, Kakeru Otsuka, Hirofumi Oki