Combined With Other Solid-state Active Device In Integrated Structure Patents (Class 257/140)
  • Patent number: 10892295
    Abstract: An imaging sensor array comprises an epitaxial germanium layer disposed on a silicon layer, and an electrically biased photoelectron collector arranged on the silicon layer, on a side opposite the germanium layer.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 12, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Satyadev Hulikal Nagaraja, Onur Can Akkaya, Cyrus Soli Bamji
  • Patent number: 10848052
    Abstract: The present invention concerns a method for controlling the temperature of a multi-die power module, comprising: determining and memorizing a first weighted arithmetic mean of junction temperatures of the dies of the multi-die power module, determining successively another weighted arithmetic mean of junction temperatures of the dies, checking if the difference between the other weighted arithmetic mean and the memorized weighted arithmetic mean is lower than a first predetermined value, enabling a modification of the duty cycle of an input signal to apply to at least one selected die of the multi-die power module if the difference is lower than a first predetermined value, disabling a modification of the duty cycle of the input signal to apply to the at least one die of the multi-die power module if the difference is not lower than the first predetermined value.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 24, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jeffrey Ewanchuk, Julio Cezar Brandelero, Stefan Mollov, Jonathan Robinson
  • Patent number: 10840099
    Abstract: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kouji Mukai, Souichi Yoshida
  • Patent number: 10811529
    Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Christian Fachmann, Bjoern Fischer, Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: 10763345
    Abstract: In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 1, 2020
    Assignee: DENSO CORPORATION
    Inventors: Koichi Murakawa, Masakiyo Sumitomo, Shigeki Takahashi
  • Patent number: 10748988
    Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 18, 2020
    Assignee: DENSO CORPORATION
    Inventors: Masanori Miyata, Shigeki Takahashi, Masakiyo Sumitomo, Tomofusa Shiga
  • Patent number: 10734506
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 10727228
    Abstract: A stacked integrated circuit encompasses a lower chip including a lower semiconductor element and an upper surface-electrode electrically connected to an upper main-electrode region of the lower semiconductor element, the upper main-electrode region is located on an upper-surface side of the lower semiconductor element; and an upper chip including an upper semiconductor element and a lower surface-electrode electrically connected to a lower main-electrode region of the upper semiconductor element, the lower main-electrode region is located on a lower-surface side of the upper semiconductor element, the lower surface-electrode is metallurgically in contact with the upper surface-electrode.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 10727225
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate electrode, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, and a second electrode. The first semiconductor region is provided on the first electrode. The eighth semiconductor region surrounds the third semiconductor region, the sixth semiconductor region, and the seventh semiconductor region. The eighth semiconductor region includes a first region and a second region respectively arranged with the third semiconductor region and the seventh semiconductor region in a third direction. A lower end of the second region is positioned higher than a lower end of the first region.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 28, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Ryohei Gejo
  • Patent number: 10720518
    Abstract: A semiconductor device includes a drift layer, a base layer, a collector layer, gate insulating films, gate electrodes, an emitter region, a first electrode and a second electrode. The base layer is provided on the drift layer. The drift layer is provided between the base layer and the collector layer. The gate insulating films are respectively provided on wall surfaces of trenches penetrating the base layer to reach the drift layer. The gate electrodes are respectively provided on the gate insulating films. The emitter region is provided in a surface layer portion of the base layer, and is in contact with the trenches. The first electrode is electrically coupled with the base layer and the emitter region. The second electrode is electrically coupled with the collector layer. Some gate electrodes are applied with a gate voltage. Other gate electrodes are electrically coupled to the first electrode.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 21, 2020
    Assignee: DENSO CORPORATION
    Inventor: Masakiyo Sumitomo
  • Patent number: 10700217
    Abstract: A semiconductor device includes second and third semiconductor layers provided on a first semiconductor layer. The second semiconductor layer includes a recess portion and an outer edge portion. The third semiconductor layer is away from the second semiconductor layer in a first direction along a first boundary between the first semiconductor layer and the recess portion. The second semiconductor layer has first and second distributions of a second conductivity type impurity at a vicinity of the first boundary and at a vicinity of a second boundary between the outer edge portion and the first semiconductor layer, respectively. The third semiconductor layer has a third distribution of a second conductivity type impurity at a vicinity of a third boundary between the first semiconductor layer and the third semiconductor layer. The first distribution is substantially same as the second distribution. The third distribution is substantially same as the second distribution.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 30, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masato Izumi
  • Patent number: 10686038
    Abstract: An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only to form the backside contact regions and the front side device region. The fabrication method forms an RC-IGBT device using front side processing to form the backside contact regions and then using wafer bonding process to flip the semiconductor structure onto a carrier wafer so that front side processing is used again to form the device region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 16, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Hongyong Xue, Lei Zhang, Brian Schorr, Chris Wiebe, Wenjun Li
  • Patent number: 10651168
    Abstract: Embodiments of an RF amplifier package include a body section comprising an upper surface having first and second opposing edge sides, and a die pad vertically recessed beneath the upper surface and comprising first and second opposing sides and a third side intersecting with the first and second sides. Embodiments also include first and second leads disposed on the upper surface, the second lead extending from adjacent to the second side to the second edge side; and a biasing strip connected to the second lead and disposed on the upper surface adjacent to the third side. Other embodiments include packaged RF amplifiers comprising an RF amplifier package, and an RF transistor mounted on the die pad and comprising: a control terminal electrically coupled to the first lead, a reference potential terminal directly facing and electrically connected to the die pad, and an output terminal electrically connected to the second lead.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Cree, Inc.
    Inventors: Timothy Canning, Bjoern Herrmann, Richard Wilson
  • Patent number: 10629685
    Abstract: An RC-IGBT having a transistor portion and diode portion is provided. An RC-IGBT having a transistor portion and diode portion, and including: a semiconductor substrate; drift region of the first conductivity type provided on the upper surface side of the semiconductor substrate; base region of the second conductivity type provided above the drift region; source region of the first conductivity type provided above the base region; and two or more trench portions provided passing through the source region and the base region from the upper end side of the source region is provided. The diode portion includes: a source region; contact trench provided between two adjacent trench portions of the two or more trench portions on the upper surface side of the semiconductor substrate; and contact layer of the second conductivity type provided below the contact trench, whose doping concentration is higher than a doping concentration of the base region.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10629678
    Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 21, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10606141
    Abstract: In an electrooptical device, a plurality of scanning lines extend between a first side of a display region and a scanning line driving circuit. A semiconductor sensor is provided between the scanning line driving circuit and the first side of the display region, the semiconductor sensor including a sensor semiconductor layer which is on the same layer as a semiconductor layer of a pixel transistor. The semiconductor sensor is a diode temperature sensor, and includes a plurality of diode elements (sensor elements) that are disposed along the first side of the display region and electrodes that electrically connect the plurality of diode elements.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 10586793
    Abstract: A semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode. A corresponding method for operating a semiconductor device is also disclosed.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Frank Wolter
  • Patent number: 10580853
    Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 3, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10563501
    Abstract: In one aspect, an electromagnetic (EM) telemetry device is disclosed including an EM telemetry circuit capable of transmitting a pulsed high power EM telemetry signal, wherein the high power EM telemetry signal has a peak or average pulse power of about 20 W to about 2000 W.
    Type: Grant
    Filed: June 19, 2016
    Date of Patent: February 18, 2020
    Assignee: FASTCAP SYSTEMS CORPORATION
    Inventors: John J. Cooley, Riccardo Signorelli, Morris Green, Joseph K. Lane, Dan Stiurca
  • Patent number: 10559663
    Abstract: A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: February 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10535760
    Abstract: An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
    Type: Grant
    Filed: January 21, 2018
    Date of Patent: January 14, 2020
    Assignee: LITTELFUSE, INC.
    Inventor: Kyoung Wook Seok
  • Patent number: 10522674
    Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: December 31, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Nasu
  • Patent number: 10510832
    Abstract: A semiconductor device including: a drift region formed on a semiconductor substrate; a gate trench portion provided on an upper surface of the semiconductor substrate; a first and second mesa portion adjacent to one and the other of the gate trench portions; an accumulation region provided above the drift region in the first mesa portion; a base region provided above the accumulation region; a emitter region provided between the base region and the upper surface of the semiconductor substrate; an intermediate region provided above the drift region in the second mesa portion; a contact region provided above the intermediate region, wherein the gate trench portion has a gate conductive portion; a bottom portion of the gate conductive portion has a first step and second step; and, at least part of the intermediate region is provided between the steps and the bottom portion of the gate trench portion will be provided.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10483356
    Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 19, 2019
    Assignee: SILICONIX INCORPORATED
    Inventors: Max Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso
  • Patent number: 10483383
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
  • Patent number: 10475911
    Abstract: Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm?3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm?3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Philip Christoph Brandt, Andre Rainer Stegner
  • Patent number: 10475782
    Abstract: Provided are an ESD protection diode and an electronic device including the same. An ESD protection diode and an electronic device including the same according to an embodiment of the inventive concept include first to fifth wells. The first well is connected to a first voltage terminal. The second well is connected to a second voltage terminal. The third well is connected to the input/output terminal. The fourth well is disposed between the first well and the third well, and the fifth well is disposed between the second well and the third well. The first to third wells are N-type wells, and the fourth and fifth wells are P-type wells. The first well includes a first N+ diffusion region and the second well includes a second N+ diffusion region. The fourth well includes a first P+ diffusion region and the fifth well includes a second P+ diffusion region.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 12, 2019
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, DANKOOK UNIVERSITY
    Inventors: Jimin Oh, Yong-Seo Koo, Yil Suk Yang, Jongdae Kim
  • Patent number: 10468484
    Abstract: A modified bipolar transistor is provided which can provide improved gain, Early voltage, breakdown voltage and linearity over a finite range of collector voltages. It is known that the gain of a transistor can change with collector voltage. This document teaches a way of reducing this variation by providing structures for the depletion regions with the device to preferentially deplete with. As a result the transistor's response can be made more linear.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 5, 2019
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, William Allan Lane, Seamus P. Whiston
  • Patent number: 10468511
    Abstract: A semiconductor device includes a third electrode between a first semiconductor region and a second electrode, a fourth electrode between the first semiconductor region and the second electrode, a second semiconductor region between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth electrode between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and a fifth semiconductor region between the first electrode and the first semiconductor region. A first insulating film is provided between the third electrode and the first semiconductor region, the second semiconductor region, the third semiconductor region and the second electrode.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 5, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai
  • Patent number: 10438971
    Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electron (19) together.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 8, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhisa Nagao, Noriaki Kawamoto
  • Patent number: 10424661
    Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 24, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Vadim Kushner, Eric Vann
  • Patent number: 10396071
    Abstract: A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigeki Sato
  • Patent number: 10381225
    Abstract: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: August 13, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kouji Mukai, Souichi Yoshida
  • Patent number: 10381347
    Abstract: A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 13, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Yu-Chi Chang, Wen-Ying Wen, Han-Hui Chiu
  • Patent number: 10366985
    Abstract: To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense IGBT used for current detection of the main IGBT. At a peripheral portion located at an outermost periphery of an active region surrounded by a dummy region within a sense IGBT cell, an n+-type semiconductor region is formed over an upper surface of a well of a floating state adjacent to a trench gate electrode embedded into a trench at an upper surface of a semiconductor substrate and applied with a gate voltage.
    Type: Grant
    Filed: May 20, 2017
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukio Takahashi, Hitoshi Matsuura
  • Patent number: 10361191
    Abstract: A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: July 23, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Katsumi Uryu
  • Patent number: 10361293
    Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Che Tsai, Alain F. Loiseau, Robert J. Gauthier, Jr., Souvick Mitra, You Li, Mickey H. Yu
  • Patent number: 10319713
    Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Kuo-Chin Chiu, Chia-Wei Hung
  • Patent number: 10297683
    Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei, Akio Nakagawa
  • Patent number: 10290568
    Abstract: A power module for an electric motor has at least one semiconductor switch half bridge with a high-side semiconductor switch and a low-side semiconductor switch. The semiconductor switches of the semiconductor switch half bridge have contact gap terminals which are each formed by a flat surface region of the semiconductor switch and which each point in the same direction. The high-side semiconductor switch and the low-side semiconductor switch enclose between them a circuit carrier that has at least two electrically conductive layers. A contact gap terminal of the low-side semiconductor switch and a contact gap terminal of the high-side semiconductor switch of the half bridge are electrically connected to each other by the circuit carrier.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 14, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Joachim Joos, Walter Von Emden
  • Patent number: 10276556
    Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 30, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Moshe Agam, Johan Camiel Julia Janssens, Bruce Greenwood, Sallie Hose, Agajan Suwhanov
  • Patent number: 10276552
    Abstract: A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with t
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: ABB Schweiz AG
    Inventors: Samuel Hartmann, Ulrich Schlapbach
  • Patent number: 10249751
    Abstract: A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer, and crystal defects are formed such that the frequency of appearance is gradually decreased from the upper surface of the p-type semiconductor layer toward the bottom surface of the n-type semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 2, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10229969
    Abstract: A protective diffusion region includes a first protective diffusion region at a location closest to a termination region, and a second protective diffusion region located away from the first protective diffusion region with a first space therebetween. A second space that is a distance between a termination diffusion region and the first protective diffusion region is greater than the first space. A current diffusion layer of a first conductivity type includes a first current diffusion layer located between the first protective diffusion region and the second protective diffusion region and having a higher impurity concentration than a drift layer, and a second current diffusion layer located between the first protective diffusion region and the termination diffusion region. The second current diffusion layer includes a region having a lower impurity concentration than the current diffusion layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Katsutoshi Sugawara
  • Patent number: 10224282
    Abstract: A protection device including a substrate, a first doped region, a first well region, a second doped region, a third doped region, a fourth doped region, a second well region, a fifth doped region, and a sixth doped region is provided. The substrate, the first well region, and the third and the fifth doped regions have a first conductivity type. The first doped and the second well regions are disposed in the substrate. The first, second, fourth, and sixth doped regions and the second well region have a second conductivity type. The first well and the second doped regions are disposed in the first doped region. The second doped region is not in contact with the first well region. The third and fourth doped regions are disposed in the first well region. The fifth and sixth doped regions are disposed in the second well region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 5, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Shao-Chang Huang
  • Patent number: 10186572
    Abstract: A semiconductor device includes first, second, and gate electrodes. A first silicon carbide region of a first type is between the first and second electrodes and between the gate and second electrodes. Second and third silicon carbide regions of a second type are between the first electrode and first silicon carbide region. A portion of the first silicon carbide region is between the second and third silicon carbide regions. A fourth silicon carbide region of the first type is between the first electrode and second silicon carbide region. A fifth silicon carbide region of the first type is between the first electrode and third silicon carbide region. An insulation layer is between the gate electrode and second and third silicon carbide regions and sixth silicon carbide region of the second type. A second portion of the first silicon carbide region is between the second electrode and sixth silicon carbide region.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Teruyuki Ohashi
  • Patent number: 10177221
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 8, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Patent number: 10134891
    Abstract: A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is disposed on the substrate. The first doped region and the second doped region are respectively disposed in the substrate at one side and another side of the gate structure. The first doped region and the second doped region have a first conductive type. The body region is disposed in the substrate at one side of the first doped region away from the gate structure. The body region has a second conductive type. The body region and the first doped region are separated by a distance, and no isolation structure exists between the body region and the first doped region.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 20, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Ting Hsu, Hong-Ze Lin
  • Patent number: 10109725
    Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 23, 2018
    Assignee: ABB Schweiz AG
    Inventors: Liutauras Storasta, Chiara Corvasce, Manuel Le Gallo, Munaf Rahimo, Arnost Kopta
  • Patent number: 10083956
    Abstract: A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the first semiconductor region and the second electrode, a fourth semiconductor region between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, a first insulating film between the third electrode and both the first electrode and the first semiconductor region, a fifth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, and a seventh semiconductor region between the fourth semiconductor region and the first insulating film and in contact with the first semicond
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai