Combined With Other Solid-state Active Device In Integrated Structure Patents (Class 257/140)
  • Patent number: 11355602
    Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: June 7, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoaki Inokuchi, Hiro Gangi, Yusuke Kobayashi, Masahiko Kuraguchi, Kazuto Takao, Ryosuke Iijima, Tatsuo Shimizu, Tatsuya Nishiwaki
  • Patent number: 11355477
    Abstract: There are provided a small-sized power semiconductor module and a small-sized power conversion device capable of reducing ringing voltage. A power semiconductor module includes: a positive electrode-side switching element and a positive electrode-side freewheeling diode corresponding to a positive electrode-side power semiconductor element; a negative electrode-side switching element and a negative electrode-side freewheeling diode corresponding to a negative electrode-side power semiconductor element; a positive electrode conductor pattern; a negative electrode conductor pattern; an AC electrode pattern; and a snubber substrate including an insulating substrate having a snubber circuit formed thereon. The snubber substrate includes the insulating substrate and the at least one snubber circuit arranged on the insulating substrate. The snubber substrate is arranged on at least one of the positive electrode conductor pattern, the negative electrode conductor pattern and the AC electrode pattern.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 7, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Horiguchi, Yuji Miyazaki, Tatsunori Yanagimoto
  • Patent number: 11349020
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 31, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 11335795
    Abstract: To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.
    Type: Grant
    Filed: November 24, 2019
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kaname Mitsuzuka, Misaki Takahashi, Tohru Shirakawa
  • Patent number: 11322604
    Abstract: An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Ryu Kamibaba, Tetsuya Nitta
  • Patent number: 11322585
    Abstract: A semiconductor device includes a semiconductor layer. The semiconductor layer has bottom and upper surfaces opposite to each other in a first direction. The semiconductor layer includes a first region of a first conductivity type at the bottom surface, a second region of the first conductivity type at the bottom surface surrounding the first region, a third region of the first conductivity type above the first and second regions, and a fourth region of a second conductivity type extending from the upper surface into the third region. In a first cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a first distance. In a second cross sectional plane along the first direction, an outer edge of the first region is within an outer edge of the fourth region by a second distance.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Shoko Hanagata
  • Patent number: 11296192
    Abstract: A silicon carbide semiconductor device includes, sequentially, a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type provided on the third semiconductor layer. A first electrode is provided on the first semiconductor layer, and a second electrode is provided on the fourth semiconductor layer. An impurity concentration of the second semiconductor layer is higher than that of the first semiconductor layer, and an impurity concentration of the third semiconductor layer is lower than that of the second semiconductor layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Mina Ohse
  • Patent number: 11289593
    Abstract: A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 29, 2022
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gilberto Curatola, Martin Huber, Ingo Daumiller
  • Patent number: 11282937
    Abstract: The invention provides an inexpensive flywheel diode having a low power loss. A semiconductor substrate side of a gate electrode provided on a surface of an anode electrode side of a semiconductor substrate including silicon is surrounded by a p layer, an n layer, and a p layer via a gate insulating film. The anode electrode is in contact with the p layer with a low resistance, and is also in contact with the n layer or the p layer, and a Schottky diode is formed between the anode electrode and the n layer or the p layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 22, 2022
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Mutsuhiro Mori, Tomoyuki Miyoshi, Tomoyasu Furukawa, Masaki Shiraishi
  • Patent number: 11276771
    Abstract: A semiconductor device is provided, which includes a semiconductor substrate, a transistor section and a diode section. Each of the transistor and diode sections includes a plurality of trench parts, an insulating portion formed on an inner wall of each trench part, a conductive portion provided in each trench part, a plurality of mesa parts, an interlayer dielectric film having contact holes, and a first electrode in contact with the mesa parts via the contact holes. The mesa parts in the transistor section include T-side mesa parts arranged closest to the diode section, the mesa parts in the diode section include D-side mesa parts arranged closest to the transistor section, and a maximum mesa width of mesa parts electrically connected to the first electrode in the transistor section is greater than both a mesa width of the T-side mesa parts and a mesa width of the D-side mesa parts.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11251161
    Abstract: An object of the present invention is to suppress reduction in a temperature cycle life of a wiring in a two-in-one type chopper module. A two-in-one type chopper module according to the present invention includes: a switching transistor; a first diode inverse-parallelly connected to the switching transistor; a second diode serially connected to the switching transistor and the first diode; a first wiring pattern mounting the switching transistor and the first diode; and a second wiring pattern mounting the second diode, wherein each of the switching transistor and the first diode has a power loss substantially identical with each other at a time of a forward direction current conduction, and an effective area of the second diode is larger than an effective area of the first diode.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 15, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Tetsu Negishi
  • Patent number: 11222886
    Abstract: The present invention provides an ESD protection device with the mechanism of punch through to achieve low trigger voltage. At the same time, the structure of ESD protection device includes parasitic NPN and parasitic PNP. Parasitic NPN and parasitic PNP will form a silicon controlled rectifier (SCR) device with snapback behavior to increase the protection capability of ESD protection device.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 11, 2022
    Inventor: Wen-Tsung Chang
  • Patent number: 11217579
    Abstract: A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n? drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuo Takahashi
  • Patent number: 11217580
    Abstract: A semiconductor device includes a single semiconductor substrate on which an IGBT region including an IGBT element and an FWD region including a FWD element are formed. In the semiconductor device, a cathode layer is formed with a carrier injection layer, which is electrically connected to a second electrode and has a PN junction with a field stop layer. When a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current is flowing through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 4, 2022
    Assignee: DENSO CORPORATION
    Inventor: Taku Mizukami
  • Patent number: 11201061
    Abstract: Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aritra Dasgupta, Oleg Gluschenkov
  • Patent number: 11195908
    Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11195941
    Abstract: Provided is a semiconductor device including a semiconductor substrate having a drift region; a transistor portion having a collector region; a diode portion having a cathode region; and a boundary portion arranged between the transistor portion and the diode portion at an upper surface of the semiconductor substrate, and having the collector region, wherein the mesa portion of each of the transistor portion and the boundary portion has an emitter region and a base region, the base region has a channel portion, and a density in the upper surface of the mesa portion in the region in which the channel portion is projected onto the upper surface of the mesa portion of the boundary portion may be smaller than the density of the region in which the channel portion is projected onto the upper surface of the mesa portion of the transistor portion.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Michio Nemoto
  • Patent number: 11183588
    Abstract: A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Satoh
  • Patent number: 11183388
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi
  • Patent number: 11183387
    Abstract: A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 23, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinichi Tabuchi, Yasuo Ata
  • Patent number: 11139278
    Abstract: A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 5, 2021
    Assignee: YANGZHOU GUOYANG ELECTRONIC CO., LTD.
    Inventors: Ligang Niu, Yulin Wang, Hesong Teng, Wenhui Xu
  • Patent number: 11139291
    Abstract: A semiconductor device is provided, including a semiconductor substrate, wherein the semiconductor substrate has: a diode region; a transistor region; and a boundary region that is positioned between the diode region and the transistor region, the boundary region includes a defect region that is provided: at a predetermined depth position on a front surface-side of the semiconductor substrate; and to extend from an end portion of the boundary region adjacent to the diode region toward the transistor region, at least part of the boundary region does not include a first conductivity-type emitter region exposed on a front surface of the semiconductor substrate, and the transistor region does not have the defect region below a mesa portion that is sandwiched by two adjacent trench portions, and closest to the boundary region among the mesa portions having the emitter region.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi, Kaname Mitsuzuka, Daisuke Ozaki, Akinori Kanetake
  • Patent number: 11127846
    Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first recess is located between the drain structure and the gate structure.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 21, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 11121253
    Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 14, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Jin Seong Chung, Tae Hoon Lee
  • Patent number: 11107887
    Abstract: A semiconductor device includes: an n-type semiconductor substrate having a cell region and a termination region provided around the cell region; a p-type anode layer provided on an upper surface of the n-type semiconductor substrate in the cell region; an n-type buffer layer provided on a lower surface of the n-type semiconductor substrate; and a p-type layer provided on the lower surface of the n-type buffer layer in the termination region and deeper than the n-type buffer layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Patent number: 11101375
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 24, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11069529
    Abstract: To provide a semiconductor device, wherein each of a transistor portion and a diode portion that are arrayed along an array direction has: a second-conductivity type base region provided above a first-conductivity type drift region inside a semiconductor substrate; a plurality of trench portions that penetrate the base region from an upper surface of the semiconductor substrate, extend at the upper surface of the semiconductor substrate and in a direction of extension perpendicular to the array direction, and have conductive portions provided therein; and a lower-surface side lifetime control region that lies on a lower-surface side in the semiconductor substrate, and from the transistor portion to the diode portion, and includes a lifetime killer. In the array direction, the transistor portion may have a portion provided with the lower-surface side lifetime control region, and another portion not provided with the lower-surface side lifetime control region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11063141
    Abstract: An insulated gate field effect bipolar transistor (IGFEBT) includes a substrate, a deep well (DW) region, a first conductivity type well region, a gate structure, a source region and a drain region located on the first conductivity type well region at both sides of the gate structure, an anode, and a cathode. The source region includes a first doped region and a second doped region between the first doped region and the gate structure, and the drain region includes a third doped region and a fourth doped region formed on the third doped region. The substrate, the first and fourth doped regions are of the first conductivity type, and the DW region, the second and the third doped regions are of a second conductivity type. The anode is electrically coupled to the fourth doped region, and the cathode is electrically coupled to the first and second doped regions.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 13, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Chun-Sheng Chen
  • Patent number: 11043555
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 22, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11011510
    Abstract: An electronic device includes an ESD protection device with implanted regions that extend around a finger shape with a straight portion and elongated turn portions, and contacts that extend only in the straight portion, where the turn portions include elongated lightly doped implanted regions to mitigate turn on of a curvature PNP transistor for uniform device breakdown performance. Adjacent finger structures are spaced apart from one another to mitigate thermal transfer between device fingers.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 10943891
    Abstract: A semiconductor module includes a base plate for dissipating heat and a body having a bottom surface facing the base plate, a top surface opposite the bottom surface, and side surfaces between the bottom and top surfaces, wherein a first main electrode through which a first main current flows faces a first side surface among the side surfaces, and a second main electrode through which a second main current flows faces a second side surface opposite the first side surface. A power conversion apparatus includes a plurality of the semiconductor modules, wherein a cylindrical section is formed by arranging the semiconductor modules to surround a predetermined position, some of the first and second main electrodes are arranged on a first ring-shaped end surface at one end of the cylindrical section, and remaining electrodes are arranged on a second ring-shaped end surface at another end of the cylindrical section.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuji Sano
  • Patent number: 10930770
    Abstract: A power semiconductor device includes a semiconductor body, a first load terminal structure arranged at a front side of the semiconductor body, and a second load terminal structure arranged at a back side of the semiconductor body, and configured for controlling a load current between the load terminal structures by means of at least one transistor cell. The at least one transistor cell is at least partially included in the semiconductor body and electrically connected to the first load terminal structure on one side and to a drift region on the other side, the drift region being of a first conductivity type. The semiconductor body further includes: a transistor short region of the first conductivity type, wherein a transition between the transistor short region and the first load terminal structure forms a Schottky contact; and a separation region of a second conductivity type separating the transistor short and drift regions.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: February 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Guenter Eckel, Quang Tien Tran
  • Patent number: 10923578
    Abstract: A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Caspar Leendertz, Markus Bina, Matteo Dainese, Alice Pei-Shan Hsieh, Christian Philipp Sandow
  • Patent number: 10892295
    Abstract: An imaging sensor array comprises an epitaxial germanium layer disposed on a silicon layer, and an electrically biased photoelectron collector arranged on the silicon layer, on a side opposite the germanium layer.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 12, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Satyadev Hulikal Nagaraja, Onur Can Akkaya, Cyrus Soli Bamji
  • Patent number: 10848052
    Abstract: The present invention concerns a method for controlling the temperature of a multi-die power module, comprising: determining and memorizing a first weighted arithmetic mean of junction temperatures of the dies of the multi-die power module, determining successively another weighted arithmetic mean of junction temperatures of the dies, checking if the difference between the other weighted arithmetic mean and the memorized weighted arithmetic mean is lower than a first predetermined value, enabling a modification of the duty cycle of an input signal to apply to at least one selected die of the multi-die power module if the difference is lower than a first predetermined value, disabling a modification of the duty cycle of the input signal to apply to the at least one die of the multi-die power module if the difference is not lower than the first predetermined value.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: November 24, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jeffrey Ewanchuk, Julio Cezar Brandelero, Stefan Mollov, Jonathan Robinson
  • Patent number: 10840099
    Abstract: Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 17, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kouji Mukai, Souichi Yoshida
  • Patent number: 10811529
    Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Christian Fachmann, Bjoern Fischer, Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: 10763345
    Abstract: In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 1, 2020
    Assignee: DENSO CORPORATION
    Inventors: Koichi Murakawa, Masakiyo Sumitomo, Shigeki Takahashi
  • Patent number: 10748988
    Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 18, 2020
    Assignee: DENSO CORPORATION
    Inventors: Masanori Miyata, Shigeki Takahashi, Masakiyo Sumitomo, Tomofusa Shiga
  • Patent number: 10734506
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 10727225
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate electrode, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, and a second electrode. The first semiconductor region is provided on the first electrode. The eighth semiconductor region surrounds the third semiconductor region, the sixth semiconductor region, and the seventh semiconductor region. The eighth semiconductor region includes a first region and a second region respectively arranged with the third semiconductor region and the seventh semiconductor region in a third direction. A lower end of the second region is positioned higher than a lower end of the first region.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 28, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Ryohei Gejo
  • Patent number: 10727228
    Abstract: A stacked integrated circuit encompasses a lower chip including a lower semiconductor element and an upper surface-electrode electrically connected to an upper main-electrode region of the lower semiconductor element, the upper main-electrode region is located on an upper-surface side of the lower semiconductor element; and an upper chip including an upper semiconductor element and a lower surface-electrode electrically connected to a lower main-electrode region of the upper semiconductor element, the lower main-electrode region is located on a lower-surface side of the upper semiconductor element, the lower surface-electrode is metallurgically in contact with the upper surface-electrode.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 10720518
    Abstract: A semiconductor device includes a drift layer, a base layer, a collector layer, gate insulating films, gate electrodes, an emitter region, a first electrode and a second electrode. The base layer is provided on the drift layer. The drift layer is provided between the base layer and the collector layer. The gate insulating films are respectively provided on wall surfaces of trenches penetrating the base layer to reach the drift layer. The gate electrodes are respectively provided on the gate insulating films. The emitter region is provided in a surface layer portion of the base layer, and is in contact with the trenches. The first electrode is electrically coupled with the base layer and the emitter region. The second electrode is electrically coupled with the collector layer. Some gate electrodes are applied with a gate voltage. Other gate electrodes are electrically coupled to the first electrode.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 21, 2020
    Assignee: DENSO CORPORATION
    Inventor: Masakiyo Sumitomo
  • Patent number: 10700217
    Abstract: A semiconductor device includes second and third semiconductor layers provided on a first semiconductor layer. The second semiconductor layer includes a recess portion and an outer edge portion. The third semiconductor layer is away from the second semiconductor layer in a first direction along a first boundary between the first semiconductor layer and the recess portion. The second semiconductor layer has first and second distributions of a second conductivity type impurity at a vicinity of the first boundary and at a vicinity of a second boundary between the outer edge portion and the first semiconductor layer, respectively. The third semiconductor layer has a third distribution of a second conductivity type impurity at a vicinity of a third boundary between the first semiconductor layer and the third semiconductor layer. The first distribution is substantially same as the second distribution. The third distribution is substantially same as the second distribution.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 30, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Masato Izumi
  • Patent number: 10686038
    Abstract: An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only to form the backside contact regions and the front side device region. The fabrication method forms an RC-IGBT device using front side processing to form the backside contact regions and then using wafer bonding process to flip the semiconductor structure onto a carrier wafer so that front side processing is used again to form the device region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 16, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Hongyong Xue, Lei Zhang, Brian Schorr, Chris Wiebe, Wenjun Li
  • Patent number: 10651168
    Abstract: Embodiments of an RF amplifier package include a body section comprising an upper surface having first and second opposing edge sides, and a die pad vertically recessed beneath the upper surface and comprising first and second opposing sides and a third side intersecting with the first and second sides. Embodiments also include first and second leads disposed on the upper surface, the second lead extending from adjacent to the second side to the second edge side; and a biasing strip connected to the second lead and disposed on the upper surface adjacent to the third side. Other embodiments include packaged RF amplifiers comprising an RF amplifier package, and an RF transistor mounted on the die pad and comprising: a control terminal electrically coupled to the first lead, a reference potential terminal directly facing and electrically connected to the die pad, and an output terminal electrically connected to the second lead.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Cree, Inc.
    Inventors: Timothy Canning, Bjoern Herrmann, Richard Wilson
  • Patent number: 10629685
    Abstract: An RC-IGBT having a transistor portion and diode portion is provided. An RC-IGBT having a transistor portion and diode portion, and including: a semiconductor substrate; drift region of the first conductivity type provided on the upper surface side of the semiconductor substrate; base region of the second conductivity type provided above the drift region; source region of the first conductivity type provided above the base region; and two or more trench portions provided passing through the source region and the base region from the upper end side of the source region is provided. The diode portion includes: a source region; contact trench provided between two adjacent trench portions of the two or more trench portions on the upper surface side of the semiconductor substrate; and contact layer of the second conductivity type provided below the contact trench, whose doping concentration is higher than a doping concentration of the base region.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10629678
    Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 21, 2020
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Souichi Yoshida, Seiji Noguchi, Kenji Kouno, Hiromitsu Tanabe
  • Patent number: 10606141
    Abstract: In an electrooptical device, a plurality of scanning lines extend between a first side of a display region and a scanning line driving circuit. A semiconductor sensor is provided between the scanning line driving circuit and the first side of the display region, the semiconductor sensor including a sensor semiconductor layer which is on the same layer as a semiconductor layer of a pixel transistor. The semiconductor sensor is a diode temperature sensor, and includes a plurality of diode elements (sensor elements) that are disposed along the first side of the display region and electrodes that electrically connect the plurality of diode elements.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinsuke Fujikawa
  • Patent number: 10586793
    Abstract: A semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode. A corresponding method for operating a semiconductor device is also disclosed.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Frank Wolter