Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under a high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.

Abstract: In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconductor layer. A first electrode is formed on the third semiconductor layer, and a second electrode is formed on the first semiconductor layer in contact with the second semiconductor layer and apart from the semiconductor layer, thus forming a diode.

Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to monitor the growth rate of the growing film. The monocrystalline oxide layer (24) may be used to form a compliant substrate for monocrystalline growth of additional layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22) spaced apart from the silicon wafer (22) by an amorphous interface layer of silicon oxide (28). The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24).

Abstract: The invention includes a method of forming a transistor device. A semiconductor substrate is provided. The substrate has a silicon-comprising surface. The silicon-comprising surface is exposed to activated nitrogen for a time of at least about 20 seconds to convert the silicon-comprising surface to a material comprising silicon and nitrogen. The activated nitrogen is formed by exposing a nitrogen-containing precursor to a plasma generated at a power of at least about 750 watts. A transistor gate structure is formed over the material comprising silicon and nitrogen. The transistor gate structure defines a channel region underlying it. The material comprising silicon and nitrogen separates the transistor gate structure from the channel region. A pair of source/drain regions are formed which are separated from one another by the channel region.

Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

Abstract: An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Abstract: A wide high concentration P+ type region is formed on the surface of an N− type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, holes generated at the outside of the cell region mostly flow through the P+ type region and reach to an emitter electrode. Therefore, the flow amount of the holes does not concentrate on a channel P well for forming a channel region of the transistor device at the cell edge portion, whereby a ruggedness against a latch-up phenomenon can be improved.

Abstract: A semiconductor device includes a pair of semiconductor switching elements and a board. Each semiconductor switching element has positive and control electrodes formed on one surface and a negative electrode formed on the other surface. The positive and control electrodes of one of the semiconductor switching elements are joined to the board, and the negative electrode of the other semiconductor switching element, which faces in a direction opposite to that of one of the semiconductor switching elements, is joined to the board.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: AN IGBT including a collector positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. An emitter positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define a conduction channel extending laterally adjacent the control terminal and communicating with the drift region and the emitter. The substrate and buried region are the same conductivity and opposite the doped region to form a bipolar transistor therebetween.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: An insulated gate semiconductor device contains a common drain and a plurality of cells, each having a body region and a source. In each cell, the body region contains a channel region extending between the common drain and the source. The body region further includes a special portion spaced apart from the channel region, more heavily doped than the portion of the body region below the source, extending no more than an electrically insignificant amount below the source, and not extending significantly deeper below the upper semiconductor surface than the portion of the body region underlying the source. The special portion of each body region provides improved ruggedness under drain avalanche conditions. The special portion of each body region normally reaches a peak net dopant concentration below the upper semiconductor surface.

Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).

Abstract: A power device integrated structure includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type superimposed over the substrate, a plurality of first doped regions of the first conductivity type formed in the semiconductor layer, and a respective plurality of second doped regions of the second conductivity type formed inside the first doped regions. The power device includes: a power MOSFET having a fisrt electrode region formed by the second doped regions and a second electrode region formed by the semiconductor layer; a first bipolar junction transistor having an emitter, a base and a collector respectively formed by the substrate, the semiconductor layer and the first doped regions; and a second bipolar junction transistor having an emitter, a base and a collector respectively formed by the second doped regions, the first doped regions and the semiconductor layer.

Abstract: After selectively forming P.sup.+ -type gate regions 14 in the upper surface of a first N.sup.- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P.sup.+ -type gate regions. A P.sup.+ -type layer 12 is formed in the lower surface of the N.sup.- -type substrate 10. Recessed portions 26 which can house the gate electrodes are formed in the lower surface of the second N.sup.- -type semiconductor substrate 20 and an N.sup.+ -type layer 22 is formed in the upper surface thereof. After removing impurities from the surfaces of the first and second semiconductor substrates 10 and 20 by RCA cleaning, the surfaces are cleaned with a pure water and are dried by a spinner. Then the substrates 10 and 20 are joined to each other by heating the substrates 10 and 20 at 700-1100.degree. C. in an H.sub.2 atmosphere, while the upper surface of the first semiconductor substrate 10 is brought into contact with projected portions 29 on the lower surface of the second semiconductor substrate 20.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.

Abstract: A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.

Abstract: An n.sup.+ buffer layer, that is located between an n.sup.- base layer and a p.sup.+ substrate, has a resistivity in the range of 0.005-0.03 .OMEGA.cm and a thickness not more than 10.mu.m. Further, the base layer has an impurity concentration not more than (0.3.times.I.sub.1)/(S.times.1.6.times.10.sup.-19 .times.6.0.times.10.sup.6), where I.sub.1 is a rated current in ampere and S is an effective are in cm.sup.2.

Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.

Abstract: An insulated gate bipolar transistor employs a semiconductor substrate constructed by putting a high impurity density area, a low impurity density and a conductivity modulation area, respectively, of an n type on one another sequentially on a substrate of a p type, serving as a drain area. A gate is disposed on a gate oxide film deposited on the conductivity modulation area. A channel forming layer of a p type and a source layer of an n type are diffused from windows of the gate in such a manner that the peripheral edges of these layers creep under the gate, and a drain terminal, a source terminal, and on/off controlling gate terminal extend from the drain area, the channel forming layer and source layer, and the gate, respectively.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to .about.10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.