Abstract: The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.

Abstract: A semiconductor device includes a semiconductor layer having a main surface in which a trench is formed, a first-conductivity-type body region formed along a sidewall of the trench in a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type impurity region formed along the sidewall of the trench in a surface layer portion of the body region, a gate insulating layer formed on an inner wall of the trench, a gate electrode that is embedded in the trench and that faces the body region and the impurity region with the gate insulating layer placed between the gate electrode and the body region and between the gate electrode and the impurity region, a contact electrode that passes through the sidewall of the trench from inside the trench and is drawn out to the surface layer portion of the main surface of the semiconductor layer and is electrically connected to the body region and to the impurity region, and an embedded insulating layer that is interposed between the gate el

Abstract: A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

Abstract: A semiconductor device is provided including: a semiconductor substrate having a first-conductivity-type drift region; a second-conductivity-type base region provided above the drift region inside the semiconductor substrate; an accumulation region provided between the drift region and the lower surface of the base region inside the semiconductor substrate, and having a lower second-conductivity-type carrier mobility than the drift region and the base region; a gate trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, where the gate trench portion is in contact with the base region; and a carrier passage region occupying at least a partial region between the accumulation region and the gate trench portion inside the semiconductor substrate, where the carrier passage region has a higher second-conductivity-type carrier mobility than the accumulation region.

Abstract: An insulated gate bipolar transistor includes a substrate; a first conductivity type base disposed on the substrate and having a first trench; a first conductivity type buffer region disposed in the first conductivity type base; a collector doped region having a second conductivity type and disposed in the first conductivity type base; a second conductivity type base to which the first trench extends downwardly; a gate oxide layer disposed on an inner surface of the first trench; a polysilicon gate disposed inside the gate oxide layer; an emitter doped region having a first conductivity type and disposed in the second conductivity type base and under the first trench; a conductive plug extending downwardly from above the first trench and contacting the second conductivity type base; and an insulating oxide layer filled in the first trench, the insulating oxide layer insulating and isolating the polysilicon gate from the emitter doped region.

Abstract: A semiconductor device may include a semiconductor substrate, an upper electrode and a lower electrode. The semiconductor substrate may include: a p-type anode region being in contact with the upper electrode; an n-type cathode region being in contact with the lower electrode; an n-type drift region interposed between the anode region and the cathode region. The semiconductor substrate may further include a barrier region interposed between the anode region and the drift region; and an n-type pillar region extending between the barrier region and the upper electrode. The barrier region may include a multi-layer structure in which a p-type second barrier layer is interposed between an n-type first barrier layer and an n-type third barrier layer. The first barrier layer may be in contact with the anode region and is connected to the upper electrode via the pillar region.

Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.

Abstract: A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

Abstract: A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.

Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

Abstract: The present examples relate to a Schottky diode having floating guard rings and an additional element isolation layer configured to further improve a breakdown voltage of the Schottky diode, while maintaining the turn-on voltage and current in the forward characteristic, compared to a related Schottky diode. The floating guard rings in the examples are located in a position between the anode and the cathode regions or under the anode.

Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.

Abstract: An improvement is achieved in the performance of an electronic device. A first semiconductor device and a second semiconductor device are mounted over the upper surface of a wiring board such that, e.g., in plan view, the orientation of the second semiconductor device intersects the orientation of the first semiconductor device. That is, the first semiconductor device is mounted over the upper surface of the wiring board such that a first emitter terminal and a first signal terminal are arranged along an x-direction in which the pair of shorter sides of the wiring board extend. On the other hand, the second semiconductor device is mounted over the upper surface of the wiring board such that a second emitter terminal and a second signal terminal are arranged along a y-direction in which the pair of longer sides of the wiring board extend.

Abstract: A first device is provided. The first device further comprises an organic light emitting device. The organic light emitting device further comprises an anode, a cathode, and an emissive layer disposed between the anode and the cathode. The emissive layer may include an organic host compound and at least one organic emitting compound capable of fluorescent emission at room temperature. Various configurations are described for providing a range of current densities in which T-T fusion dominates over S-T annihilation, leading to very high efficiency fluorescent OLEDs.

Abstract: A p-type thin-layer along a side wall surface of a V-shaped groove reaching the bottom portion of a p-type isolation layer from the back surface of an n? semiconductor substrate, couples a p-type collector layer with the p-type isolation layer. A collector electrode contacts the surfaces of the p-type collector layer and the p-type thin-layer. The collector electrode is formed by laminating an Al—Si film, a barrier layer, a nickel-based metal film, and a gold-based metal film in sequence from the n? semiconductor substrate side. The Al—Si film contacting the surface of the p-type collector layer is in a range of 1.1 to 3.0 ?m in thickness. The Al—Si film contacting the surface of the p-type thin-layer is in a range of 0.55 to 1.5 ?m in thickness. Arise in leak current caused by aluminum spiking is eliminated or suppressed, and solder joining including tin is made easier.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: A semiconductor device includes a semiconductor substrate and a first electrode. An element region, and a non-element region that surrounds this element region, are formed on the semiconductor substrate. The first electrode is arranged on the semiconductor substrate and is electrically connected to the element region formed on the semiconductor substrate. The first electrode is made of at least two materials having different moduli of elasticity. A modulus of elasticity per unit area of an outer peripheral portion of the first electrode when the semiconductor substrate is viewed from above is smaller than a modulus of elasticity per unit area of a center portion of the first electrode.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.

Abstract: A semiconductor device having a lateral insulated gate bipolar transistor includes a first conductivity type drift layer, a second conductivity type collector region formed in a surface portion of the drift layer, a second conductivity type channel layer formed in the surface portion of the drift layer, a first conductivity type emitter region formed in a surface portion of the channel layer, and a hole stopper region formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.

Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.

Abstract: A semiconductor device includes a semiconductor body with a base layer and a field shaping zone of a first conductivity type. The base layer extends parallel to a back surface of the semiconductor body in a central portion and into an edge portion that surrounds the central portion. The field shaping zone is formed in the edge portion and has a maximum dopant concentration exceeding at least three times a maximum dopant concentration in the base layer. A back side metal structure directly adjoins the back surface in the central portion and extends over the edge portion. A dielectric structure is between the back side metal structure and the field shaping zone. Leakage current mechanisms reducing the reverse blocking capabilities are reduced.

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract: An organic EL device includes: an anode; a cathode and an organic thin-film layer provided between the anode and the cathode. The organic thin-film layer includes: a fluorescent-emitting layer containing a fluorescent host and a fluorescent dopant; and a phosphorescent-emitting layer containing a first phosphorescent host and a first phosphorescent dopant. The first phosphorescent dopant emits light by receiving exited triplet energy transferred from the fluorescent host. The fluorescent host has a substituted or unsubstituted polycyclic fused aromatic skeleton and has an exited triplet energy gap of 2.10 eV to 3.00 eV.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first semiconductor region 20 is formed on a substrate, and a second electroconductive type second semiconductor region 22, a second electroconductive type third semiconductor region 23, designated as an anode, and a first electroconductive type fourth semiconductor region 24, designated as an anode gate, are formed on the surface layer part of the first semiconductor region. Also, a first electroconductive type fifth semiconductor region 26, designated as a cathode, and a second electroconductive type sixth semiconductor region 25, designated as a cathode gate, are formed on the surface layer part of the second semiconductor region.

Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.

Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.

Abstract: An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.

Abstract: Disclosed are a liquid crystal display and a substrate for the same. The substrate comprises first wires formed in one direction on the substrate; second wires intersecting and insulated from the first wires; pixel electrodes formed in pixel regions defined by the first wires and the second wires; and switching elements connected to the first wires, the second wires and the pixel electrodes, wherein an interval between two adjacent second wires has a predetermined dimension that repeatedly varies from one set of adjacent second wires to the next, and a side of the pixel electrodes adjacent to the second wires is shaped in a pattern identical to the second wires such that the pixel electrodes have a wide portion and a narrow portion.

Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.

Abstract: A method of manufacturing a field emission device (FED) using a photoresist for performing multi-patterning processes, whereby different structures can be multi-patterned using a single photoresist mask. The photoresist has a solubility to a solvent by post-exposure heat-treatment, and a complicated structure can be formed using the photoresist.

Abstract: A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: A fast switching diode includes an n? layer having an upper surface and a lower surface and a first edge and a second edge, the second edge provided on an opposing side of the first edge. A converted region is provided proximate the upper surface of the n? layer. The converted region includes platinum and has a first depth. The converted region has a platinum concentration that is substantially greater than an n-type dopant concentration in the converted region. First and second n+ regions are provided proximate the first and second edges of the n? layer, respectively, and extend from the upper surface of the n? layer to second and third depths, respectively. Each of the second and third depths is greater than the first depth to reduce leakage current. A first electrode is provided proximate the upper surface of the n? layer. A second electrode is provided proximate the lower surface of the n? layer.

Abstract: The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell provides DRAM-like density and SRAM-like performance. The memory cell includes an access transistor and a gated-lateral thyristor integrally formed above the access transistor. The cathode region (n+) of the stacked lateral thyristor device (p+/n/p/n+) is physically and electrically connected to one of the source/drain regions of the FET to act as the storage node for the memory cell. The FET transistor can include an active region which extends into a Si/Ge material. The material comprising Si/Ge can have a relaxed crystalline lattice, and a layer having a strained crystalline lattice can be between the material having the relaxed crystalline lattice and the transistor gate. The device construction can be formed over a versatile substrate base.

Abstract: A field emission display with a double gate structure and a method of manufacturing therefor are provided. The field emission display includes a substrate, a cathode layer formed on the substrate, a gate insulating layer which is formed on the substrate and the cathode layer and has a cavity through which part of the cathode layer is exposed, a field emitter provided on the cathode layer exposed on the bottom of the cavity, a first gate layer which is formed in the gate insulating layer and in which a first gate hole having a diameter greater than that of the cavity is formed not to be exposed to an inner surface of the cavity, and a second gate layer which is formed on the gate insulating layer and in which a second gate hole is formed in a portion that corresponds to the cavity.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.

Abstract: ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: A cold cathode field emission device comprising a cathode electrode 11 formed on a supporting member 10, a gate electrode 13 which is formed above the cathode electrode 11 and has an opening portion 14, and an electron emitting portion 15 formed on a surface of a portion of the cathode electrode 11 which portion is positioned in a bottom portion of the opening portion 14, said electron emitting portion 15 comprising a carbon-group-material layer 23, and said carbon-group-material layer 23 being a layer formed from a hydrocarbon gas and a fluorine-containing hydrocarbon gas.

Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.

Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: A field emission display device and a method of fabricating the same are provided. The field emission display device includes a substrate, a transparent cathode layer, an insulation layer, a gate electrode, a resistance layer, and carbon nanotubes. The transparent cathode layer is deposited on the substrate. The insulation layer is formed on the cathode layer and has a well exposing the cathode layer. The gate electrode is formed on the insulation layer and has an opening corresponding to the well. The resistance layer is formed to surround the surface of the gate electrode and the inner walls of the opening and the well so as to block ultraviolet rays. The carbon nanotube field emitting source is positioned on the exposed cathode layer. An alignment error between the gate electrode and the cathode is removed, and carbon nanotube paste is prevented from remaining during development, thereby preventing current leakage and short circuit between the electrodes and diode emission.

Abstract: A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.

Abstract: A cold cathode device is formed from a p-type semiconductor substrate 1. Two source/drain regions 2 are formed in the p-type semiconductor substrate 1, a silicon oxide film 3, which is an insulating film, is formed on the surface of the p-type semiconductor substrate 1 (the face where the source/drain regions 2 are formed), and a gate electrode 4 is formed on top of the silicon oxide film 3. Furthermore, a substrate electrode 5 is formed on the back surface of the p-type semiconductor substrate 1. The same voltages are applied to the source/drain regions 2 and the gate electrode 4, and a lower voltage is applied to the substrate electrode 5.

Abstract: The invention concerns a semiconductor component with at east one lateral region which is provided to accommodate a lateral electric field strength, whereby the semiconductor body within the body and/or in regions proximal to the surface of the semiconductor body at least over regions thereof has a lateral three-dimensional structure which has vertical recesses in the semiconductor body within which there are electrical conductors which are smaller than in the intervening spaces of the semiconductor body between the recesses, as well as a method for making and of using the semiconductor component.