Cathode Emitter Or Cathode Electrode Feature Patents (Class 257/152)
  • Patent number: 10461157
    Abstract: The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 29, 2019
    Assignee: ABB Schweiz AG
    Inventors: Martin Arnold, Umamaheswara Vemulapati
  • Patent number: 10158325
    Abstract: An inspection apparatus inspects a solar cell. The inspection apparatus includes: a short-circuiting element that electrically connects an anode as a p-type semiconductor layer and a cathode as an n-type semiconductor layer of the solar cell to short-circuit the solar cell; an irradiation part that irradiates the solar cell short-circuited by the short-circuiting element with pulse light; and a detection part that detects an electromagnetic wave emitted from the solar cell in response to the irradiation of the solar cell with pulse light from the irradiation part.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 18, 2018
    Assignees: Screen Holdings Co., Ltd., Osaka University
    Inventors: Hidetoshi Nakanishi, Akira Ito, Iwao Kawayama, Masayoshi Tonouchi
  • Patent number: 10026732
    Abstract: A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (GCT) cells and a plurality of second GCT cells alternating with each other, a first base layer of each first GCT cell is separated from a neighbouring second anode layer of a neighbouring second GCT cell by a first separation region, and a second base layer of each second GCT cell is separated from a neighbouring first anode layer of a neighbouring first GCT cell by a second separation region.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 17, 2018
    Assignee: ABB Schweiz AG
    Inventors: Munaf Rahimo, Martin Arnold, Umamaheswara Vemulapati
  • Patent number: 9620632
    Abstract: A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 11, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Okawara, Yusuke Yamashita, Satoru Machida
  • Patent number: 9543305
    Abstract: A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w?), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w?) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: January 10, 2017
    Assignee: ABB SCHWEIZ AG
    Inventors: Neophythos Lophitis, Florin Udrea, Umamaheswara Vemulapati, Lulian Nistor, Martin Arnold, Jan Vobecky, Munaf Rahimo
  • Patent number: 9136268
    Abstract: A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-il Oh, Seok-jae Lee, Sung-hoon Kim, Joung-yeal Kim
  • Patent number: 9041143
    Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Nobuhiro Takahashi, Hironobu Shibata
  • Patent number: 8847277
    Abstract: An exemplary reverse-conducting power semiconductor device with a wafer having a first main side and a second main side parallel to the first main side. The device includes a plurality of diode cells and a plurality of IGCT cells, each IGCT cell including between the first and second main side: a first anode electrode, a first anode layer of a first conductivity type on the first anode electrode, a buffer layer of a second conductivity type on the first anode layer, a drift layer of the second conductivity type on the buffer layer, a base layer of the first conductivity type on the drift layer, a first cathode layer of a second conductivity type on the base layer, and a cathode electrode on the first cathode layer. A mixed part includes the second anode layers of the diode cells alternating with the first cathode layers of the IGCT cells.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 30, 2014
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Martin Arnold, Thomas Stiasny
  • Patent number: 8415710
    Abstract: A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 9, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Patent number: 8410002
    Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8330155
    Abstract: Semiconductor devices include a gate electrode, a gate insulation layer, a first channel layer pattern, a second channel layer pattern and first and second metallic patterns. The gate electrode is on a substrate. The gate insulation layer is on the gate electrode. The first channel layer pattern is on the gate insulation layer, and has a first conductivity level. The second channel layer pattern is on the first channel layer pattern, and has a second conductivity level that is lower than the first conductivity level. The first and second metallic patterns are on the gate insulation layer and contact respective sidewalls of the first and second channel layer patterns.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hun Jeon, Moon-Sook Lee
  • Patent number: 8093622
    Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani
  • Patent number: 8089139
    Abstract: A TSOP (Thin Small Outline Package) contains a MOSFET and a Schottky diode. The MOSFET has a source terminal a gate terminal and a drain terminal. The Schottky diode has a cathode terminal, a anode terminal. The TSOP contains the MOSFET and the Schottky diode with a special configuration by placing the drain terminal of the MOSFET and the anode terminal of the Schottky diode on a same side. Specifically, the TSOP implements a leadframe that comprises a plurality of leads. The drain terminal of the MOSFET and the anode terminal extends outside of the TSOP separate on the same side of the package.
    Type: Grant
    Filed: October 9, 2005
    Date of Patent: January 3, 2012
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: Zhengyu Shi, Limin Wang, Lei Shi
  • Patent number: 7999285
    Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 16, 2011
    Assignee: Dongby Hitek Co., Ltd.
    Inventor: Sang Yong Lee
  • Patent number: 7906796
    Abstract: In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Hidekatsu Onose, Natsuki Yokoyama
  • Patent number: 7884389
    Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method. The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 8, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Patent number: 7795047
    Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 14, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 7759194
    Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: July 20, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yi-Peng Chan, Sheng-He Huang, Zhen Yang
  • Patent number: 7732833
    Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroto Yamagiwa, Takashi Saji
  • Patent number: 7692211
    Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: April 6, 2010
    Assignee: Silicon Power Corporation
    Inventors: Vic Temple, Forrest Holroyd, Sabih Al-Marayati, Deva Pattanayak
  • Patent number: 7560773
    Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Tanaka
  • Patent number: 7485921
    Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Yoshihiro Yamaguchi, Syotaro Ono, Miwako Akiyama
  • Patent number: 7429761
    Abstract: A high power diode includes a cathode for emitting a primary electron discharge, an anode, and a porous dielectric layer, e.g. a honeycomb ceramic, positioned between the cathode and the anode for receiving the primary electron discharge and emitting a secondary electron discharge. The diode can operate at voltages 50 kV and higher while generating an electron beam with a uniform current density in the range from 1 A/cm2 to >10 kA/cm2 throughout the area of the cathode. It is capable of repetitively pulsed operation at a few Hz with pulse duration from a few nanoseconds to more than a microseconds, while the total number of pulses can be >107 pulses. The diode generates minimal out-gassing or debris, i.e. with minimal ablation, providing a greater diode lifetime, and can operate in a high vacuum environment of 10?4 Torr. The high power diode is useful in many applications requiring a high current electron beam.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 30, 2008
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Moshe Friedman, Matthew Myers, Frank Hegeler, John Sethian
  • Patent number: 7400017
    Abstract: To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: July 15, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Aono, Kenzo Yamamoto, legal representative, Ikuko Yamamoto, legal representative, Hideki Takahashi, Aya Yamamoto
  • Patent number: 7332749
    Abstract: A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: February 19, 2008
    Assignee: NGK Insulators, Ltd.
    Inventors: Naohiro Shimizu, Takayuki Sekiya
  • Patent number: 7276778
    Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 2, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 7259440
    Abstract: A fast switching diode includes an n? layer having an upper surface and a lower surface and a first edge and a second edge, the second edge provided on an opposing side of the first edge. A converted region is provided proximate the upper surface of the n? layer. The converted region includes platinum and has a first depth. The converted region has a platinum concentration that is substantially greater than an n-type dopant concentration in the converted region. First and second n+ regions are provided proximate the first and second edges of the n? layer, respectively, and extend from the upper surface of the n? layer to second and third depths, respectively. Each of the second and third depths is greater than the first depth to reduce leakage current. A first electrode is provided proximate the upper surface of the n? layer. A second electrode is provided proximate the lower surface of the n? layer.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: August 21, 2007
    Assignee: IXYS Corporation
    Inventor: Ulrich Kelberlau
  • Patent number: 7250628
    Abstract: The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell provides DRAM-like density and SRAM-like performance. The memory cell includes an access transistor and a gated-lateral thyristor integrally formed above the access transistor. The cathode region (n+) of the stacked lateral thyristor device (p+/n/p/n+) is physically and electrically connected to one of the source/drain regions of the FET to act as the storage node for the memory cell. The FET transistor can include an active region which extends into a Si/Ge material. The material comprising Si/Ge can have a relaxed crystalline lattice, and a layer having a strained crystalline lattice can be between the material having the relaxed crystalline lattice and the transistor gate. The device construction can be formed over a versatile substrate base.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7135717
    Abstract: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal 1 and the second input-output terminal.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: November 14, 2006
    Assignee: Nec Electronics Corporation
    Inventor: Hiroshi Mizutani
  • Patent number: 6921943
    Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (?-field) results from the changing dopant concentration. The creation of this ?-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: July 26, 2005
    Assignee: GlobiTech Incorporated
    Inventors: Danny Kenney, Keith Lindberg, Curtis Hall, G. R. Mohan Rao
  • Publication number: 20040206976
    Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.
    Type: Application
    Filed: May 14, 2004
    Publication date: October 21, 2004
    Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
  • Patent number: 6774434
    Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond J. E. Hueting, Jan W. Slotboom, Petrus H. C. Magnee
  • Publication number: 20040147049
    Abstract: Provided are a low-temperature formation method for emitter tips including copper oxide nanowires or copper nanowires and a display device or a light source manufactured using the same. The low-temperature formation method includes preparing a substrate having an exposed copper surface. The copper surface contacts an oxide solution at a low temperature of 100° C. or less to grow copper oxide nanowires on the surface of the substrate. Optionally, a reduction gas or a heat is supplied to the copper oxide nanowires, or plasma processing is performed on the copper oxide nanowires, thereby reducing the copper oxide nanowires to copper nanowires. Thus, emitter tips including copper oxide nanowires or copper nanowires are formed densely at a low temperature such that the emitter tips have a shape and length suitable for emission of electrons.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 29, 2004
    Applicant: Seoul National University Industry Foundation
    Inventors: Ho-Young Lee, Yong-Hyup Kim, Woo Yong Sung
  • Patent number: 6737705
    Abstract: A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: May 18, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiji Momota, Yuichi Onozawa, Masahito Otsuki, Hiroki Wakimoto
  • Patent number: 6727526
    Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Josef Niedernostheide, Hans-Joachim Schulze
  • Publication number: 20040056271
    Abstract: Nanotip arrays are formed by exposing a substrate to a process gas mixture that simultaneously forms nanomasks on the substrate surface and etches exposed portions of the substrate surface to form the nanotip array. Components of the process gas mixture form nanocrystallites on the surface of the substrate, thereby masking portions of the substrate from other components of the process gas mixture, which etch exposed portions of the substrate. Accordingly, nanotip arrays formed using this technique can have nanocrytallite endpoints.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 25, 2004
    Inventors: Kuie-Hsien Chen, Jih Shang Hwang, Debajyoti Das, Hong Chun Lo, Li-Chyong Chen
  • Patent number: 6677622
    Abstract: A semiconductor substrate is of first-conductivity-type and has a principal surface. A first semiconductor region and a second semiconductor region are of second-conductivity-type and formed apart from each other in the principal surface of the semiconductor substrate. A third semiconductor region is of second-conductivity-type and formed on the first semiconductor region. The third semiconductor region has an impurity concentration higher than that of the first semiconductor region. A fourth semiconductor region is of first-conductivity-type and formed on the third semiconductor region. A first main electrode is formed on the fourth semiconductor region. A second main electrode is formed on the second semiconductor region. A gate electrode is formed, at least on the first semiconductor region and on the principal surface of the semiconductor substrate between the fourth semiconductor region and the second semiconductor region, with a gate insulating film therebetween.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumito Suzuki, Hitoshi Takahashi, Haruki Arai, Yoshihiro Yamaguchi
  • Patent number: 6657239
    Abstract: In order to reduce a turn-on time of a power switching semiconductor device at a low cost, a first main electrode divided into a plurality of segments forming segment rows of a multi-concentric circle and a control electrode surrounding the segments are formed on a front major surface of a semiconductor substrate, and a second electrode is formed on a rear major surface thereof, and a turn-on operation is performed between the first main electrode and the second main electrode with a control signal inputted from the control electrode, specifying a relationship between a width of a segment and a distance between adjacent segments, and others.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: December 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhiro Morishita, Katsumi Satoh
  • Publication number: 20030141495
    Abstract: A field emission display device and a method of fabricating the same are provided. The field emission display device includes a substrate, a transparent cathode layer, an insulation layer, a gate electrode, a resistance layer, and carbon nanotubes. The transparent cathode layer is deposited on the substrate. The insulation layer is formed on the cathode layer and has a well exposing the cathode layer. The gate electrode is formed on the insulation layer and has an opening corresponding to the well. The resistance layer is formed to surround the surface of the gate electrode and the inner walls of the opening and the well so as to block ultraviolet rays. The carbon nanotube field emitting source is positioned on the exposed cathode layer. An alignment error between the gate electrode and the cathode is removed, and carbon nanotube paste is prevented from remaining during development, thereby preventing current leakage and short circuit between the electrodes and diode emission.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 31, 2003
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Hang-Woo Lee, Sang-Jin Lee, Shang-Hyeun Park
  • Patent number: 6476429
    Abstract: A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: November 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiro Baba
  • Patent number: 6429501
    Abstract: A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P−-type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N+-channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 1015-1016 atoms/cm3 where it contacts the semiconductive film.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: August 6, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Tsuchitani, Shingo Satou
  • Patent number: 6313485
    Abstract: A gate-controlled thyristor in which an IGBT in a first cell and a thyristor in a main cell are connected together in ouch a way that the first cell and the main cell form a lateral FET with a channel of a first conducting type. In an emitter zone of the thyristor, there is a layer embedded that increases the charge carrier recombination in order to reduce the start-up resistance of the gate-controlled thyristor. Trenches, filled with insulated gate electrodes, can be introduced into the lateral FET, so that the FET is a side wall FET.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Patent number: 6278140
    Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: August 21, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yuichi Harada, Noriyuki Iwamuro, Tadayoshi Iwaana
  • Patent number: 6271545
    Abstract: Both the blocking voltage as well as the sweep voltage of conventional thyristors exhibit a pronounced temperature behavior, whereby the corresponding voltage values can change by up to 15% within the relevant temperature range (5° C.-120° C.). In the proposed thyristor, the overhead triggering is compelled by the “punch through” effect that is independent of the temperature (expanse of the space charge zone allocated to the p-base/n-base junction 10) up to the neighboring n-base/p-emitter junction 11). Due to the laterally non-uniform distribution of the dopant in the n+ stop zone (7′) of the anode-side base (7), further, it is assured that the central thyristor region always ignites first. Sweep or punch through voltage is not dependent on the temperature in the asymmetrical thyristors.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: August 7, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Joachim Schulze
  • Patent number: 6258634
    Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 10, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 6236069
    Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: May 22, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
  • Patent number: 6180965
    Abstract: In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one conductivity type, gate regions 13 of the other conductivity type are formed at bottoms of the recessed portions, recessed portions 14 are formed at portions surrounded by adjacent gate regions, cathode short-circuit regions 15 of the other conductivity type are formed as an island at bottoms of the recessed portions to be extended to the surface of the silicon substrate. Cathode regions 17 extending up to the surface of the silicon substrate in succession to channel regions 16 surrounded by the cathode regions 13 and cathode short-circuit regions 15, are formed. A cathode electrode substrate 21 is formed to be contacted with the cathode short-circuit regions 15 and cathode regions 17.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: January 30, 2001
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 6172381
    Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed and isolated from another polysilicon structure lying in the same elevated plane. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A first transistor is provided which is disposed upon and within a silicon-based substrate. A primary interlevel dielectric is deposited across the transistor and the substrate. Polysilicon may then be deposited across the primary interlevel dielectric and doped using ion implantation. A second transistor may be formed upon and within a portion of the polysilicon layer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Daniel Kadosh
  • Patent number: 6147369
    Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: November 14, 2000
    Assignee: Winbond Electronics Corp.
    Inventors: Wei-Fan Chen, Fu-Chien Chiu, Ta-Lee Yu
  • Patent number: 6111278
    Abstract: Power semiconductor devices having discontinuous emitter regions therein include a semiconductor substrate containing therein a collector region of second conductivity type, a buffer region of first conductivity type which forms a first P-N junction with the collector region and a drift region of first conductivity type which forms a non-rectifying junction with the buffer region. A base region of second conductivity type is also provided in the drift region and forms a second P-N junction therewith. In addition, a base contact region of second conductivity type is provided in the base region of second conductivity type. The base contact region typically has a much higher second conductivity type doping concentration therein than the base region. A preferred emitter region is also provided in the substrate. This preferred emitter region comprises an emitter contact region which is entirely surrounded in the substrate by the highly doped base contact region and a carrier emitting region.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: August 29, 2000
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventor: Tae-Hoon Kim