Cathode Emitter Or Cathode Electrode Feature Patents (Class 257/152)
  • Patent number: 6111290
    Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.- silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: August 29, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Katsumi Nakamura
  • Patent number: 6054728
    Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: April 25, 2000
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yuichi Harada, Noriyuki Iwamuro, Tadayoshi Iwaana
  • Patent number: 5998811
    Abstract: A trench emitter controlled thyristor 30 having a collector layer 32, a drift layer 34, a body layer 36, and a floating layer 38. Each of the layers 32, 34, 36, and 38 contacts the adjacent layer(s). The floating layer 38 does not cover the entirety of the adjacent layer (the body layer 36) but at one of the lateral ends of the thyristor 30, an emitter 40 is formed. A gate area (or electrode) 43 is formed to span laterally across the thyristor 30. Additionally, trenches are formed into the lateral edges 44 of the body layer 36 and a portion of the drift layer 34. Within the trenches 44 are formed additional gate area 42 which runs for substantially the length of the thyristor 30. The gate 42 is kept electrically isolated from the remainder of the thyristor by an insulating region 46 directly over the body layer 36.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: December 7, 1999
    Assignee: Intersil Corporation
    Inventor: Qin Huang
  • Patent number: 5981984
    Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: November 9, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tadayoshi Iwaana, Yuichi Harada, Noriyuki Iwamuro
  • Patent number: 5977569
    Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: November 2, 1999
    Assignee: Allen-Bradley Company, LLC
    Inventor: Hsin-Hua P. Li
  • Patent number: 5939736
    Abstract: A semiconductor device for conducting a in current across a cathode electrode and an anode electrode, includes a thyristor formed of an n.sup.+ floating region connected electrically to the cathode electrode, a p.sup.+ anode connected electrically to the anode electrode, a p base, and an n.sup.- layer. A p.sup.+ diverter is provided inside and outside the p base region. The semiconductor device further includes a gate oxide film and a gate electrode for forming a channel region between the p base and each p.sup.+ diverter and between the n.sup.+ floating region and the n.sup.- layer. When the thyristor is turned off, the hole-current within the p base is split into each p.sup.+ diverter. A semiconductor device superior in controllable current is obtained.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: August 17, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tetsuo Takahashi
  • Patent number: 5936267
    Abstract: Surfaces of a second p base region 6 and an n emitter region 8 are covered with an insulating film 19 and the second p base region 6 and a first p base region 4 are connected partially below a gate electrode 10. In a conventional EST, a potential difference is obtained by hole current flowing in a Z direction to make the transition from an IGBT mode to a thyristor mode. However, since an n emitter region 8 becomes a potential almost equal to that of an n source region 7, hole current injected from a p emitter layer 1 causes the potential of the second p base region 6 to rise, making the prompt transition to the thyristor mode. Particularly, in the portion where the second p base region 6 and the first p base region 4 are in contact with each other, an inversion layer at the gate on time is short and small in resistance and does not touch an n base layer 3, thus electrons from the n source region 7 flow effectively into the n emitter region 8 and the on-state voltage is lowered.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: August 10, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5923055
    Abstract: The invention concerns a semiconductor component which can be controlled on the anode side and whose semiconductor body comprises a plurality of adjacent, parallel-connected unit cells having a thyristor structure. A lightly doped n-base region (3) is adjoined on both sides by highly doped p-regions constituting p-base region (2) and p-emitter region (4). The p-base region (2) is followed by a highly doped n-emitter (1) which contacts a cathode electrode (7). Integrated in the p-emitter region (4) is a first n-channel MOSFET (M1) which is connected in series with the thyristor structure by means of a floating electrode (FE). The drain electrode (5b) of the first MOSFET (M1) is provided with an outer anode (8) which has no contact with the p-emitter region (4). A second n-channel MOSFET (M2) is integrated between the n-base region (3) and the drain region (5b) of the first MOSFET (M1).
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 13, 1999
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventors: Heinrich Schlangenotto, Marius Fuellmann, Jacek Korec, Alexander Bodensohn
  • Patent number: 5894141
    Abstract: Semiconductor bipolar power devices comprise a control electrode for turning on or off a first source of charge carriers into the device and a p-n junction emitter remote from the first source and acting in correspondence with the condition of the first source. The p-n junction is a heterojunction where the bandgap of the semiconductor material of the emitter side of the junction is less wide than the bandgap of the material on the base side for reducing the emitter injection efficiency in comparison with an otherwise identical device having a homojunction emitter.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 13, 1999
    Assignee: Harris Corporation
    Inventor: Anup Bhalla
  • Patent number: 5894149
    Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.31 silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: April 13, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Katsumi Nakamura
  • Patent number: 5874751
    Abstract: An insulated gate thyristor is provided which includes a first-conductivity-type base layer of high resistivity, first and second second-conductivity-type base regions formed in a surface layer of a first major surface of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region, a gate electrode formed on surfaces of the first second-conductivity-type base region, the first-conductivity-type base layer, and the second second-conductivity-type base region, which surfaces are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region, an insulating film interposed between the gate electrode and these surface of the base regions and layer, a first main electrode in contact with both the first second-conductivity-type base region and the first-conduct
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: February 23, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Noriyuki Iwamuro, Yuichi Harada, Tadayoshi Iwaana
  • Patent number: 5856683
    Abstract: A MOS-gate switched power semiconductor component with a semiconductor body that has a number of unit cells arranged side-by-side and switched in parallel and consisting of a p-emitter zone adjacent to the anode, an adjoining, weakly doped n-base zone, then a p-base zone and an adjoining n-emitter zone. Incorporated in the n-emitter zone of the unit cells are pairs of p.sup.+ zones (5a, 5b) which, together with the n zone between them and an insulated gate situated above, form a lateral p-channel MOSFET (M1). The n-emitter zone (4) is equipped with a floating cathode contact (K') which at the same time constitutes the electrode of the p.sup.+ region serving as source. The p+ region serving as drain is connected to an external cathode (K), which has no contact with the n-emitter zone. Another MOSFET is formed by the surface region of the p-base zone (3) and the intervening region of the n-emitter zone (4b) together with an insulating gate.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: January 5, 1999
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventor: Heinrich Schlangenotto
  • Patent number: 5844258
    Abstract: An emitter switched thyristor has an enlarged safe operating range. A semiconductor substrate of a first conductivity type (a p-type) is provided and a semiconductor region of a second conductivity type (an n-type) is formed on the substrate. A well region of the first conductivity type is formed within the semiconductor region, and a plurality of well subregions of the second conductivity type are formed within the well region. The well subregions are all separated from each other by a separating portion of the well region. A plurality of electrode contacts are provided, including a gate electrode in contact with the well region and at least first and second cathode electrodes. The second cathode electrode is in contact with the separating portion of the well region.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: December 1, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwang-Hoon Oh
  • Patent number: 5844259
    Abstract: An MCT is formed as a four-layer device, using alternating cells of: (a) P diffusions in an N.sup.- wafer having lower N.sup.+ and P.sup.+ layers with N.sup.+ cathode regions in the P diffusions, and (b) shallow P.sup.+ diverter cells. A cathode electrode is connected to the N.sup.+ cathodes, but not to the P diffusions containing the N.sup.+ cathode regions. The alternating cells are arranged in checkerboard fashion with the cells of any given row having a narrow spacing to define a narrow turn-off channel and the rows being more widely spaced to define a conduction channel having a reduced inherent JFET resistance.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 1, 1998
    Assignee: International Rectifier Corporation
    Inventors: Daniel M. Kinzer, Weizuo Zhang
  • Patent number: 5831293
    Abstract: There is provided a semiconductor substrate which includes a pair of main surfaces, a first semiconductor layer of a first conductivity type adjacent to one of the main surface, a second semiconductor layer of a second conducting type of which impurity concentration is lower than that of the first semiconductor layer and which is adjacent to the first semiconductivity, a third semiconductor layer of the first conductivity type adjacent to the second semiconductor, and a fourth semiconductor of the second conductivity type of which impurity concentration is higher than that of the third semiconductor and which is adjacent to the other of the main surfaces and the third semiconductor.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: November 3, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Mizoguchi, Masahiro Nagasu, Hideo Kobayashi, Tsutomu Yatsuo
  • Patent number: 5831291
    Abstract: A semiconductor device comprises a plurality of IGBT-like cells arranged in groups on a single wafer of silicon. Each group of cells has a unified gate structure and a unified source structure electrically insulated therefrom but physically overlying it. The gate structure of each group of cells is brought via a removable link to a single gate electrode for the whole device, so that the gate connection to any group of cells may be broken by removing the link, thus disabling the corresponding group of cells. Also, each group of cells is provided separately with a built-in controlled shunt conductance between its source structure and its gate structure.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: November 3, 1998
    Assignee: Westinghouse Brake and Signal Holdings Limited
    Inventors: Michael J. Evans, Robert C. Irons
  • Patent number: 5793066
    Abstract: An insulated gate base resistance controlled thyristor with a high controllable current capability is described. The device has a high density of MOS-channels modulating the resistance of the base region of the NPN transistor of the thyristor structure. The higher MOS channel density is achieved by contacting directly only the N.sup.++ emitter and the P.sup.+ cells (and not the P base region of the NPN transistor) to the cathode electrode. The N.sup.++ cells (i.e. the P base regions each containing an N.sup.++ emitter) and the P.sup.+ cells are connected in certain regions under the MOS gate by a P.sup.- region to provide a higher base resistance when a positive bias is applied to the MOS gate, thereby facilitating latching of the thyristor. The added MOS gate controlled base resistance between cells allows the P base cells to be designed with smaller dimensions for high maximum controllable current without affecting latch-up capability.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: August 11, 1998
    Assignee: International Rectifier Corporation
    Inventor: Janardhanan S. Ajit
  • Patent number: 5757036
    Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: May 26, 1998
    Assignee: Harris Corporation
    Inventor: Victor Albert Keith Temple
  • Patent number: 5710445
    Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: January 20, 1998
    Assignee: Asea Brown Boveri AG
    Inventors: Friedhelm Bauer, Simon Eicher
  • Patent number: 5710443
    Abstract: A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 20, 1998
    Assignee: SGS-Thompson Microelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 5710444
    Abstract: The invention concerns a field-effect controlled semiconductor component with at least four regions of alternating opposite performance types: an anode-side emitter region, a first and a second base region connected to the emitter region, and a cathode-side emitter region; the cathode-side emitter region and the first base region from the source and drain of an MOS field effect transistor. The component also comprises an anode contact, a contact at the cathode-side emitter region and a control electrode contact of the MOS field effect transistor. The invention lies in the fact that a p+ region (36) which is adjacent to the cathode-side base region, separate, and accomodated in the anode-side n- base region (20), is connected via a separate component as a coupling element (80) with non-linear current/voltage characteristics to the cathode contact, the said region (36) being directly surrounded by the anode-side base region (20).
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: January 20, 1998
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventors: Horst Neubrand, Jacek Korec, Dieter Silber
  • Patent number: 5684306
    Abstract: An insulated gate thyristor is provided which includes a first-conductivity-type base layer having a high resistivity, a first and a second second-conductivity-type base region separately formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. A gate electrode is formed through an insulating film on exposed portions of the first second-conductivity-type base region, the first-conductivity-type base layer, and the second second-conductivity-type base region, which exposed portions are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. A first main electrode is held in contact with both the first second-conductivity-type base region and the first-conductivity-type source region.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: November 4, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5665987
    Abstract: In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed in the second gate. A MOS structure is formed on the second gate as a control gate electrode isolated therefrom. Since the channel integration density is high, the area efficiency increases. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed swtching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: September 9, 1997
    Assignees: Toyo Denki Seizo Kabushiki Kaisha, Takashige Tamamushi
    Inventors: Kimihiro Muraoka, Yoshinobu Ohtsubo, Toshio Higuchi, Makoto Iguchi, Takashige Tamamushi
  • Patent number: 5659185
    Abstract: Improved breakdown withstand capability is realized in a double gate insulated gate thyristor with low on-voltage in the thyristor operation mode and high-speed turn-off in the IGBT operation mode. Turn-off current through the lateral MOSFET using a second gate electrode is reduced, and breakdown withstand capability of the insulated gate thyristor is improved by inclusion of a gap in the (n) type source region, by contacting a part of the cathode directly to the (p) type base layer, and by connecting the bipolar transistor and the thyristor in parallel, for a part of the turn-off current to flow through the bipolar transistor to the cathode. A trench-type first gate electrode is preferred.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 19, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5652467
    Abstract: An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: July 29, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Hidekatsu Onose, Shuroku Sakurada
  • Patent number: 5644150
    Abstract: A double gate type insulated gate thyristor is provided which improves the breakdown withstand capability by turning on at low on-voltage by a thyristor operation mode and by turning off at high speed by an IGBT operation mode. In the insulated gate thyristor, a part of an n.sup.+ source region is removed and a p-base region is directly connected with a part of a cathode so as to connect a bipolar transistor with a main thyristor in parallel. A part of a switching-off current flows through the bipolar transistor to the cathode and the switching-off current which flows through a lateral MOSFET to the second gate electrode is reduced. By this configuration, the breakdown withstand capability is improved.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: July 1, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 5635734
    Abstract: An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: June 3, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Takayanagi, Hideo Kobayashi, Shuroku Sakurada, Hidekatsu Onose
  • Patent number: 5619047
    Abstract: A diode (1) is specified which has electron injection means on the anode-side principal surface (3). After the reverse-current peak has been traversed, said means inject electrons into the anode emitter. This compensates for holes and the danger of a dynamic field overshoot, which may result in an avalanche breakdown, is reduced. The electron injection means preferably comprise an n-channel MOS cell. High voltages and high dI/dt values can be safely handled with a diode according to the invention. A diode in accordance with the invention is preferably used as freewheeling diode in a converter circuit arrangement.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: April 8, 1997
    Assignee: Asea Brown Boveri AG
    Inventor: Friedhelm Bauer
  • Patent number: 5610415
    Abstract: In turn-off semiconductor components such as GTO thyristors, the semiconductor body can be locally overheated and destroyed as a consequence of inhomogeneities. The anode-side emitter is therefore doped with additional substances that locally compensate the emitter doping above the operating temperature and locally reduce the current amplification factor of the anode-side transistor structure. An increased turn-off current is thus achieved.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: March 11, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Joachim Schulze
  • Patent number: 5602405
    Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: February 11, 1997
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 5491351
    Abstract: A GTO having a cathode emitter (7) is specified, which cathode emitter has a low emission efficiency. This cathode emitter (7) provides a clearly increased resistance to the formation of current filaments. As a result, relatively high turn-off current densities can be reliably mastered. In addition, the fraction of the hole current in the total current is more than 10%. This is achieved, for example, by selecting the penetration depth as <1 .mu.m and the edge concentration as <10.sup.19 cm.sup.-3.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: February 13, 1996
    Assignee: ABB Management AG
    Inventors: Friedhelm Bauer, Peter Streit
  • Patent number: 5461242
    Abstract: In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate region of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed between the first and second gate regions. A MOS structure is formed on the second gate region as a insulated gate control gate region electrode isolated therefrom. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed switching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: October 24, 1995
    Assignee: Toyo Denki Seizo Kabushiki Kaisha
    Inventors: Kimihiro Muraoka, Yoshinobu Ohtsubo, Toshio Higuchi, Makoto Iguchi, Takashige Tamamushi
  • Patent number: 5455442
    Abstract: The performance of COMFET-based electrical switches may be improved by connecting a MOSFET substantially in parallel with the COMFET. In a monolithic embodiment, a MOSFET drain region may be added to a surface of a COMFET and shorted to the emitter region of the COMFET. The invention decreases the turn-off time of the COMFET, reduces the discontinuity at current direction reversal and increases the latch-up current of a semiconductor switch.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: October 3, 1995
    Assignee: Harris Corporation
    Inventors: John M. S. Neilson, Wolfgang F. W. Dietz
  • Patent number: 5444271
    Abstract: Base regions of a second conductivity type are formed and spaced apart from one another in a first major surface of a semiconductor substrate of a first conductivity type which functions as a drain region. Source regions of the first conductivity type are formed in each of the base regions and spaced apart from one another. Gate insulating films are formed on portions of the drain region which are located between adjacent source regions. Gates are formed on the gate insulating films. Source electrodes are formed such that each electrode short-circuits one-base region to the source regions formed in the base region. A first anode region of the second conductivity type is formed on a second major surface of the semiconductor substrate. A second anode region of the second conductivity type is formed on the first anode region. This second anode region is made of polycrystalline silicon of the second conductivity type and has an impurity concentration higher than that of the first anode region.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: August 22, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masashi Kuwahara
  • Patent number: 5426314
    Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: June 20, 1995
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Sohbe Suzuki
  • Patent number: 5387806
    Abstract: The semiconductor substrate of a GTO-Thyristor is structured at a cathode-side such that the cathode electrode lies in a first uppermost level of and in a second level lying there below. A gate contact lies in a third lowest level. Passivation layers extend only over the second and third levels. The cathode electrode also contacts the cathode emitter zone in the second level. It is overlapped there by the passivation layers.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: February 7, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventor: Guenther Franz
  • Patent number: 5387805
    Abstract: A readily manufacturable field controlled thyristor with a first semiconductor region of n-type conductivity, a second semiconductor region of p-type in contact with said first region, a void penetrating through said first and second semiconductor regions, a fourth semiconductor region of n-type forming a channel adjacent to said void, a fifth semiconductor region, of p-type, in contact with said third region. The device has a large tolerance for deviations in process parameter precision and accuracy, which enables the device to be produced at a low cost.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: February 7, 1995
    Inventors: Richard A. Metzler, Vladimir Rodov
  • Patent number: 5381025
    Abstract: An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T.sub.5) that can turn off the latched IGBT.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: January 10, 1995
    Assignee: Ixys Corporation
    Inventor: Nathan Zommer
  • Patent number: 5350935
    Abstract: A four-region semiconductor device (that is a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: September 27, 1994
    Assignee: Harris Corporation
    Inventor: Victor A. K. Temple
  • Patent number: 5336907
    Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: August 9, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Nakanishi, Yasunori Usui
  • Patent number: 5317172
    Abstract: A PNPN semiconductor device has an inner P-type region which includes at least one ridge which extends into its outer N-type region and terminates short of the outer boundary of the outer N-type region, the inner P-type region includes a formation which is substantially level with the outer boundary of the outer N-type region, and the device includes a terminal which contacts the outer N-type region and the formation of the inner P-type region.An alternative structure of the PNPN semiconductor device has an inner P-type region having at least one elongate sub-region, of higher conductivity than the remainder of the inner P-type region, lying along the junction between the inner P-type region and the outer N-type region, the formation which is substantially level with the outer boundary of the outer N-type region, and the terminal which contacts the formation and the outer N-type region.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: May 31, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen W. Byatt
  • Patent number: 5306930
    Abstract: An emitter switched thyristor with buried dielectric layer includes a contiguous P-N-P-N series of semiconductor regions between an anode contact and cathode contact. These regions correspond to an anode region of second conductivity type, a first base region of first conductivity type, a second base region of second conductivity type on the first base region, and a floating emitter region contacting the second base region and forming a P-N junction therewith. In addition, a field effect transistor is also provided between the cathode contact and the floating emitter for controlling turn-on and turn-off. An insulating region is also provided between the cathode region and the second base region and prevents the formation of a parasitic thyristor between the cathode contact and the anode contact. The insulating region preferably includes a buried dielectric layer selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: April 26, 1994
    Assignee: North Carolina State University at Raleigh
    Inventor: Bantval J. Baliga
  • Patent number: 5298769
    Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: March 29, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Mitsuhiko Kitagawa
  • Patent number: 5293054
    Abstract: An emitter switched thyristor without parasitic thyristor latch-up susceptibility includes a thyristor having an anode region, a first base region, a second base region in the first base region and an emitter region of first conductivity type in the second base region. An electrical connection is provided between the emitter region and the cathode contact by a field effect transistor in the first base region. The transistor is positioned adjacent the second base region and includes a source electrically connected to the emitter region by a metal strap on the surface of the substrate. The drain of the transistor is electrically connected to the cathode contact and has a conductivity type opposite the conductivity type of the first base region. Accordingly, the cathode contact and anode contact are not separated by a four layer parasitic thyristor. Parasitic latch-up operation is thereby eliminated.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: March 8, 1994
    Assignee: North Carolina State University at Raleigh
    Inventors: Mallikarjunaswamy S. Shekar, Bantval J. Baliga
  • Patent number: 5281833
    Abstract: An insulated gate control thyristor including an n-type base region, an insulating layer, gates formed on the insulating layer, first and second windows formed in the insulating layer, p-type emitter layers and n-type cathode layers diffused into the base region from the first windows, and p-type collector layers diffused into the base region from the second windows. The emitter layer and the collector layer are disposed in close proximity to each other under the gate so that a channel is formed which is conducted when the thyristor is turned off. The turn-off of the thyristor speeds up and becomes reliable, and the quality control of the process steps for fabricating the thyristor becomes easier.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: January 25, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 5210432
    Abstract: According to this invention, there is disclosed an insulated gate GTO thyristor comprising a pnpn structure including a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. The thyristor has a first gate electrode contacting the p-type base layer and a second gate electrode formed on a channel region of the p-type base layer through a gate insulating film. An n+-type layer of the n-type emitter layer immediately below a cathode electrode and an n--type layer of the n-type emitter layer contacting the channel region are formed in different manufacturing steps, and an emitter breakdown voltage and the threshold voltage of the second gate electrode are optimally set.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: May 11, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Shinohe, Masaki Atsuta, Akio Nakagawa