With Extended Latchup Current Level (e.g., Gate Turn Off "gto" Device) Patents (Class 257/147)
  • Patent number: 10446675
    Abstract: A High Electron Mobility Transistor comprising a source and a drain, a III-N buffer layer and a III-N barrier layer jointly forming a 2DEG in the buffer layer between the source and the drain, a first gate electrode configured to receive a gate bias voltage and a second gate electrode located between the drain and the first gate and conductively connected to the source via the 2DEG.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 15, 2019
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventor: Victor Sizov
  • Patent number: 10424565
    Abstract: A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 24, 2019
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Andreas Weimar, Frank Singer, Anna Kasprzak-Zablocka, Sabine vom Dorp
  • Patent number: 10388776
    Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Patent number: 10049912
    Abstract: A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Andre Brockmeier, Elmar Falck, Francisco Javier Santos Rodriguez, Holger Schulze
  • Patent number: 10006882
    Abstract: An example biosensor is provided and includes a semiconductor sensing element, a first electrode and a second electrode located on a first plane of the sensing element with a first electric field being applied thereacross, a third electrode located on a second plane of the sensing element parallel to and removed from the first plane with a second electric field being applied across the first electrode and the third electrode perpendicular to the first electric field, and a dielectric substrate having a first portion that constrains a fluid including an analyte on a surface of the sensing element, and a second portion that facilitates dielectric separation of the fluid from the electrodes. The mutually perpendicular electric fields facilitate adjusting a height of a fluid-sensor interface comprising an electrical double layer in the fluid enabling detection and characterization of the analyte.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 26, 2018
    Assignee: EnLiSense, LLC
    Inventors: Shalini Prasad, Sriram Muthukumar, Anjan Panneer Selvam
  • Patent number: 9941397
    Abstract: In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion is configured by a third trench and a fourth trench. A width of the second trench along an X direction is expanded more than the first trench positioned above the second trench. Along the X direction, the extent to which the second trench is expanded differs for the third trench and the fourth trench. Thus, a width of the lower portion of the trench differs along a Y direction, enabling reduced gate capacitance compared to uniform expansion along a transverse direction of the trench. Further, ON voltage may be reduced and switching capability may be improved.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 10, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Fujii, Seiji Momota
  • Patent number: 9910009
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 9905680
    Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 27, 2018
    Assignee: CSMC Technologies Fab1 Co., Ltd.
    Inventor: Shukun Qi
  • Patent number: 9825121
    Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Keiko Ariyoshi, Tatsuo Shimizu, Kazuto Takao, Takashi Shinohe
  • Patent number: 9791406
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 9761709
    Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 12, 2017
    Assignee: HRL Laboratories, LLC
    Inventor: Rongming Chu
  • Patent number: 9741836
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9732437
    Abstract: A low-resistance p-type SiC single crystal containing no inclusions is provided. This is achieved by a method for producing a SiC single crystal wherein a SiC seed crystal substrate 14 is contacted with a Si—C solution 24 having a temperature gradient in which the temperature falls from the interior toward the surface, to grow a SiC single crystal, and wherein the method comprises: using, as the Si—C solution, a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al, and making the temperature gradient y (° C./cm) in the surface region of the Si—C solution 24 satisfy the following formula (1): y?0.15789x+21.52632 (1) wherein x represents the Al content (at %) of the Si—C solution.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: August 15, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takayuki Shirai
  • Patent number: 9716140
    Abstract: Embodiments relate to a fluid sensor and a method for examining a fluid. A fluid sensor includes a substrate which comprises a recess for receiving a fluid to be examined, wherein the fluid sensor is implemented to detect electrical changes in the recess caused by the fluid to be examined.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 25, 2017
    Assignee: Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e. V.
    Inventor: Ignaz Eisele
  • Patent number: 9647058
    Abstract: A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q?0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Takashi Matsuura, Mitsuru Shimazu
  • Patent number: 9548400
    Abstract: A diode includes a semiconductor body, a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, a base region arranged between the first and second emitter regions and having a lower doping concentration than the first and second emitter regions, a first emitter electrode electrically coupled to the first emitter region, a second emitter electrode in electrical contact with the second emitter region, a control electrode arrangement comprising a first control electrode section and a first dielectric layer arranged between the first control electrode section and the semiconductor body, and at least one pn junction extending to the first dielectric layer, or arranged distant to the first dielectric layer by less than 250 nm. The breakdown voltage of the diode is adjusted by applying a control potential to the first control electrode section.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 17, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Joachim Weyers
  • Patent number: 9530844
    Abstract: A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 27, 2016
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 9515145
    Abstract: A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a first well region of a second conductivity type formed in the front surface of the drift layer, a second well region of the second conductivity type formed in the front surface of the drift layer, and a gate structure that is formed on the front surface of the drift layer and forms a channel in the first well region and a channel in the second well region. A channel resistance of the channel formed in the first well region has a temperature characteristic that the channel resistance decreases with increasing temperature and a channel resistance of the channel formed in the second well region has a temperature characteristic that the channel resistance increases with increasing temperature.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 6, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayuki Furuhashi, Hiroaki Okabe, Tomokatsu Watanabe, Masayuki Imaizumi
  • Patent number: 9496743
    Abstract: An electric field coupling type wireless power feed system including a power transmitting device and a power receiving device which is unlikely to be affected by a noise and which has a reduced size is provided. A capacitive coupling type wireless power feed system includes a power receiving device including a first electrode using an oxide semiconductor film, and a battery and a power transmitting device including a second electrode, wherein the battery is charged by a voltage generated based on an electric field generated between the first electrode and the second electrode. The charging of the battery may be stopped by applying a positive direct-current voltage from a charge control circuit to the first electrode.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Kamata
  • Patent number: 9443841
    Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lu-An Chen, Ya-Ting Lin, Tien-Hao Tang
  • Patent number: 9437590
    Abstract: An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: September 6, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chang-Tzu Wang
  • Patent number: 9397178
    Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 19, 2016
    Inventors: Jiajin Liang, Chun Wai Ng, Johnny Kin On Sin
  • Patent number: 9397207
    Abstract: An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (<250 ns). Additionally, series resistance of the device is reduced without comprising voltage blocking ability is achieved. Finally, a positive only gate drive means is taught as is a method to module the saturation current using the gate terminal.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 19, 2016
    Inventor: David Schie
  • Patent number: 9293578
    Abstract: Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 22, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
  • Patent number: 9276094
    Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 1, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shigeru Kusunoki
  • Patent number: 9082648
    Abstract: An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: July 14, 2015
    Assignee: Pakal Technologies LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydio, Vladimir Rodov
  • Patent number: 8963200
    Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jam-Wem Lee, Tzu-Heng Chang, Tsung-Che Tsai, Ming-Hsiang Song
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20140240025
    Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Applicant: PAKAL TECHNOLOGIES, LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Patent number: 8809904
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 19, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 8685800
    Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, James D. Burnett, Brad J. Garni, Thomas W. Liston, Huy Van Pham
  • Publication number: 20130341675
    Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Da-Wei LAI, Handoko LINEWIH
  • Patent number: 8604584
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 10, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroki Wakimoto, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Publication number: 20130320398
    Abstract: An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Da-Wei Lai
  • Patent number: 8575702
    Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 5, 2013
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
  • Patent number: 8552435
    Abstract: Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 8, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 8530930
    Abstract: In a semiconductor device including a plurality of insulated gate switching cells each of which has a gate electrode, an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, and a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, mutual conductance of each insulated gate switching cell is varied in accordance with the distance from the connection portion corresponding to the bonding position of the bonding wire so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 10, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Shinichi Yataka, Masatoshi Goto
  • Publication number: 20130161690
    Abstract: A semiconductor device contains a first conductive type semiconductor substrate, at least one cathode formed on one surface of the semiconductor substrate, an anode formed on the other surface of the semiconductor substrate, and a gate electrode electrically insulated from the cathode, formed on the one surface of the semiconductor substrate to control current conduction between the cathode and the anode. The semiconductor substrate has a thickness of less than 460 rm.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicant: NGK INSULATORS, LTD.
    Inventor: NGK INSULATORS, LTD.
  • Publication number: 20130153957
    Abstract: A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Kun-Hsien Lin, Che-Hao Chuang, Ryan Hsin-Chin Jiang
  • Publication number: 20130001640
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Patent number: 8217420
    Abstract: According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second conductivity-type collector layer opposite to a first conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first conductivity-type emitter layer and a second conductivity-type base layer in a surface of the first conductivity-type base layer and insulated from a gate electrode in the region. The first conductivity-type second semiconductor layer extends from the surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 8110852
    Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Iwamatsu
  • Publication number: 20120018737
    Abstract: Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Publication number: 20120018738
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: CREE, INC.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 7999285
    Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 16, 2011
    Assignee: Dongby Hitek Co., Ltd.
    Inventor: Sang Yong Lee
  • Patent number: 7968940
    Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Anpec Electronics Corporation
    Inventor: Florin Udrea
  • Patent number: 7943956
    Abstract: A housing for a semiconductor device is disclosed. In an exemplary embodiment of the present invention, the housing comprises a semiconductor substrate that is arranged between two contact elements, one contact element forming an anode contact element and another contact element forming a cathode contact element, the semiconductor substrate having, on at least one surface, a gate electrode that is contacted by a gate contact element, the first contact element forming a surface arranged across from the gate electrode and at a distance from the gate electrode. Also included is at least one driver unit for generating a gate current, the driver unit comprising a first terminal that is contacted with the gate contact element, and a second terminal that is contacted with a first of the two contact elements.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 17, 2011
    Inventors: Rik W. De Doncker, Peter Koellensperger
  • Publication number: 20110073906
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla
  • Patent number: RE44547
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, John M. Parsey, Peter J. Zdebel, Gordon M. Grivna
  • Patent number: RE45365
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Components Industries
    Inventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna