Gate Region Or Electrode Feature Patents (Class 257/153)
  • Patent number: 10468555
    Abstract: A method for producing a semiconductor body is disclosed. In an embodiment, the method includes providing a semiconductor body, applying a first mask layer and a second mask layer to the semiconductor body and forming at least one second mask opening in the second mask layer and at least one recess in the semiconductor body in a region of the at least one first mask opening in the first mask layer, wherein the recess comprises a side face and a bottom face and the recess forms an undercut with the second mask opening. The method further includes applying a passivation layer unpatterned to the second mask layer and to the side face and the bottom face of the at least one recess and removing the passivation layer so that the passivation layer remains at least in part on the side face of the at least one recess.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 5, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Franz Eberhard
  • Patent number: 10347715
    Abstract: A semiconductor device includes a drift layer formed of a first conductive type semiconductor material, a MOSFET part including a p-type base layer provided on a front surface of the drift layer, a first n-type buffer layer provided on a reverse side of the drift layer, and a second n-type buffer layer provided on a reverse side of the first n-type buffer layer and having a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of 1.0×1012 cm?2 or less.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Tetsuo Takahashi, Mitsuru Kaneda, Ryu Kamibaba, Koichi Nishi
  • Patent number: 10153764
    Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder
  • Patent number: 9306048
    Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n? layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: April 5, 2016
    Assignee: Pakal Technologies LLC
    Inventors: Richard A Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Patent number: 8878290
    Abstract: A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: November 4, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Narumasa Soejima
  • Patent number: 8829524
    Abstract: An exemplary thin film transistor array substrate (200) includes a substrate (210) and a gate electrode (220) formed on the substrate. The gate electrode includes an adhesive layer (226) formed on the substrate, a conductive layer (224) formed on the adhesive layer and a barrier layer (222) formed on the conductive layer, the adhesive layer and the barrier layer both have sandwich structures. A central core of the adhesive layer, the conductive layer, and a central core of the barrier layer are made of a same material.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: September 9, 2014
    Assignee: Innolux Corporation
    Inventor: Shuo-Ting Yan
  • Patent number: 8809915
    Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining S. Yang
  • Patent number: 8754443
    Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Chandra Mouli
  • Patent number: 8748916
    Abstract: A light emitting device includes a conductive substrate, a plurality of light emitting cells disposed on the conductive substrate, wherein each of the plurality of light emitting device cells includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, a protective layer disposed to cover a side of the first semiconductor layer and a side of the active layer, and a first electrode for connecting the second semiconductor layers of more than one of the light emitting cells to each other, wherein the protective layer includes protruding portions extending to an inside of each of the light emitting cells from the side of the first semiconductor layer and the side of the active layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8507991
    Abstract: A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 13, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Kai Han, Shijie Chen, Xiaolei Wang, Dapeng Chen
  • Patent number: 8476674
    Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining Yang
  • Patent number: 8445965
    Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8344415
    Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: January 1, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Holger Ruething, Frank Pfirsch, Armin Willmeroth, Frank Hille, Hans-Joachim Schulze
  • Patent number: 8253163
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
  • Patent number: 8247878
    Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Yul Lee
  • Patent number: 8217456
    Abstract: Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8164111
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
  • Patent number: 8093622
    Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani
  • Patent number: 8058694
    Abstract: In a semiconductor device, such as a MOSFET or the like, which is a high-frequency LSI achieving a low noise figure and a high maximum oscillation frequency and which has unit cells with a ring-shaped gate electrode arranged in an array, gate drawing wires connecting together the gate electrode and gate contact pad portions are arranged on a region excluding a drain region and a source region, that is, on an isolation region. Bending portions of the ring-shaped gate electrode are all formed on the isolation region. This therefore permits an improvement in high frequency characteristics such as noise, the maximum oscillation frequency, and the like while eliminating unnecessary gate capacity addition, and also permits small characteristic variation even if a machining shape of the bending portions of the gate electrode is unstable.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: November 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Hiroshi Shimomura
  • Patent number: 7915713
    Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Juergen Faul, Juergen Holz
  • Patent number: 7842572
    Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-myeong Jang, Yong-chul Oh, Makoto Yoshida
  • Patent number: 7816706
    Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: October 19, 2010
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Peter Streit
  • Patent number: 7759194
    Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: July 20, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yi-Peng Chan, Sheng-He Huang, Zhen Yang
  • Patent number: 7732833
    Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Hiroto Yamagiwa, Takashi Saji
  • Patent number: 7705368
    Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujifilm Corporation
    Inventors: Vladimir Rodov, Hidenori Akiyama
  • Patent number: 7671441
    Abstract: A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface of the trench. The spacer gate of each gate trench may also include a layer of silicide along outer surfaces thereof. The semiconductor body may include a channel region and each gate trench may extend through the channel region and into the semiconductor body. Formed at the bottom of each gate trench within the semiconductor body may be a tip implant of the same conductivity as the semiconductor body. In addition, a deep body implant of the same conductivity as the channel region may be formed at the base of the channel region.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: March 2, 2010
    Assignee: International Rectifier Corporation
    Inventor: Timothy Henson
  • Patent number: 7652308
    Abstract: Semiconductor devices having a gate-all-around (GAA) structure capable of higher operating performance may be provided. A semiconductor device may include a semiconductor substrate, at least one gate electrode, and at least one gate insulating layer. The semiconductor substrate may have a body, at least one supporting post protruding from the body, and at least one pair of fins separated from the body, wherein both ends of each fin of the at least one pair of fins are connected to and supported by the at least one supporting post. The at least one gate electrode may enclose a portion of at least one fin of the at least one pair of fins of the semiconductor substrate, and may be insulated from the semiconductor substrate. The at least one gate insulating layer may be interposed between the at least one gate electrode and the at least one pair of fins of the semiconductor substrate.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: January 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Dong Park, Suk-Pil Kim
  • Patent number: 7582939
    Abstract: The invention relates to a semiconductor diode, an electronic component and to a voltage source converter. According to the invention, the semiconductor diode having at least one pn-transition can be switched between a first state and a second state. In comparison to the first state, the second state has a greater on-state resistance and a smaller accumulated charge, and the pn-transition is capable of blocking both in the first state as well as in the second state with at least one predetermined blocking ability. An MOS-controlled diode is hereby obtained in which the transition from the on-state to the blocking state is simplified and is thus not critical with regard to the temporal sequence of the control pulses.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: September 1, 2009
    Assignee: Siemens Aktiengesellschaft
    Inventors: Mark-Matthias Bakran, Hans-Günter Eckel
  • Patent number: 7560773
    Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Tanaka
  • Patent number: 7465966
    Abstract: A new film formation method that makes it possible to form a film with a little concentration of contaminants from a material and to form a film on a low heat-resistant member is proposed. Further, a method for forming a film that can keep semiconductor properties is proposed. In the film formation method of the present invention, a first film that is to be a target is formed by employing plasma CVD, and the first film is sputtered, thereby forming the second film on a surface of the substrate to be processed in one chamber. By employing the film formation method of the present invention for a protective film of a semiconductor element, deterioration of a semiconductor device can be controlled.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: December 16, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Taketomi Asami, Kunihiko Fukuchi, Satoshi Toriumi
  • Patent number: 7397126
    Abstract: The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is formed so as to surround a periphery of the source electrode 4.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 8, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Tomoki Kato
  • Patent number: 7385249
    Abstract: A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedure. The first, or underlying silicon layer of the composite silicon layer, is deposited using a first silane flow rate which results in a silicon layer offering good performance characteristics but comprised with large silicon bumps. The second or overlying silicon layer of the composite silicon layer, is next deposited using a second silane flow rate, with the second silane flow greater than the silane flow used for the underlying silicon layer. The second silicon layer is formed with silicon bumps smaller in size than the silicon bumps of the first silicon layer.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Shih-I Yang
  • Patent number: 7262442
    Abstract: A triac including on its front surface side an autonomous starting well of the first conductivity type containing a region of the second conductivity type arranged to divide it, in top view, into a first and a second well portion, the first portion being connected to a control terminal and the second portion being connected with said region to the main front surface terminal.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: August 28, 2007
    Assignee: STMicroelectronics S.A.
    Inventor: Samuel Menard
  • Patent number: 7180102
    Abstract: A fusible link formed on a semiconductor substrate. The fusible link comprises a silicide layer overlying a polysilicon layer. The fusible link is programmed to an open state by passing a current therethrough that opens the polysilicon and the silicide layers.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 20, 2007
    Assignee: Agere Systems Inc.
    Inventor: Frank Yauchee Hui
  • Patent number: 7155684
    Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Keiichi Kusumoto
  • Patent number: 7135367
    Abstract: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: November 14, 2006
    Assignee: Fujitsu Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 7135717
    Abstract: The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electrode, a source electrode, and a drain electrode of each of which are formed on a semiconductor. The source electrode and the drain electrode are connected with the earth as well as are disposed in parallel to each other, and the gate electrode is formed between the source electrode and the drain electrode, and both the ends of the gate electrode are connected to the first input-output terminal 1 and the second input-output terminal.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: November 14, 2006
    Assignee: Nec Electronics Corporation
    Inventor: Hiroshi Mizutani
  • Patent number: 7064359
    Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: June 20, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidetoshi Ishida, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 6982432
    Abstract: A touch type liquid-crystal display device has a liquid-crystal display panel having flexibility, a touch panel provided to adhere closely to a back side, opposite to a visual side, of the liquid-crystal display panel, and electrodes disposed to be opposite to each other through a gap. The electrodes are capable of coming into partial contact with each other by a pressing force to thereby detect an input position.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: January 3, 2006
    Assignee: Nitto Denko Corporation
    Inventors: Seiji Umemoto, Tomonori Noguchi, Tadayuki Kameyama, Kiichi Shimodaira, Hideo Sugawara, Hidehiko Andou
  • Patent number: 6943382
    Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: September 13, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Yamaguchi, Kenji Oota
  • Patent number: 6921943
    Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (?-field) results from the changing dopant concentration. The creation of this ?-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: July 26, 2005
    Assignee: GlobiTech Incorporated
    Inventors: Danny Kenney, Keith Lindberg, Curtis Hall, G. R. Mohan Rao
  • Patent number: 6894319
    Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: May 17, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takashi Kobayashi, Tatsuhiko Fujihira, Hitoshi Abe, Yasushi Niimura, Masanori Inoue
  • Patent number: 6838321
    Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 4, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsuru Kaneda, Hideki Takahashi
  • Publication number: 20040206976
    Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.
    Type: Application
    Filed: May 14, 2004
    Publication date: October 21, 2004
    Inventors: Anant Agarwal, Sei-Hyung Ryu, John W. Palmour
  • Patent number: 6800897
    Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and first and second transition regions of first conductivity type that extend between the drift region and a first surface of the semiconductor substrate. Each of the first and second transition regions has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface. First and second shielding regions of second conductivity type are provided in the drift region and define respective P-N junctions with the first transition region. The shielding regions extending laterally towards each other in a manner that constricts a neck of the first transition region to a minimum width at a second depth relative to the first surface. An anode electrode is provided. The anode electrode that extends on the first surface of the semiconductor substrate and defines a Schottky rectifying junction with the second transition region.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: October 5, 2004
    Assignee: Silicon Semiconductor Corporation
    Inventor: Bantval Jayant Baliga
  • Patent number: 6790713
    Abstract: A semiconductor device having a thyristor is manufactured and arranged in a manner that reduces or eliminates difficulties commonly experienced in the formation and implementation of such devices. According to an example embodiment of the present invention, a thyristor (e.g., a thin capacitively-coupled thyristor) is formed having some or all of the body of the thyristor formed inlayed in a semiconductor device substrate. A trench is provided in the substrate, and a semiconductor material is formed in the trench. One or more layers of material are formed in the trench and used to form a portion of a body of the thyristor. The thyristor is formed having adjacent regions of different polarity, wherein at least one of the adjacent regions includes a portion of the semiconductor material and at least one of the adjacent regions includes a portion of the substrate.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 14, 2004
    Assignee: T-Ram, Inc.
    Inventor: Andrew Horch
  • Patent number: 6780532
    Abstract: Disclosed is a photodiode detector including: an InP substrate; a u-In0.53Ga0.47As layer grown and stacked on the InP substrate; an u-Inp layer stacked on an upper portion of the u-In0.53Ga0.47As layer; a SiNx insulation layer stacked on an upper portion of u-Inp layer; an additional insulation layer stacked on an upper portion of the SiNx insulation layer; a P-InP layer formed by Zn diffusing on an u-Inp layer portion below an opening formed on a predetermined position between the additional insulation layer and the SiNx insulation layer; a P-metal layer positioned on an upper portion of the additional insulation layer; and an N-metal layer formed on a lower portion of the InP substrate together with a non-reflection layer. The photodiode detector of the present invention, forms BCB material having a low dielectric constant, which is relatively thick, on the upper portion of the SiNx insulation layer, thereby obtaining the desired capacitance.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Kee Yang, Jea-Myung Baek
  • Patent number: 6774434
    Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond J. E. Hueting, Jan W. Slotboom, Petrus H. C. Magnee
  • Patent number: 6727526
    Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Josef Niedernostheide, Hans-Joachim Schulze
  • Patent number: 6690039
    Abstract: A semiconductor device is adapted to inhibit the formation of a parasitic MOS-inversion channel between an emitter region and a gated base in a capacitively-coupled thyristor device. According to an example embodiment of the present invention, a thyristor having first and second base regions coupled between emitter regions is gated, via one of the base regions, to a control port. The control port exhibits a workfunction between the control port and the base region that inhibits the formation of a conductive channel between the base region and an adjacent emitter region, such as when the semiconductor device is in a standby and/or a read mode for memory implementations. The workfunction is selected such that the parasitic MOS-inversion channel would turn on is sufficiently high to enable the operation of the device at voltages that are optimized for a particular implementation while remaining below VT.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: February 10, 2004
    Assignee: T-Ram, Inc.
    Inventors: Farid Nemati, Andrew Horch, Scott Robins