Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

Abstract: A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second complementary conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode, and the front-side base region is electrically connected to a front-side electrode. A turn-on structure, which is an emitter structure of the second conduction type, is embedded into the front-side base region and/or rear-side base region and is covered by the respective electrode and is electrically contacted with the electrode placed on the base region respectively embedding it. It can be turned on by a trigger structure which can be activated by an electrical turn-on signal. In the activated state, the trigger structure injects an electrical current surge into the semiconductor body, which irreversibly destroys a semiconductor junction.

Abstract: A semiconductor device includes a region of semiconductor material of a first conductivity type and having a first major surface. A body region of a second conductivity type opposite to the first conductivity type is in the region of semiconductor material. The body region includes a stripe region; a first segment in the stripe region and having a first peak dopant concentration, a first depth into the region of semiconductor material, and a first length along the first major surface; and a second segment in the stripe region laterally adjacent to the first segment, adjacent to the first major surface, and having a second peak dopant concentration, a second depth into the region of semiconductor material, and a second length along the first major surface. A source region of the first conductivity type is in the first segment but not in at least part of the second segment.

Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.

Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.

Abstract: A semiconductor apparatus includes a semiconductor substrate. Semiconductor substrate includes an active region and a peripheral region surrounding active region. Semiconductor substrate has a front surface and a back surface. A semiconductor device includes an n? drift region and a p+ collector layer. Peripheral region includes n? drift region and a p+ back surface peripheral layer. P+ back surface peripheral layer is provided on the back surface side of n? drift region. A first hole concentration in p+ back surface peripheral layer is higher than a second hole concentration in p+ collector layer. The short-circuit capability of semiconductor apparatus is improved.

Abstract: A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.

Abstract: The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first semiconductor region 20 is formed on a substrate, and a second electroconductive type second semiconductor region 22, a second electroconductive type third semiconductor region 23, designated as an anode, and a first electroconductive type fourth semiconductor region 24, designated as an anode gate, are formed on the surface layer part of the first semiconductor region. Also, a first electroconductive type fifth semiconductor region 26, designated as a cathode, and a second electroconductive type sixth semiconductor region 25, designated as a cathode gate, are formed on the surface layer part of the second semiconductor region.

Abstract: Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined compositions of the tantalum carbide nitride material by controlling the deposition temperature and the flow rate of a nitrogen-containing gas during a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating the substrate to a temperature within a process chamber, and exposing the substrate to a nitrogen-containing gas and a process gas containing a tantalum precursor gas while depositing a tantalum carbide nitride material on the substrate.

Abstract: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure.

Abstract: In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.

Abstract: A surface-emitting type device includes a substrate including a first face, a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, and a third face that is tilted with respect to the second face and has a plane index equal to the plane index of the first face, an emission section formed above the first face, and a rectification section formed above each of the second face and the third face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type formed above the second face, and a second semiconductor layer of the first conductivity type formed continuously with the first semiconductor layer above the third face, at least a portion of the first semico

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.

Abstract: A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.

Abstract: A vertical power semiconductor component, e.g. a diode or an IGBT, in which there are formed, on the rear side of a substrate, a rear side emitter or a cathode emitter and, over that, a rear side metal layer that at least partly covers the latter, is defined by the fact that, in the edge region of the component, provision is made of injection attenuation means for reducing the charge carrier injection from the rear side emitter or the cathode emitter into said edge section.

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract: A method is disclosed for creating an emitter having a flat cathode emission surface: First a protective layer that is conductive is formed on the flat cathode emission surface. Then an electronic lens structure is created over the protective layer. Finally, the protective layer is etched to expose the flat cathode emission surface.

Abstract: An emitter includes an electron supply and a tunneling layer disposed on the electron supply. A cathode layer is disposed on the tunneling layer. A conductive electrode has multiple layers of conductive material. The multiple layers include a protective layer disposed on the cathode layer. The conductive electrode has been etched to define an opening thereby exposing a portion of the cathode layer.

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer. A conductive layer is partially disposed on the cathode layer and partially on the insulator layer if present. The conductive layer defines an opening to provide a surface for energy emissions of electrons and/or photons. Preferably but optionally, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: An emitter has an electron supply layer and a silicon-based dielectric layer formed on the electron supply layer. The silicon-based dielectric layer is preferably less than about 500 Angstroms. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the silicon-based dielectric layer is formed. A cathode layer is formed on the silicon-based dielectric layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: An impurity precipitation region is formed by introducing an impurity, e.g., oxygen, into a silicon substrate or a silicon layer and thermally treating it, and performing high selectivity anisotropic etching with the precipitation region used as a micro mask. Thus, a cone (conic body or truncated conic body having an annular leading end) having a very sharp and slender needle shape with an aspect ratio of about 10 and a diameter of about 10 nm to 30 nm in the vicinity of its leading end is obtained with the micro mask used as the top. By forming an insulation layer and a drive electrode such as a gate electrode around the cone, the cone can be used for a field emission device, a single electron transistor, a memory device, a high frequency switching device, a probe of a scanning type microscope or the like.

Abstract: A wafer comprising a semiconductor layer formed on a substrate is diced on the back surface of the substrate to a depth of about ¾ thickness of the substrate. Thus a separation groove 21 is formed in a direction of a dicing line. A groove 22 is formed at the portion of the semiconductor layer corresponding to the groove 21. The groove 22 reaches the substrate. The back surface 11b of the substrate 11 is polished until the substrate become a lamella having only a trace of the groove 22. A metal layer 10 is formed by depositing aluminum (Al) so as to cover the entire back 11b of the substrate 11, and a groove 23 formed at the portion of the metal layer corresponding to the groove 21. An adhesive sheet 24 is adhered on an electrode pad 20. A scribe line is formed by scribing the metal layer 10 along the groove 23. The wafer is loaded by a roller in a breaking process. Accordingly, a wafer having the metal layer on the back surface 11b of the substrate can be obtained.

Abstract: A semiconductor thyristor device incorporates buried regions to achieve low breakover voltage devices, and the buried regions are offset laterally with respect to the emitter regions. The low voltage thyristor devices can be incorporated into five-pin protection modules for protecting customer circuits.

Abstract: An IGBT has parallel spaced trenches lined with gate oxide and filled with conductive polysilicon gate bodies. The trenches extend through a P− base region which is about 7 microns deep. A deep narrow N+ emitter diffusion is at the top of the trench and a shallow P+ contact diffusion extends between adjacent emitter diffusions. The N+ emitter diffusions are arranged to define a minimum RB′. The trenches are sufficiently deep to define long channel regions which can withstand a substantial portion of the blocking voltage of the device. A second blanket emitter implant and diffusion defines a shallow high concentration emitter diffusion extension at the top of the die for improved contact to the emitter diffusions.

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions.

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.

Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

Abstract: A wafer comprising a semiconductor layer formed on a substrate is diced on the back surface of the substrate to a depth of about ¾ thickness of the substrate. Thus a separation groove 21 is formed in a direction of a dicing line. A groove 22 is formed at the portion of the semiconductor layer corresponding to the groove 21. The groove 22 reaches the substrate. The back surface 11b of the substrate 11 is polished until the substrate become a lamella having only a trace of the groove 22. A metal layer 10 is formed by depositing aluminum (Al) so as to cover the entire back 11b of the substrate 11, and a groove 23 formed at the portion of the metal layer corresponding to the groove 21. An adhesive sheet 24 is adhered on an electrode pad 20. A scribe line is formed by scribing the metal layer 10 along the groove 23. The wafer is loaded by a roller in a breaking process. Accordingly, a wafer having the metal layer on the back surface 11b of the substrate can be obtained.

Abstract: A field emission display has electron emitters that are current-limited by implanting in a silicon layer only enough ions to produce a desired current, and then forming emitters from the silicon layer by isotropic etching.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area as compared with a conventional lateral power MOSFET with a withstand voltage lower than 80 V. The semiconductor device may include a shallow and narrow trench formed in a substrate with small spacing, a drift region that is an n diffusion region formed around the trench, a gate oxide film having a uniform thickness of about 0.

Abstract: An emitter has an electron supply layer and a tunneling layer formed on the electron supply layer. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the tunneling layer is formed. A cathode layer is formed on the tunneling layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: An emitter has an electron supply layer and a silicon-based dielectric layer formed on the electron supply layer. The silicon-based dielectric layer is preferably less than about 500 Angstroms. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within in which the silicon-based dielectric layer is formed. A cathode layer is formed on the silicon-based dielectric layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.