Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: A power transistor comprising a collector region formed in a semiconductor substrate, a base region formed within the collector region, and a hoop-shaped emitter region formed within the base region. The hoop-shaped emitter region divides the base region into an external section and at least one internal section surrounded by the emitter region on the substrate surface, the external and internal base sections being connected within the substrate. A base contact is formed on the surface of each internal base section surrounded by the emitter region. By this design, the electric current is more uniform within the emitter region, and safe operating area (SOA) destruction can be prevented. The invention is also directed to semiconductor integrated circuit devices using the above power transistor, and a method of forming the same.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: A method for fabricating a field emission device (200) includes the steps of forming on the surface of a substrate (110) a cathode (112), forming on the cathode (112) a dielectric layer (114), forming an emitter well (115) in the dielectric layer (114), forming within the emitter well (115) an electron emitter structure (118) having a surface (123), forming on a portion of the dielectric layer (114) a gate electrode (116), depositing on the dielectric layer (114) a sacrificial layer (210), thereafter depositing on the surface (123) of the electron emitter structure (118) a coating material (220, 320, 420) that has an emission-enhancing material, and then removing the sacrificial layer (210).

Abstract: An integrated structure is made in a chip of semiconductor material inside an insulated N type region extending from a surface of the chip. The structure comprises a Zener diode formed by a P type first region extending from the surface inside the insulated region and by a second region of type N extending from the surface inside the first region. These regions form between themselves a buried junction, in which the structure further includes a lateral bipolar transistor having an emitter region provided by the first region.

Abstract: A bipolar transistor includes an emitter, a base, a collector, an additional base semiconductor region having the same conductivity type as the base, arranged at the emitter and constituting a connection with the emitter. A first electrical connection connects the additional base semiconductor region with the base, thereby short-circuiting the additional base semiconductor region relative to the base, such that the additional base semiconductor region and base together constitute a combined base of the transistor. A further semiconducting collector region has the same conductivity type as the collector. A second electrical connection connects the further semiconductor connecting region and the collector, thereby short-circuiting the further semiconducting collector region and the collector, such that the additional semiconducting collector region and the collector together constitute a combined collector of the transistor.

Abstract: A semiconductor device for conducting a in current across a cathode electrode and an anode electrode, includes a thyristor formed of an n.sup.+ floating region connected electrically to the cathode electrode, a p.sup.+ anode connected electrically to the anode electrode, a p base, and an n.sup.- layer. A p.sup.+ diverter is provided inside and outside the p base region. The semiconductor device further includes a gate oxide film and a gate electrode for forming a channel region between the p base and each p.sup.+ diverter and between the n.sup.+ floating region and the n.sup.- layer. When the thyristor is turned off, the hole-current within the p base is split into each p.sup.+ diverter. A semiconductor device superior in controllable current is obtained.

Abstract: The operating characteristics of emitter-switched thyristors (1) are improved by the addition of a floating ohmic contact (14) over adjacent regions of n+ and p+ type (15,16). In a lateral device, the floating ohmic contact (14) and the adjacent regions of n+ and p+ type (15,16) are provided between the anode region (4) and the cathode region (8,9,10). The device has enhanced turn-on characteristics with a high breakdown voltage and high current density capabilities.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: Semiconductor bipolar power devices comprise a control electrode for turning on or off a first source of charge carriers into the device and a p-n junction emitter remote from the first source and acting in correspondence with the condition of the first source. The p-n junction is a heterojunction where the bandgap of the semiconductor material of the emitter side of the junction is less wide than the bandgap of the material on the base side for reducing the emitter injection efficiency in comparison with an otherwise identical device having a homojunction emitter.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N.sup.+ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N.sup.+ emitter, the potential of the N.sup.+ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P.sup.+ cathode is such that punch-through occurs in these regions.

Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.

Abstract: A diode (1) is specified which has electron injection means on the anode-side principal surface (3). After the reverse-current peak has been traversed, said means inject electrons into the anode emitter. This compensates for holes and the danger of a dynamic field overshoot, which may result in an avalanche breakdown, is reduced. The electron injection means preferably comprise an n-channel MOS cell. High voltages and high dI/dt values can be safely handled with a diode according to the invention. A diode in accordance with the invention is preferably used as freewheeling diode in a converter circuit arrangement.

Abstract: A bidirectional Shockley diode includes an N-type layer sandwiched between two P-type layers. A first N-type region in the P-type region extends over substantially one half of the upper surface. A second N-type region extends in the P-type layer substantially over one half of the lower surface. Each first and second region protrudes with respect to the median plane of the component by a length r such that ratio r/e is smaller than 0.5, e being the thickness of the component.

Abstract: An integrated semiconductor device having a thyristor includes outer npn-transistors, outer pnp-transistors, and an inner npn-transistor. The outer pnp-transistors and the inner npn-transistor are interconnected so as to form a thyristor to allow the inner transistor to be biased into conduction. Furthermore, a current flow takes place via the outer npn-transistors and the inner npn-transistor. The integrated semiconductor device having a thyristor minimizes interference produced in neighboring components.

Abstract: A heavily doped n-type semiconductor region is selectively formed at a surface where a p-type semiconductor layer and an n-type semiconductor layer abut each other. Injection of holes from the p-type semiconductor layer to the n-type semiconductor layer is attained by holes which selectively flow in a region where the heavily doped n-type semiconductor region is not present. The high concentration of the holes at such a region exerts a predominant influence in the device when a collector current is small, whereby flow of the collector current is facilitated and the ON-resistance of the device is suppressed. On the other hand, when the collector current is large, under a dominantly strong influence of a fact that flow of the collector current is allowed only through the region where the heavily doped n-type semiconductor region is not provided, the flow of the collector current is suppressed, and hence, the durability against destruction of the device is enhanced.

Abstract: In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. In some embodiments, the device has two gate drives and is a four terminal device. In other embodiments, the device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: A GTO having a cathode emitter (7) is specified, which cathode emitter has a low emission efficiency. This cathode emitter (7) provides a clearly increased resistance to the formation of current filaments. As a result, relatively high turn-off current densities can be reliably mastered. In addition, the fraction of the hole current in the total current is more than 10%. This is achieved, for example, by selecting the penetration depth as <1 .mu.m and the edge concentration as <10.sup.19 cm.sup.-3.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. The device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: A vertical type construction transistor is provided wherein a bump electrode is disposed immediately on the junction portions formed on the surface of the semiconductor basic plate so as to effect a radiating operation with the electrode being connected to a heat sink. As a result the heating of the junction portion formed on the basic plate surface is effectively released, the inductance of the outgoing line is reduced, and the power amplification used in the microwave band is put to practical use.

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract: An emitter switched thyristor with buried dielectric layer includes a contiguous P-N-P-N series of semiconductor regions between an anode contact and cathode contact. These regions correspond to an anode region of second conductivity type, a first base region of first conductivity type, a second base region of second conductivity type on the first base region, and a floating emitter region contacting the second base region and forming a P-N junction therewith. In addition, a field effect transistor is also provided between the cathode contact and the floating emitter for controlling turn-on and turn-off. An insulating region is also provided between the cathode region and the second base region and prevents the formation of a parasitic thyristor between the cathode contact and the anode contact. The insulating region preferably includes a buried dielectric layer selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.

Abstract: A bidirectional two-terminal ungated thyristor (9) having two wide-base portions (25, 27). The bidirectional two-terminal ungated thyristor (9) has a first semiconductor device having a first narrow-base portion (28) in series with a first wide-base portion (25), and a second semiconductor device having a second narrow-base portion (26) in series with a second wide-base portion (27). A width of the first wide base portion (25) and a width of the second wide base portion (27) are decreased to decrease a total base width. The first and second wide-base portions (25, 27) having a decreased width produce a low forward voltage drop across the bidirectional two-terminal ungated thyristor (9); thus, improving a power dissipation capability of the bidirectional two-terminal ungated thyristor (9).

Abstract: The semiconductor protection device has a p.sup.+ -n.sup.- -p-n.sup.+ layer construction, and an n type impurity diffusion region is selectively formed in a surface portion of the pn junction. This n type impurity diffusion region is formed in a linear planar portion where substantially no electric field concentration is generated when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region. Further, an electrode is provided in ohmic contact with both of the p type semiconductor region and the n.sup.+ type semiconductor region. This electrode is selectively made in contact with the p type semiconductor region at a position remote from the n type impurity diffusion region and adjacent to a curved planar portion of the pn junction where the electric field concentration tends to occur when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region.

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.