Abstract: A silicon controlled rectifier is provided, including: a first conducting-type substrate; two second conducting-type deep wells separately disposed inside the first conducting-type substrate; a gate above the first conducting-type substrate and between the two second conducting-type deep wells; a first source/drain inside one of the two second conducting-type deep wells and at one side of the gate; a second source/drain inside the other of the two second conducting-type deep wells and at the other side of the gate; a first conducting-type doped region inside the first conducting-type substrate; and a first conducting-type doped floating region inside the one of the two second conducting-type deep wells and adjacent to the first source/drain. The first conducting-type doped floating region and the first source/drain constitute an equivalent Zener diode so that the modified silicon controlled rectifier can have a higher holding voltage.

Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: A bi-directional silicon controlled rectifier structure provides electrostatic discharge (ESD) protection against both positive and negative voltage spikes. The structure utilizes a pair of wells, n+ and p+ regions formed in both wells, a first ring formed around the junction between the first well and the semiconductor material, and a second ring formed around the junction between the second well and the semiconductor material.

Abstract: A semiconductor thyristor device that incorporates buried region breakdown junctions laterally offset from an emitter region. By spacing the buried regions around the emitter region, current carriers emitted from the buried regions are distributed over a large area of the emitter region, thereby providing a high current capability during initial turn on of the device. In order to achieve low breakover voltage devices, the buried regions are characterized with high impurity concentrations, with the breakdown junctions located near the surface of the chip. The low voltage thyristor device minimizes the area of high dopant concentration junctions, thus minimizing the chip capacitance and permitting high speed, low voltage signal operation.

Abstract: A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

Abstract: A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N?type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

Abstract: A semiconductor arrangement including: a substrate having a substrate layer (13) with an upper and lower surface, the substrate layer (13) being of a first conductivity type; a first buried layer (12) in the substrate, extending along said lower surface below a first portion of said upper surface of said substrate layer (13), and a second buried layer (12) in the substrate, extending along said lower surface below a second portion of said upper surface of said substrate layer (13); a first diffusion (26) in said first portion of said substrate layer (13), being of a second conductivity type opposite to said first conductivity type and having a first distance to said first buried layer (12) for defining a first breakdown voltage between said first diffusion (26) and said first buried layer (12); a second diffusion (45) in said second portion of said substrate layer (13), being of said second conductivity type and having a second distance to said second buried layer (12) for defining a second breakdown volta

Abstract: In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Abstract: In an ESD protection device using a LVTSCR-like structure, the holding voltage is increased by placing the p+ emitter outside the drain of the device, thereby retarding the injection of holes from the p+ emitter. The p+ emitter may be implemented in one or more emitter regions formed outside the drain. The drain is split between a n+ drain and a floating n+ region near the gate to avoid excessive avalanche injection and resultant local overheating.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: An ESD protection circuit having a high triggering threshold. The ESD protection circuit comprises a semiconductor-controlled rectifier (SCR) and a bipolar-junction-transistor (BJT). The SCR comprises an anode, an anode gate, a cathode gate and a cathode. The anode is coupled to a first pad. The cathode gate and the cathode are coupled to a second pad. The BJT transistor is parasitic under a metal-on-semiconductor (MOS) transistor and has a collector and an emitter. Either the collector or the emitter is coupled to the anode gate, and the other is coupled only to the second pad. Current generated at the anode is shared by the BJT transistor. A larger current is required to trigger the SCR in the ESD protection circuit of the present invention and result in a latch-up. Thus, latch-up caused by accidental noise is prevented during normal power operations.

Abstract: In accordance with an embodiment of the present invention, a semiconductor rectifier includes an insulation-filled trench formed in a semiconductor region. Strips of resistive material extend along the trench sidewalls. The strips of resistive material have a conductivity type opposite that of the semiconductor region. A conductor extends over and in contact with the semiconductor region so that the conductor and the underlying semiconductor region form a Schottky contact.

Abstract: A high voltage integrated switching device includes at least one high voltage switching circuit, preferably employing DMOS technology and characterized by a breakdown voltage of at least 100 volts, on a dielectrically isolated, bonded and vertically trenched silicon substrate. Multiple high-voltage switching circuits may be located in close proximity on a single substrate without circuit breakdown or shorting during circuit operation. The circuit may further include one or more low- and/or intermediate-voltage circuits employing, for example, CMOS and bipolar technologies on the same silicon substrate and located in close proximity without voltage breakdown during circuit operation.

Abstract: A semiconductor device providing an improved effect of suppressing variation with time of reverse breakdown voltage applied to PN junction, particularly, a voltage-regulator device, is provided. The semiconductor device includes an impurity diffusion layer 15 formed on a surface of a certain-conductivity-type semiconductor substrate or well, the impurity diffusion layer having a conductivity opposite to that of the semiconductor substrate or well, and a device separating insulation film 12 formed at a distance from the impurity diffusion layer, and a distance between an end of the impurity diffusion layer and an end of the device separating insulation film is defined to be not less than 1.2 &mgr;m.

Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the substrate between the second region and the wall. The component includes a succession of trenches extending in the substrate under the track and perpendicularly to this track, each trench being filled with an insulator.

Abstract: A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 &mgr;m or less.

Abstract: An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.

Abstract: A semiconductor thyristor device that incorporates buried regions centrally located on the chip with respect to the other semiconductor regions. By centering an upper and lower buried region, larger-area contacts can be realized, thereby increasing the current capability of the device. In order to achieve low breakover voltage devices, the buried regions are offset laterally with respect to the respective emitter regions. The low voltage thyristor devices can be incorporated into five-pin protection modules for protecting customer circuits.

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.

Abstract: An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafer. The voltage at the series MOSFET (M1) functions as an indicator for the overcurrent and excess temperature, and an additional MOSFET (M4) is provided where source (region) is connected conducting to the source of the series MOSFET (M1), where drain is conductivity connected with the gate of the series MOSFET (M1) and where gate conductivity connected with the drain of the series MOSFET (M1). A resistance (Rg) is provided between the gate electrode (G1) of the series MOSFET (M1) and the gate (G) of the thyristor.

Abstract: A high voltage integrated switching device includes at least one high voltage switching circuit, preferably employing DMOS technology and characterized by a breakdown voltage of at least 100 volts, on a dielectrically isolated, bonded and vertically trenched silicon substrate. Multiple high-voltage switching circuits may be located in close proximity on a single substrate without circuit breakdown or shorting during circuit operation. The circuit may further include one or more low- and/or intermediate-voltage circuits employing, for example, CMOS and bipolar technologies on the same silicon substrate and located in close proximity without voltage breakdown during circuit operation.

Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×1017 cm−3) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages.

Abstract: The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region.

Abstract: An ESD protection circuit for protecting a circuit, comprising a lateral semiconductor-controlled rectifier, a MOS transistor, and a current-sinking device. The lateral semiconductor-controlled rectifier is coupled to the circuit and provided with a first common region and a second common region. The MOS transistor integrated with the lateral semiconductor-controlled rectifier includes the first common region The current-sinking device integrated with the lateral semiconductor controlled rectifier includes the second common region. The current-sinking device shunts the majority of a discharge current when the MOS transistor enters breakdown, thereby increasing the trigger current of the lateral semiconductor-controlled rectifier.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: A semiconductor device has first and second electrical terminals. The device comprises at least one n/p or p/n first junction adjacent the first terminal, and at least one of the other of a p/n or n/p second junction adjacent the second terminal. It also has at least one n/p or p/n junction disposed between the first and second junctions and arranged to be transverse thereto, and at least one gate terminal in contact with the p or n doped region of the first junction or the n or p doped region of the second junction.

Abstract: A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.

Abstract: A four-layer low voltage thyristor device (30) in which the breakover voltage is independent of the holding current. Rather than forming a buried region (38) underlying the emitter region (42), the buried region 38 is formed laterally to the side of the emitter (42). In order to form a low breakover voltage device, the buried region (38) is required to be highly doped, but the resulting junction (40) does not approach the emitter junction (48). A low breakover voltage (5 V-12-V) thyristor can thus be realized.

Abstract: An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main thyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: A compound semiconductor device including a MISFET and a thyristor connected in series wherein either the withstanding voltage between the MISFET p base layer and the thyristor p base layer is set lower than the withstanding voltage of the MISFET, the MISFET is turned off under a condition that the MISFET p base layer and the thyristor p base layer are connected via a p channel or the lateral resistance of the thyristor p base layer is reduced, thereby the safe operating region of the compound semiconductor device is extended.

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: An amplifying-gate thyristor having an increased integrated circuit includes a main thyristor and an amplifying thyristor. The amplifying thyristor is of the gate turnoff-type. The main tbyristor and the amplifying thyristor are such that the amplifying thyristor remains in the conductive state while the main thyristor is conductive. A control circuit turns off the amplifying thyristor when the current through the main thyristor is approximately its hold current.

Abstract: An increase in breakdown voltage of a semiconductor device upon which a layer of high resistance material, such as SIPOS, has been formed is achieved by controllably modifying the physical composition of the high resistance layer, for example by patterning a plurality of generally wedge-shaped apertures into the layer, so that the electric field in the underlying substrate is made more uniform across the surface of the device. This increase in uniformity in the radial direction effectively spreads out or reduces the field away from its normal peak region near the corner of the drain/substrate PN junction. In most versions of this device, an additional advantage--decreased leakage current--is realized.

Abstract: A novel semiconductor device with a pair of main surfaces is disclosed, in which at least three semiconductor layers are formed adjacently to each other. The device comprises a main thyristor portion for supplying a main current, an auxiliary thyristor portion, a pilot thyristor portion and a breakover portion. The breakover portion, in turn, includes a semiconductor layer having a high impurities concentration formed on one of the main surfaces, and a plurality of semiconductor layers having a high impurities concentration of opposite conduction type formed adjacently to the semiconductor layer and in spaced relationship from each other.

Abstract: In a complex semiconductor device, an IGBT and a thyristor are formed in an identical semiconductor substrate to be connected in parallel with each other between main electrodes such that an end of the thyristor on the cathode side is connected to the main electrode via an insulated gate electrode of the IGBT. Thanks to the complex of the IGBT and the thyristor, there is attained a semiconductor device having a satisfactory ignition characteristic, a low on-state voltage, and a high breakdown voltage.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A thyristor includes a semiconductor body with a surface. The semiconductor body has an inner zone of a first conduction type; a cathode-side base zone of a second conduction type opposite the first type, the base zone having a recess formed therein; a layer of the second conduction type being disposed on the surface of the semiconductor body, being disposed in the cathode-side base zone, being thinner than the cathode-side base zone, and being joined to the cathode-side base zone; and an additional zone of the second conduction type being disposed in the recess, being joined to the layer, being thicker than the layer, and being spaced apart from the cathode-side base zone.

Abstract: MOS-controlled thyristor is formed of a P-type first base layer (23), an N-type floating emitter layer (24), and a P-type second base layer (25) on an N.sup.- -type base layer (14), by a double diffusion process. The thyristor mode is realized early on and conduction in a parasitic thyristor is prevented by forming a source layer (17) in the second base layer (25) to restrict the current flowing through the second base layer (25). The semiconductor has high withstand voltage, low resistance over the entire device, suppresses the occurrence of discontinuity in the voltage-current curve, and is capable of suppressing the latch-up phenomenon and controlling large currents.

Abstract: A PNPN semiconductor device has an inner P-type region which includes at least one ridge which extends into its outer N-type region and terminates short of the outer boundary of the outer N-type region, the inner P-type region includes a formation which is substantially level with the outer boundary of the outer N-type region, and the device includes a terminal which contacts the outer N-type region and the formation of the inner P-type region.An alternative structure of the PNPN semiconductor device has an inner P-type region having at least one elongate sub-region, of higher conductivity than the remainder of the inner P-type region, lying along the junction between the inner P-type region and the outer N-type region, the formation which is substantially level with the outer boundary of the outer N-type region, and the terminal which contacts the formation and the outer N-type region.

Abstract: When bypassing a high voltage surge by externally installing a diode between a collector and a gate and protecting a circuit by turning on an IGBT, it is difficult to select a withstand voltage of the diode, because the withstand voltage of the IGBT must be higher with a certain margin. In the present invention, regions of an inverse conductivity type are formed in a high resistivity layer of an IGBT as in base region, and a transistor is formed together with a collector layer of an inverse conductivity type, which is connected between the collectors of an IGBT to be utilized as a clamping transistor. The breakdown voltage of this transistor is made lower than the breakdown voltage of a bipolar transistor of the IGBT main body. Then when the transistor breaks down, the gate-emitter capacity of the IGBT is charged and the IGBT is turned on, thus absorbing the high energy produced by an abnormal voltage into the chip and increasing the withstand capacity.