Abstract: A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm2 of the electrical contact portion of the first lead is available for contacting a printed circuit board. The second lead is in contact with a second electrical contact of the power semiconductor die. The second lead includes a heat exchanging portion on the bottom side of the housing and an electrical contact portion also on the bottom side of the housing.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a plurality of conductive blocks, wherein each conductive block is operatively coupled with each semiconductor unit; a conductive malleable layer operatively coupled with each conductive block, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A donor substrate for laser induced thermal imaging and a method of fabricating an organic light emitting diode (OLED) using the donor substrate are disclosed. In one embodiment, the donor substrate includes a base film, a light-to-heat conversion layer formed on the base film, a buffer layer formed on the light-to-heat conversion layer, and a transfer layer formed on the buffer layer. The buffer layer is formed of magnesium (Mg), an Mg alloy, or magnesium oxide. In the donor substrate for laser induced thermal imaging, the buffer layer is formed between the interlayer and the transfer layer or between the light-to-heat conversion layer and the transfer layer, so that surface characteristics between the donor substrate and the transfer layer can be improved.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: An electronic assembly including a first heat producing device mounted on a first outer surface of a first portion of a circuit board. The first portion can deflect upwardly and downwardly relative to other portions of the circuit board. A first force element urges the first heat producing device against a heat sink. The force exerted by the first force element is variable with respect to time.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: A power semiconductor device that uses a lead frame for making connection to a semiconductor device and has a structure less subject to fatigue failure at the connection part of the lead frame. A mold resin of a casing (14) is used for integrally covering the lead frame (6, 7, 13), semiconductor device (1), and metal block (15) serving as a substrate mounting the semiconductor device (1). The mold resin surrounding the lead frame (6) and semiconductor device (1) strengthens the joint therebetween, resulting in the power semiconductor device less subject to fatigue failure at the connection part of the lead frame (6).

Abstract: A nitride semiconductor laser device includes a nitride semiconductor substrate, and a layered portion corresponding to a nitride semiconductor film grown on the nitride semiconductor substrate, the layered portion including an n-type layer and a p-type layer and a light emitting layer posed between the n- and p-type layers, of the n- and p-type layers a layer opposite to the nitride semiconductor substrate with the light emitting layer opposed therebetween serving as an upper layer having a stripe of 1.9 ?m to 3.0 ?n in width, the light emitting layer and the upper layer having an interface distant from a bottom of the stripe by 0 ?m to 0.2 ?m.

Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.

Abstract: A socket assembly for removably receiving a solder ball of a chip package and methods for forming the same. The socket assembly is a raised construction formed over a substrate and includes a socket, a ball contact structure, and an electrical trace. A relatively thick photoresist layer, which may have a thickness in a range from about 20 microns to about 450 microns, is used in the process of forming the socket assembly. The photoresist layer may have formed therein a patterned opening used as a mold for the socket assembly. Alternatively, the photoresist layer may be an integral and permanent component of the socket assembly. The socket assembly is configured such that a solder ball may be disposed in the socket so as to be electrically connected to the socket assembly. Optionally, the socket assembly includes one or more ball penetration structures for facilitating the establishment of electrical contact and for adapting the socket assembly to solder balls of different dimensions.

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A multilayered electronic part with minimized silver diffusion into ceramic body. The multilayered electronic part is produced by sintering a green ceramic body of a plurality of ceramic layers comprising a main phase and a grain boundary phase, at least one of the ceramic layers being printed thereon Ag-containing internal electrode patterns which may serve as markers for indicating several information such as a production number, a name of manufacturer, a kind of circuit, etc. By the production method of the invention, the diffusion of Ag in the internal electrode patterns into the ceramic body is effectively prevented to avoid the deterioration of the electrical characteristics as well as to avoid the blackening of the ceramic to ensure a high lightness of the ceramic body which enhances the reliability of the visual identification and distinguishability of the markers.

Abstract: A resin sealing type semiconductor device includes an internal heat radiator having an element placing surface, a semiconductor element bonded to the element placing surface and leads which are separated from the semiconductor element. Wires electrically connect the leads to the electrodes of the semiconductor element. An insulator is located between the internal heat radiator and the leads. A resin package is formed exposing an exposed area of the internal heat radiator. A heat radiating fin is bonded to the exposed area of the internal heat radiator by a solder layer therebetween. The dimension S1 of the exposed area is equal to or larger than the dimension S2 of the bonding area of the heat radiating fin and the solder layer.