Abstract: A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.

Abstract: A semiconductor device includes a switching element, a control circuit, and a first and second temperature detectors. The control circuit controls the switching element and have an overcurrent detection circuit for the switching element. The first temperature detector detects the temperature of the switching element and the second temperature detector detects the temperature of the control circuit. The control circuit includes a reference correction circuit for correcting an overcurrent reference value of the overcurrent detection circuit on the basis of a first detection value and a second detection value detected by the first and second temperature detectors and outputting a corrected overcurrent reference value.

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

Abstract: A disk cell for pressure contacting a plurality of semiconductor components via a clamping device to generate a clamping force. The disk cell includes a housing comprising at least one metallic pressure plate, a first semiconductor component arranged in the housing, and a second semiconductor component arranged in the housing. The first and second semiconductor components are different. The at least one metallic pressure plate reaches across and clamps the first and second semiconductor components, is substantially perpendicular to the clamping force, and is arranged so that the clamping force acts on the at least one metallic pressure plate to provide a local region of influence to clamp the first and second semiconductor components. The first semiconductor component is arranged below the local region of influence of the clamping force. The second semiconductor component is at least partially arranged outside the local region of influence of the clamping force.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a fin field effect transistor (finFET) array including finFET units. Each of the finFET units includes a substrate having a fin along a first direction. A first metal strip pattern and a second metal strip pattern are formed on the fin, extending along a second direction that is different from the first direction. The first and second metal strip patterns are conformally formed on opposite sidewalls and a top surface of the fin, respectively. A first contact and a second contact are formed on the fin. The first and second metal strip patterns are disposed between the first and second contacts. A first dummy contact is formed on the fin, sandwiched between the first and second metal strip patterns.

Abstract: A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Abstract: A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.

Abstract: A heat transfer member is disposed between a semiconductor element and an electrode plate. The heat transfer member comprises a metal portion extending between a first face at the semiconductor element side and a second face at the plate electrode side, and a ceramic portion surrounding the metal portion. An area of the first face is less than an area of the second face in the metal portion.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A structurally robust power switching assembly, that has a power transistor, comprising a thin and delicate layer of metal oxide, and a major surface of the layer of metal oxide being substantially coincident with a major surface of the power transistor, the major surface of the power transistor defining both an emitter and a gate. Also, dielectric material is placed over a portion of the emitter, so that it abuts the gate and a highly conductive pillar is constructed out of a relatively soft material, supported by the gate and the dielectric material, so that it has a larger area than would be possible if it was supported only by the gate.

Abstract: An integrated circuit structure includes a semiconductor chip, which includes a corner, a side, and a center. The semiconductor chip further includes a plurality of bump pad structures distributed on a major surface of a substrate; a first region of the substrate having formed thereon a first bump pad structure having a first number of supporting metal pads associated with it; and a second region of the substrate having formed thereon a second bump structure having a second number of supported metal pads associated with it, the second number being greater than the first number.

Abstract: Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.

Abstract: A vertical semiconductor power switch has a semiconductor body having a first surface and a second surface. At least one anode and one control electrode are positioned on the first surface and at least one cathode is positioned on the second surface. The cathode comprises a multi-layer contact structure which comprises an inner contact layer positioned directly on the second surface of the semiconductor body, and an outermost layer consisting essentially of a Ni-alloy.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

Abstract: A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.

Abstract: A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.

Abstract: A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.

Abstract: The present invention according to one preferred embodiment provides a thermoelectric element device comprising a first electrode including an electrode member, an elastic member that has electrically conductive and is provided on the electrode member, and a heat uniforming member that has electrically conductive and is provided on the elastic member; a thermoelectric element that is made of a thermoelectric material having thermoelectric effect and arranged on the first electrode so as to contact the heat uniforming member; and a second electrode arranged on the thermoelectric element.

Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.

Abstract: Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Abstract: A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expa

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.

Abstract: According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.

Abstract: A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 ?m. The reason is as follows. If the diameter of the mesh hole is less than 75 ?m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 ?m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 ?m. The reason is as follows. If the distance is less than 100 ?m, the solid layer cannot function. If the distance exceeds 2000 ?m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract: This invention relates to a semiconductor having protruding contacts comprising, a first semiconductor substrate having at least one interconnect located substantially within the first substrate, and a second semiconductor substrate having at least one protruding contact point that substantially contacts at least one interconnect.

Abstract: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Abstract: The invention relates to a power semiconductor module having at least one semiconductor chip (11) made of a semiconductor material and having a first and a second main electrode (12, 13), a first and a second main connection (91, 92) and a contact lamina (2) in electrical contact with the first main electrode (12) and the first main connection (92). The contact lamina (2) contains an alloying partner which can form a eutectic with the semiconductor material. According to the invention, the contact lamina is coated with an electrically conductive protective layer (31, 32) that prevents formation of a fixed material connection between the first main electrode (12) and the contact lamina (2).

Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal, thin film fabrication technology is used during the wafer process.

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: Semiconductor-mounted device comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and sealing resin sealing, with a same height, a region disposed at and around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip; and a producing method thereof. Semiconductor-mounted device also comprises wired board, first semiconductor chip mounted on first side of wired board, second semiconductor chip mounted on second side of wired board and resin sheet covering, at substantially a same height as first semiconductor chip, a region disposed around first semiconductor chip and opposite, across wired board, to at least an area of projecting electrodes of second semiconductor chip, back surface of first semiconductor chip being exposed; and a producing method thereof.

Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: A semiconductor or electronic device, such as a power module uses at least one spring terminal as a control terminal. The spring terminal is led outside a case through a coil-accommodating member, which can be a frame or removable cover. With this arrangement, the spring terminal can be arranged at an arbitrary position inside the case. The spring terminal can be joined by soldering or bonding to the electrode of an in-case substrate while being held by the frame or cover. The in-case substrate can be accessed for solder joining through at least one aperture formed in the frame.

Abstract: A semiconductor device connecting structure is provided for connecting a semiconductor IC to a substrate. A bonding layer is placed between the substrate and the semiconductor IC to accomplish adhesion therebetween. Sufficient heat and pressure are applied to the bonding layer to create spaces therein which deform during relative movement between the semiconductor IC and substrate thereby maintaining consistent electrical contact between the semiconductor contact bumps and electrodes on the substrate.

Abstract: A fault detection system detecting malfunctions or deteriorations, which may result in an inverter fault, is provided. The system has a temperature sensor installed on a semiconductor module to monitor a temperature rise rate. It is judged that an abnormal condition has occurred if the thermal resistance is increased by the deterioration of a soldering layer of the semiconductor module or by drive circuit malfunctions and, as a result, the relation between an operation mode and the temperature rise rate falls outside a predetermined range.

Abstract: A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film.

Abstract: A package type semiconductor device comprising: a semiconductor chip having a semiconductor part; a main electrode for connecting to a first region of the semiconductor part; a control wiring layer for connecting to a second region of the semiconductor part; a blocking member electrically isolated from the control wiring layer; a first metallic layer; a protection film disposed among the main electrode, the control wiring layer and the blocking member; and a metal block for connecting to the main electrode through the first metallic layer. The chip, the main electrode, the control wiring layer, the blocking member, and the metal block are packaged. The blocking member is disposed between the main electrode and the control wiring layer.