Abstract: A light emitting transducer including a flexible sheet having a bottom side and a top side, the flexible sheet including a substrate that is stretchable and compressible, the substrate having a bottom substrate surface at the bottom side, and a top substrate surface facing towards the top side, the top substrate surface comprising a surface pattern of a plurality of raised and depressed micro-scale surface portions which extend in at least one direction; a light emitting diode layer above the substrate and conforming in shape to the top substrate surface, the light emitting diode layer corresponding with the surface pattern of the top substrate surface, wherein the light emitting diode layer has a bottom diode surface facing towards the bottom side, and a top diode surface facing towards the top side, a bottom electrode on the bottom diode surface, and a top electrode on the top diode surface.

Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.

Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.

Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.

Abstract: A power semiconductor module applied to a power converting apparatus for a railway car includes an element pair formed by connecting an IGBT and an SiC-FWD in anti-parallel to each other and an element pair formed by connecting an Si-IGBT and an SiC-FWD in anti-parallel to each other. The element pair and the element pair are housed in one module and configured as a 2-in-1 module in a manner that the first element pair operates as a positive side arm of the power converting apparatus and the second element pair operates as a negative side arm of the power converting apparatus. The element pairs are formed such that a ratio of an occupied area of SiC-FWD chips to an occupied area of IGBT chips in the element pairs is equal to or higher than 15% and lower than 45%.

Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.

Abstract: This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.

Abstract: A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down.

Abstract: A semiconductor device includes a plate-shaped semiconductor element and an electrically insulating resin member. The semiconductor element has a front-surface electrode on its front surface and a back-surface electrode on its back surface. The resin member encapsulates the semiconductor element. The front-surface electrode is exposed to a front side of an outer surface of the resin member. The back-surface electrode is exposed to a back side of the outer surface of the resin member. The resin member has an extension portion that covers the entire side surface of the semiconductor element and extends from the side surface of the semiconductor element in a direction parallel to the front surface of the semiconductor element.

Abstract: A heat transfer member is disposed between a semiconductor element and an electrode plate. The heat transfer member comprises a metal portion extending between a first face at the semiconductor element side and a second face at the plate electrode side, and a ceramic portion surrounding the metal portion. An area of the first face is less than an area of the second face in the metal portion.

Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: A group III nitride semiconductor light-emitting device comprises an n-type gallium nitride-based semiconductor layer, a first p-type AlXGa1-XN (0?X<1) layer, an active layer including an InGaN layer, a second p-type AlYGa1-YN (0?Y?X<1) layer, a third p-type AlZGa1-XN layer (0?Z?Y?X<1), and a p-electrode in contact with the third p-type AlZGa1-ZN layer. The active layer is provided between the n-type gallium nitride-based semiconductor layer and the first p-type AlXGa1-XN layer. The second p-type AlYGa1-YN (0?Y?X<1) layer is provided on the first p-type AlXGa1-XN layer. The p-type dopant concentration of the second p-type AlYGa1-YN layer is greater than the p-type dopant concentration of the first p-type AlXGa1-XN layer. The third p-type AlZGa1-ZN layer (0?Z?Y?X<1) is provided on the second p-type AlYGa1-YN layer. The p-type dopant concentration of the second p-type AlYGa1-YN layer is greater than a p-type dopant concentration of the third p-type AlZGa1-ZN layer.

Abstract: A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.

Abstract: A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract: The invention discloses a method of fabricating a first substrate and a method of recycling a second substrate during fabrication of the first substrate. The second substrate is heterogeneous for the first substrate. First, the fabricating method according to the invention is to prepare the second substrate. Subsequently, the fabricating method is to deposit a buffer layer on the second substrate. Then, the fabricating method is to deposit a semiconductor material layer on the buffer layer. The buffer layer assists the epitaxial growth of the semiconductor material layer, and serves as a lift-off layer. Finally, with an etching solution, the fabricating method is to only etch the lift-off layer to debond the second substrate away from the semiconductor material layer, where the semiconductor material layer serves as the first substrate.

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.

Abstract: A power semiconductor module includes a housing, terminal elements leading to the outside of the housing, an electrically insulated substrate arranged inside the housing, with the substrate being comprised of an insulating body and having on the first main face facing away from the base plate a plurality of connecting tracks electrically insulated from each other. The terminal and connecting elements are arranged on a connecting track in with contact faces contacting connecting tracks or power semiconductor components, with the individual contact faces having a plurality of partial contact faces. In one optional embodiment, each partial contact face has a maximum area of 20 mm2. In another embodiment, partial contact faces each are arranged at a distance of approximately 5 mm with regard to each other and the connection of the partial faces to the connecting tracks or the power semiconductor components is flush.

Abstract: A housing for a semiconductor device is disclosed. In an exemplary embodiment of the present invention, the housing comprises a semiconductor substrate that is arranged between two contact elements, one contact element forming an anode contact element and another contact element forming a cathode contact element, the semiconductor substrate having, on at least one surface, a gate electrode that is contacted by a gate contact element, the first contact element forming a surface arranged across from the gate electrode and at a distance from the gate electrode. Also included is at least one driver unit for generating a gate current, the driver unit comprising a first terminal that is contacted with the gate contact element, and a second terminal that is contacted with a first of the two contact elements.

Abstract: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than a width of the first pattern; and a convex portion provided in the first pattern.

Abstract: A main substrate is provided with a wiring pattern on its surface and in the inner layer. A wiring pattern for connecting the signal line or power line of the main substrate to an external circuit is formed on the flexible printed circuit. A connection terminal to which a corresponding wiring pattern is connected is formed at the tip of the flexible printed circuit. A through-hole is formed between the wiring patterns. Potting resin is potted in each through-hole and around it. When the resin hardens, the potting resin joints the main substrate and the flexible printed circuit.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A MEMS switch includes a lower substrate having a signal line on an upper surface of the lower substrate; an upper substrate, having a cavity therein, disposed apart from the upper surface of the lower substrate by a distance, and having a membrane layer on a lower surface of the upper substrate; a bimetal layer formed in the cavity of the upper substrate on the membrane layer; a heating layer formed on a lower surface of the membrane layer; and a contact member formed on a lower surface of the heating layer. The contact member can come into contact with or separate from the signal line. A method for manufacturing the MEMS switch includes preparing the upper and lower substrates and combining them so that a surface having the signal line faces a surface having the contact member and the upper and lower substrates are disposed apart by a distance.

Abstract: An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.

Abstract: The invention relates to a power semiconductor module having at least one semiconductor chip (11) made of a semiconductor material and having a first and a second main electrode (12, 13), a first and a second main connection (91, 92) and a contact lamina (2) in electrical contact with the first main electrode (12) and the first main connection (92). The contact lamina (2) contains an alloying partner which can form a eutectic with the semiconductor material. According to the invention, the contact lamina is coated with an electrically conductive protective layer (31, 32) that prevents formation of a fixed material connection between the first main electrode (12) and the contact lamina (2).

Abstract: A housing for a semiconductor device is disclosed. In an exemplary embodiment of the present invention, the housing comprises a semiconductor substrate that is arranged between two contact elements, one contact element forming an anode contact element and another contact element forming a cathode contact element, the semiconductor substrate having, on at least one surface, a gate electrode that is contacted by a gate contact element, the first contact element forming a surface arranged across from the gate electrode and at a distance from the gate electrode. Also included is at least one driver unit for generating a gate current, the driver unit comprising a first terminal that is contacted with the gate contact element, and a second terminal that is contacted with a first of the two contact elements.

Abstract: A rectifier for rectifying alternating current into direct current is described, in which a three-phase generator includes a three-phase stator winding. The phases of the stator winding are triggered via switching elements of a power circuit. The power circuit is controlled via a control part, which includes a controller component. The rectifier includes a control part (control module) having control terminals and a power circuit (power module) controlled by the control module and optionally provided with a cooling device, in which all the power-conducting components are designed as power MOS components and integrated in a stacked construction.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Abstract: Disclosed is a semiconductor module comprising a semiconductor element (1) and two terminal electrodes (3a, 3b, 3c) between which the semiconductor element (1) is disposed and with which the semiconductor element (1) is contacted in an electrically conducting manner. The semiconductor element (1) is surrounded by an at least partly electrically insulating housing (5, 7, 11, 12). In order to protect the housing from the effect of electric arcs occurring in the event of an overload, a high temperature-resistant insulator which is arranged at least at some points between a housing wall and the semiconductor element is provided inside the module. The insulator can surround the semiconductor element as a hollow cylinder.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. The annular flange preferably comprises a projection having a squared tab and circular distal end that is received by a receiving groove having a notch (to receive the squared tab) and a cavity (to receive the distal end).

Abstract: This power switching cell comprises: at least two power components (4–6) forming a chain (2) of components electrically linked in series by way of at least one intermediate bond (52, 70), and a dielectric substrate inside which are incorporated said at least two components (4–6). Each intermediate bond (52, 70) as well as the faces of the components linked to this intermediate bond are entirely incorporated inside said substrate, and the faces not linked to an intermediate bond (52, 70) of the components situated at the ends of said chain (2) are disposed in such a way as to be separated from one another by way of the dielectric material forming said substrate (22). This substrate is formed of a stack of parallel sheets (24–27) of dielectric material, and each of the components (4–6) following in said chain is incorporated in the thickness of a different sheet.

Abstract: A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage VA continues to increase without significant anode current increase.

Abstract: A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

Abstract: A semiconductor device comprising a semiconductor layer and one, or a plurality of, semiconductor elements formed on a surface of the semiconductor layer, characterized in that said semiconductor layer is divided into a plurality of pieces in a region wherein said semiconductor layer does not have a semiconductor element and in that the respective pieces of the divided semiconductor layer have a flexible region made of an insulating layer adhered to the sides of the respective pieces so that the pieces are integrated.

Abstract: Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication parameters (i.e., temperature, pressure, and electrical bias) during spring material film information to generate the tensile or compressive stress at the saturation point of the spring material. Methods are also disclosed for tuning the saturation point through the use of high temperature or the incorporation of softening metals. In other embodiments, isotropic internal stress is generated through randomized deposition (e.g., pressure homogenization) or directed deposition techniques (e.g., biased sputtering, pulse sputtering, or long throw sputtering). Cluster tools are used to separate the deposition of release and spring materials.

Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.

Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: An object of the present invention is to provide a novel semiconductor mounting system having a semiconductor mounting member, a metal member and a joining layer joining the mounting and metal members, to improve the flatness of a mounting surface and to control the temperature on the surface of a semiconductor. A semiconductor mounting system 12 has a semiconductor mounting member 1, a metal member 7 and a joining layer 27 joining the mounting member 1 and metal member 7. The metal member 1 has a surface mounting a semiconductor. The adhesive sheet 4 has a resin matrix 11 and a filler 10 dispersed in the resin matrix 11.