Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: A semiconductor device includes a semiconductor chip comprising a first and second terminal surfaces. An insulator surrounds an outer circumference of a side surface of the chip. A reinforcing-member is arranged between the side surface of the chip and an inner side surface of the insulator and surrounds the outer circumference of the side surface of the chip. A first and second holders hold the reinforcing-member therebetween at a top and bottom surfaces of the reinforcing-member. The first and second holders comprise protrusions facing an inner wall surface of the reinforcing-member, and the when ?1in represents an inner-diameter of parts of the reinforcing-member opposing to the protrusions, ?1out represents an outer-diameter of the reinforcing-member, ?2 represents an outer-diameter of the protrusion of either the first or the second holder, and ?3 represents an inner diameter of the insulator, the following Expression 1 is satisfied ?1in??2<?1out.

Abstract: A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down.

Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).

Abstract: A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface.

Abstract: A semiconductor device includes a semiconductor substrate including a first surface serving as an element formation surface, and a second surface opposite to the first surface; a through-via penetrating the semiconductor substrate; an insulating via coating film formed between a sidewall of the through-via and the semiconductor substrate; and an insulating protective film formed on the second surface of the semiconductor substrate. The via coating film and the protective film are different insulating films from each other.

Abstract: A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.

Abstract: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one another such that slicing the frame in the second direction along the mechanical connections separates the leads. Each lead has a first terminal which is conductively attached to a chip contact and a second terminal extending beyond the boundaries of the chip to which the first terminal is attached. In this manner, the contact pitch is effectively expanded to the terminal pitch of the leads.

Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.

Abstract: The standard housing (27) of a semiconductor component (21), preferably a power semiconductor component features a plurality of external leads (1-5). Between adjacent external leads (2-3 and 4-5) for identical supply potentials or signals, mechanically reinforcing flat conductor webs (28) electrically connecting the external leads (2-3 and 4-5) are located within and/or outside the standard housing (27).

Abstract: A semiconductor device is disclosed that includes a first and a second semiconductor package. Each semiconductor package includes a semiconductor element, a plurality of electrode members, and an encapsulating member. The semiconductor elements are interposed between the respective electrode members, and the electrode members are in electrical communication with and provide heat transfer for the respective semiconductor element. The encapsulating member encapsulates the respective semiconductor element between the respective electrode members, and an outer surface of each of the electrode members is exposed from the respective encapsulating member. Each semiconductor package includes a connecting terminal electrically coupled to one of the electrode members and extending outward so as to be exposed from the respective encapsulating member. The connecting terminals are electrically connected by abutment or via a conductive junction material.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.

Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: An optical semiconductor apparatus has an eyelet having a through hole, an insulating member provided in the through hole, a semiconductor optical element, and a submount on which the semiconductor optical element is mounted. The insulating member supports a plurality of lead terminals. The submount has a first portion supported by the eyelet, a second portion supported by the eyelet, and a third portion disposed between the first portion and the second portion and located above the insulating member. The semiconductor optical element is provided on the third portion of the submount.

Abstract: This power switching cell comprises: at least two power components (4–6) forming a chain (2) of components electrically linked in series by way of at least one intermediate bond (52, 70), and a dielectric substrate inside which are incorporated said at least two components (4–6). Each intermediate bond (52, 70) as well as the faces of the components linked to this intermediate bond are entirely incorporated inside said substrate, and the faces not linked to an intermediate bond (52, 70) of the components situated at the ends of said chain (2) are disposed in such a way as to be separated from one another by way of the dielectric material forming said substrate (22). This substrate is formed of a stack of parallel sheets (24–27) of dielectric material, and each of the components (4–6) following in said chain is incorporated in the thickness of a different sheet.

Abstract: A power semiconductor device that uses a lead frame for making connection to a semiconductor device and has a structure less subject to fatigue failure at the connection part of the lead frame. A mold resin of a casing (14) is used for integrally covering the lead frame (6, 7, 13), semiconductor device (1), and metal block (15) serving as a substrate mounting the semiconductor device (1). The mold resin surrounding the lead frame (6) and semiconductor device (1) strengthens the joint therebetween, resulting in the power semiconductor device less subject to fatigue failure at the connection part of the lead frame (6).

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: A semiconductor thyristor device incorporates buried regions to achieve low breakover voltage devices, and the buried regions are offset laterally with respect to the emitter regions. The low voltage thyristor devices can be incorporated into five-pin protection modules for protecting customer circuits.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A pressure-contact type semiconductor device comprises a plurality of semiconductor elements (IGBTs) which are in pressure contact with one another, and in which first main electrodes are electrically connected to a first common main power source plate (pressure-contact type emitter electrode plate), and second main electrodes are electrically connected to a second common main power source plate (pressure-contact type collector electrode). The pressure-contact type semiconductor device also includes a common control signal board which is constituted by a printed circuit board or a multi-layered printed circuit board, and extends over spaces between rows of semiconductor elements, thereby forming a path for sending a control signal.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A power semiconductor module comprises a metal base, plural wiring substrates provided on said the base, a first wiring substrate of the wiring substrates having a power circuit portion including a power semiconductor device, and substrate containing portions having a resin portion in which one of the wiring substrates is contained. The one of the wiring substrates is positioned in self-alignment on the metal substrate on the basis of an inner wall of the resin portion of the substrate-containing portion.

Abstract: A first cathode flange (14) provided with branch-like protrusions (14d) extending towards substantially its outer periphery and a gate flange (15) provided with branch-like protrusions (15c) extending towards substantially its outer periphery are connected to a cathode electrode (7a) and a gate electrode (7b), respectively, formed on one surface of a gate drive substrate (7). With this structure, a gate commutated turn-off semiconductor device which eliminates the necessity of a gate spacer and a cathode spacer and allows reduction in time and cost required for manufacture can be achieved.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: In a GCT device which controls large current at the operating frequency of 1 kHz or more, a ring-shaped gate terminal (10) is made of a magnetic material with the maximum permeability of 15,000 or less in the CGS Gaussian system of units. Further, in the outer end portion of an outer plane portion (10O) of the ring-shaped gate terminal (10), a plurality of slits extending diametrically are provided along the circumference to be coupled to mounting holes (10b).

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A double circular gate conductor 9 comprises a first circular gate conductor 7 connected to a gate electrode 2a, a second circular gate conductor 8, and a connecting conductor which connects the first circular gate conductor 7 and the second circular gate conductor 8, and is configured so as to equalize the voltage drop due to self-inductance or mutual inductance between the first circular gate conductor 7, second circular gate conductor 8 and cathode post electrode 4. In this manner it is possible to guarantee more or less uniform parallel inductance over the surface of the element.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: In the present invention, by virtue of heat buffer plates respectively located on the major surfaces of IGBT chips and FRD chips arranged in a single plane, the total thickness of each chip and a corresponding one of the heat can be set to a substantially predetermined value. A thickness-correcting member having elongated projections corresponding to the chips is provided on those surfaces of the heat buffer plates which is remote from the chips. A heat buffer disk plate is provided on those surfaces of the chips which are opposite to the major surfaces thereof. The thickness-correcting member, the heat buffer plates and the IGBT and FRD chips are held and simultaneously pressed between an emitter press-contact electrode plate and a collector press-contact electrode plate.

Abstract: A compression bonded type semiconductor element having a ring-shaped gate terminal in the form of an annular metal disk projecting through the side of an insulating cylinder. The ring-shaped gate terminal includes an inner circumferential planar portion which is disposed so as to be slidable on an annular ring gate electrode. The annular ring gate electrode is in contact with a gate electrode formed on a semiconductor substrate, and the ring gate electrode is pressed against the gate electrode via the ring-shaped gate terminal by an elastic body.

Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.

Abstract: An alloy-free pressure contact type semiconductor device maintains a high reliability during transportation even without a pressure contact tool such as a simplified stack and therefore does not require a high transportation cost. Through holes (H1) and (H2) each having a circular cross section are formed in distortion buffer plates (21A) and (21K) at the center. A first and a second bottomed holes (i.e., recesses) (N1) and (N2) are formed in an anode electrode plate (41A) and a cathode electrode plate (41K). From the through hole (H1) up to the first bottomed hole (N1), a pressure contact pin (9) biased by a coil spring (8) is disposed. From the through hole (H2) down to the second bottomed hole (N2), a fixing pin (90) is disposed. Without applying external pressure upon the device, it is possible to prevent displacement of the first and the second distortion buffer plates due to vibration or impact during transportation and damage to a semiconductor body.

Abstract: A circuit arrangement and a power semiconductor module are provided in which the circuit arrangement comprises a plurality of parallel-connected power semiconductor modules, of which only one is connected to a control device. The other modules function as slaves of the master connected to the control device and draw the signal required for triggering from the master via a signal bus. For this purpose, the power semiconductor modules have a number of signal connections which are interconnected. The signal connections may be connected signalwise to the gate connections, for example via an interface. The power semiconductor modules according to the invention provide a circuit arrangement in which a plurality of modules can be connected in parallel up to maximum performances without limitations.

Abstract: In a turn-off high-power semiconductor component, in particular in the form of a GTO, comprising a disk-shaped semiconductor substrate (2) which is disposed concentrically in an annular insulating housing (10) between a disk-shaped cathode contact (4), to which pressure can be applied, and a disk-shaped anode contact (5), to which pressure can also be applied, and which is contacted on the cathode-contact side by a gate contact (7, 21), the cathode contact (4) being connected to one end of the insulating housing (10) via a first lid (11a) and the anode contact (5) to the other end of the insulating housing (10) via a second lid (11b), an outwardly hermetically sealed component (1) being formed, and the gate contact (7) being capable of being fed with a gate current via a gate lead (8) brought to the outside, a connection to the gate unit is achieved with low mutual inductance with a minimum of alterations compared with conventional components as a result of the gate lead (8) being of rotationally symmetrical

Abstract: Coned disc springs (84, 86) lie between a gate extracting electrode (80G) held in a ringlike recess (63) of an external cathode electrode (60K) and a bottom surface of the ringlike recess (63). A semiconductor body (30) is pressed against an anode distortion buffering plate (50A) by a urging force of the coned disc springs (84, 86) for vertical positional fixation of the semiconductor body (30). This enables the semiconductor body to be prevented from damages and deformation in a full press-pack type semiconductor device.