With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 12266730
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 1, 2025
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Naohiro Tsurumi, Daisuke Shibata, Satoshi Tamura
  • Patent number: 12243955
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 4, 2025
    Assignee: Apple Inc.
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 12230689
    Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 18, 2025
    Assignee: Infineon Technologies AG
    Inventors: Helmut Brech, Albert Birner, John Twynam
  • Patent number: 12230699
    Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 18, 2025
    Assignee: Analog Devices, Inc.
    Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava
  • Patent number: 12211899
    Abstract: Embodiments relate to a semiconductor device, which includes: a substrate made of a first material; an insulating layer formed on an upper surface of the substrate; a trench formed at the insulating layer to penetrate the insulating layer toward the substrate; and a seed layer disposed in the trench. The seed layer is made of a second material, the second material lattice-mismatches with respect to the first material, the seed layer includes a threading dislocation extending at least partially in a first direction non-parallel to the upper surface of the substrate and parallel to a <110> direction of a (111) plane and a threading dislocation extending at least partially in a second direction, and the extension of the threading dislocation is terminated at a sidewall of the trench.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 28, 2025
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyung-jun Kim, Seung Hwan Kim
  • Patent number: 12206032
    Abstract: An electromagnetic radiation detector includes an InP substrate having a first surface opposite a second surface; a first InGaAs electromagnetic radiation absorber stacked on the first surface and configured to absorb a first set of electromagnetic radiation wavelengths; a set of one or more buffer layers stacked on the first InGaAs electromagnetic radiation absorber and configured to absorb at least some of the first set of electromagnetic radiation wavelengths; a second InGaAs electromagnetic radiation absorber stacked on the set of one or more buffer layers and configured to absorb a second set of electromagnetic radiation wavelengths; and an immersion condenser lens formed on the second surface and configured to direct electromagnetic radiation through the InP substrate and toward the first InGaAs electromagnetic radiation absorber and the second InGaAs electromagnetic radiation absorber.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 21, 2025
    Assignee: Apple Inc.
    Inventors: Mark Alan Arbore, Matthew T. Morea, Miikka M. Kangas, Romain F. Chevallier, Tomas Sarmiento
  • Patent number: 12205986
    Abstract: A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 21, 2025
    Assignee: KOREA ADVANCED NANO FAB CENTER
    Inventors: Dong Hwan Jun, Hyun Mi Kim, Sang Tae Lee, Chan Soo Shin
  • Patent number: 12199098
    Abstract: Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm3. A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Cory Weber, Stephen M. Cea, Leonard C. Pipes, Seahee Hwangbo, Rishabh Mehandru, Patrick Keys, Jack Yaung, Tzu-Min Ou
  • Patent number: 12176217
    Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hung Liao, Chung-Wei Hsu, Tsung-Ling Tsai, Chen-Hao Wu, An-Hsuan Lee, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 12176430
    Abstract: A semiconductor structure and a semiconductor device are provided. The semiconductor includes a substrate, a seed layer on the substrate, a buffer layer on the seed layer, a back barrier layer with a V-group element polarity on the buffer layer, a channel layer on the back barrier layer, and a front barrier layer on the channel layer.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 24, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
  • Patent number: 12142639
    Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: November 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qhalid R S Fareed, Dong Seup Lee, Nicholas S. Dellas
  • Patent number: 12136796
    Abstract: The present disclosure is generally directed to an EML with a filter layer disposed between an active region of the EML and a substrate of the EML to absorb a portion of unmodulated light energy, and preferably the unmodulated light energy caused by transverse electric (TE) substrate mode. The filter layer preferably comprises a material with an energy band gap (Eg) that is less than the energy band gap of the predetermined channel wavelength to absorb unmodulated laser light.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: November 5, 2024
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Dapeng Xu, Jin Huang, Huanlin Zhang
  • Patent number: 12132050
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 12119382
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: October 15, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Patent number: 12119618
    Abstract: A manufacturing method of a nitride-based semiconductor light-emitting element includes: forming an n-type nitride-based semiconductor layer; forming, on the n-type nitride-based semiconductor layer, a light emission layer including a nitride-based semiconductor; forming, on the light emission layer in an atmosphere containing a hydrogen gas, a p-type nitride-based semiconductor layer while doping the p-type nitride-based semiconductor layer with a p-type dopant at a concentration of at least 2.0×1018 atom/cm3; and annealing the p-type nitride-based semiconductor layer at a temperature of at least 800 degrees Celsius in an atmosphere not containing hydrogen. In this manufacturing method, a hydrogen concentration of the p-type nitride-based semiconductor layer after the annealing is at most 5.0×1018 atom/cm3 and at most 5% of the concentration of the p-type dopant, and a hydrogen concentration of the light emission layer is at most 2.0×1017 atom/cm3.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: October 15, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Shuichi Nakazawa, Shinji Yoshida, Isao Kidoguchi
  • Patent number: 12113526
    Abstract: A high-voltage switch is adapted for use as a medium-voltage direct current circuit breaker, which provides a low-cost, small-footprint device to mitigate system faults. In one example, a method for operating a wideband optical device includes illuminating the wide bandgap optical device with a light within a first range of wavelengths and a first average intensity, allowing a current to propagate therethrough without substantial absorption of the current, illuminating the wide bandgap optical device with light within the first range of wavelengths and a second average intensity that is lower than the first average intensity to allow a sustained current flow though the wide bandgap optical device, and illuminating the wide bandgap optical device with light within a second range of wavelengths to stop or substantially restrict propagation of the current through the wide gap material.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 8, 2024
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Lars F. Voss, Adam M. Conway
  • Patent number: 12095002
    Abstract: A group-III-nitride structure and a manufacturing method thereof are provided. In the manufacturing method, a first mask layer is first formed on a substrate; an uncoalesced second group-III-nitride epitaxial layer is formed by performing a first epitaxial growth with the first mask layer as a mask; and a second mask layer is formed at least on the second group-III-nitride epitaxial layer; a third group-III-nitride epitaxial layer is laterally grown and formed by performing a second epitaxial growth on the second group-III-nitride epitaxial layer with the second mask layer as a mask, where the second group-III-nitride epitaxial layer is coalesced by the third group-III-nitride epitaxial layer; a fourth group-III-nitride epitaxial layer is formed by performing a third epitaxial growth on the third group-III-nitride epitaxial layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 17, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 12068319
    Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani, Abhishek A. Sharma
  • Patent number: 12062581
    Abstract: A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Chun Chang, Guan-Jie Shen
  • Patent number: 12051724
    Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: July 30, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Tzu-Yao Lin, Jia-Zhe Liu, Ying-Ru Shih
  • Patent number: 12046652
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Nicole Thomas, Michael K. Harper, Leonard P. Guler, Marko Radosavljevic, Thoe Michaelos
  • Patent number: 12046666
    Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: July 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang Soo Suh, Sameer Prakash Pendharkar, Naveen Tipirneni, Jungwoo Joh
  • Patent number: 12027522
    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 12027417
    Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: July 2, 2024
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Suresh Vishwanath, Yulia Tolstova, Pratik Patel, Szuya S. Liao, Anand S. Murthy
  • Patent number: 12021350
    Abstract: In an embodiment an edge-emitting semiconductor laser includes a semiconductor layer sequence having a waveguide region with an active layer disposed between a first waveguide layer and a second waveguide layer and a layer system arranged outside the waveguide region configured to reduce facet defects in the waveguide region, wherein the layer system includes one or more layers with the material composition AlxInyGa1-x-yN with 0?x?1, 0?y<1 and x+y?1, wherein at least one layer of the layer system includes an aluminum portion x?0.05 or an indium portion y?0.02, wherein a layer strain is at least 2 GPa at least in some areas, and wherein the semiconductor layer sequence is based on a nitride compound semiconductor material.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 25, 2024
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jan Wagner, Werner Bergbauer, Christoph Eichler, Alfred Lell, Georg Brüderl, Matthias Peter
  • Patent number: 12009450
    Abstract: A first n-type contact layer, a second n-type contact layer, a multiplication layer, an electric field control layer, a light absorbing layer, and a p-type contact layer are layered in this order on a substrate. The second n-type contact layer is formed between the first n-type contact layer and the light absorbing layer, is made to have an area smaller than that of the light absorbing layer in a plan view, and is disposed inside the light absorbing layer in a plan view.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: June 11, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yuki Yamada, Masahiro Nada
  • Patent number: 12009431
    Abstract: A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: June 11, 2024
    Assignee: Epinovatech AB
    Inventor: Martin Andreas Olsson
  • Patent number: 12002903
    Abstract: Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 ?m or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 4, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hajime Fujikura, Taichiro Konno, Takeshi Kimura
  • Patent number: 11990343
    Abstract: A method of manufacturing an electrode structure for a device, such as a GaN or AlGaN device is described. In one example, the method includes providing a substrate (212) of GaN or AlGaN with a surface region of the GaN or AlGaN exposed through an opening (216) in a layer of silicon nitride (214) formed on the substrate. The method further includes depositing layers of W (222), in one example, or Ni (220) and W (222), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers (230) having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN (224) and Al over the underlying layers of W or Ni and W by sputtering.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 21, 2024
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Wayne Mack Struble, Timothy Edward Boles, Jason Matthew Barrett, John Stephen Atherton
  • Patent number: 11990562
    Abstract: In various embodiments, device structures configured to emit ultraviolet light have lateral surfaces that form angles to the substrate normal of approximately the Brewster angle corresponding to the light-emitting portion of the device structure. The device structures may include one or more mesas disposed over a shared substrate or handle wafer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: May 21, 2024
    Assignee: CRYSTAL IS, INC.
    Inventor: Leo J. Schowalter
  • Patent number: 11973163
    Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 30, 2024
    Assignee: Tianjin Sanan Optoelectronics Co., Ltd.
    Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng Liu, Weihuan Li, Liming Shu, Chao Liu
  • Patent number: 11972947
    Abstract: A semiconductor laminate film includes a silicon substrate and a semiconductor layer formed on the silicon substrate and containing silicon and germanium. The semiconductor layer having a surface roughness Rms of 1 nm or less. Further, the semiconductor layer satisfies the following relationship t?0.881×x?4.79 where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer. Also, the semiconductor layer being a mixed crystal semiconductor layer containing silicon and germanium.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 30, 2024
    Assignees: National University Corporation Tokyo University Of Agriculture And Technology, National Institute of Information and Communications Technology
    Inventors: Yoshiyuki Suda, Takahiro Tsukamoto, Akira Motohashi, Kyohei Degura, Katsumi Okubo, Takuma Yagi, Akifumi Kasamatsu, Nobumitsu Hirose, Toshiaki Matsui
  • Patent number: 11974508
    Abstract: According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: April 30, 2024
    Assignee: Ambature, Inc.
    Inventors: Michael S. Lebby, Davis H. Hartmann
  • Patent number: 11973127
    Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 11962900
    Abstract: In some embodiments, a ToF sensor includes an illumination source module, a transmitter lens module, a receiver lens module, and an integrated circuit that includes a ToF imaging array. The ToF imaging array includes a plurality of SPADs and a plurality of ToF channels coupled to the plurality of SPADs. In a first mode, the ToF imaging array is configured to select a first group of SPADs corresponding to a first FoV. In a second mode, the ToF imaging array is configured to select a second group of SPADs corresponding to a second FoV different than the first FoV.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: April 16, 2024
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Neale Dutton, Stuart McLeod, Bruce Rae
  • Patent number: 11963457
    Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
  • Patent number: 11942378
    Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11935951
    Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Yuan-Ko Hwang
  • Patent number: 11935793
    Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11923313
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 5, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11910714
    Abstract: A thermoelectric conversion material contains a matrix composed of a semiconductor and nanoparticles disposed in the matrix, and the nanoparticles have a lattice constant distribution ?d/d of 0.0055 or more.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 20, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiro Adachi, Makoto Kiyama, Yoshiyuki Yamamoto, Ryo Toyoshima
  • Patent number: 11908839
    Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist, Eli Lusky
  • Patent number: 11901445
    Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 13, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jiacheng Lei, James Jerry Joseph, Lawrence Selvaraj Susai, Shyue Seng Tan
  • Patent number: 11901433
    Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 11894275
    Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ying-Keung Leung
  • Patent number: 11887999
    Abstract: In a photodetector using GePDs, a photodetector having small change in light sensitivity due to temperature is provided. A photodetector includes a plurality of photodiodes formed on a silicon substrate and having germanium or a germanium compound in a light absorption layer, and two chips of integrated circuits arranged parallel to two sides connected to one corner of the silicon substrate, respectively, the two integrated circuits are connected to photodiodes formed on the silicon substrate, two or more of the photodiodes are arranged equidistantly from the integrated circuit that is parallel to one side connected to the one corner, and the numbers of equidistantly arranged photodiodes are equal, when viewed from the integrated circuits.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 30, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Kotaro Takeda
  • Patent number: 11855223
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Patent number: 11855187
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
  • Patent number: 11855142
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
  • Patent number: 11854905
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge