With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 10388751
    Abstract: The present application discloses a semiconductor device and a method for forming an n-type conductive channel in a diamond using a heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method comprises: forming a diamond layer on a substrate; and depositing a ternary compound having a donor characteristic and graded components on an upper surface of the diamond layer to form a first donor layer, forming a graded heterojunction at an interface between the diamond layer and the first donor layer, forming two-dimensional electron gas at one side of the diamond layer adjacent to the graded heterojunction, and using the two-dimensional electron gas as the n-type conductive channel. The method enables a concentration and a mobility of carriers in the n-type diamond channel to reach 1013 cm?2 and 2000 cm2/V·s respectively.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 20, 2019
    Assignee: The 13ᵗʰ Research Institute Of China Electronics Technology Group Corporation
    Inventors: Jingjing Wang, Zhihong Feng, Cui Yu, Chuangjie Zhou, Qingbin Liu, Zezhao He
  • Patent number: 10388509
    Abstract: A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 20, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 10380494
    Abstract: A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, Josephine B. Chang, Jay M. Gambetta
  • Patent number: 10366884
    Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than, the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 30, 2019
    Assignee: STRATIO
    Inventors: Jaehyung Lee, Yeul Na, Youngsik Kim
  • Patent number: 10366892
    Abstract: Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 10361159
    Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
  • Patent number: 10354998
    Abstract: Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Yung-Ta Li, Chun-Hsiang Fan, Tung-Ying Lee, Clement Hsing-Jen Wann
  • Patent number: 10340345
    Abstract: A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 2, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Takeshi Tanaka, Naoki Kaneda, Yoshinobu Narita
  • Patent number: 10340416
    Abstract: To fabricate a practically useful non-polar AlN buffer layer on a sapphire crystal plate and manufacture a UV light-emitting device on a non-polar crystal substrate by adopting the crystal substrate as an example, an embodiment of the present invention provides a crystal substrate 1D comprising an r-plane sapphire crystal plate 10 and an AlN buffer layer 20D of non-polar orientation. The AlN buffer layer comprises a surface protection layer 22 and a smoothing layer 26. The surface protection layer suppresses roughness increase on a surface of the AlN buffer layer, and the smoothing layer makes the surface of the AlN buffer layer a smoothed surface. Also provided is a crystal substrate 11 comprising an AlN buffer layer 20T to which a dislocation blocking layer 24 for reducing crystallographic defects is added between the surface protection layer 22 and the smoothing layer 26. In another embodiment a deep UV light-emitting device is provided.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 2, 2019
    Assignee: RIKEN
    Inventors: Masafumi Jo, Hideki Hirayama
  • Patent number: 10340338
    Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation structure having a first depth, and a gate electrode. The semiconductor substrate has source and drain regions, a reverse conductivity region having a second depth, a body region, and a drift region. The source region, the drift region, and the drain region are of a first conductivity type, and the body region and the reverse conductivity region are of a second conductivity type which is opposite to the first conductivity type. The insulating isolation structure is disposed between the drain region and the reverse conductivity region. The first depth is larger than the second depth.
    Type: Grant
    Filed: November 11, 2017
    Date of Patent: July 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Mori
  • Patent number: 10332980
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 25, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Zhaoxu Shen
  • Patent number: 10326034
    Abstract: A semiconductor layer includes a first semiconductor layer containing a III-V group compound semiconductor and having a first conductivity type, a quantum-well structure containing a III-V group compound semiconductor, a second semiconductor layer containing a III-V group compound semiconductor, a third semiconductor layer containing a III-V group compound semiconductor, and a fourth semiconductor layer containing a III-V group compound semiconductor and having a second conductivity type different from the first conductivity type. The first semiconductor layer, the quantum-well structure, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are stacked in this order. The concentration of an impurity that generates carriers of the second conductivity type is lower in the third semiconductor layer than in the fourth semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 18, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Suguru Arikata, Takuma Fuyuki, Susumu Yoshimoto, Takashi Kyono, Katsushi Akita
  • Patent number: 10319857
    Abstract: A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fen Chen, Chui-Ya Peng, Ching Yu, Pin-Hen Lin, Yen Chuang, Yuh-Ta Fan
  • Patent number: 10319643
    Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes depositing a strain relaxed buffer (SRB) layer over a substrate; recessing the SRB layer on a first region of the structure; and forming a first semiconductor layer on the first region of the structure and depositing one or more mandrels over the first semiconductor layer of the first region of the structure. The method further includes depositing a spacer layer over the one or more mandrels, the spacer layer including vertical portions and horizontal portions; and removing the one or more mandrels and the horizontal portions of the spacer layer. The method further includes performing a reactive ion etch to remove material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer. The first channel has a compressive strain.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10312665
    Abstract: An optical semiconductor device includes an InP substrate; an active layer disposed above the InP substrate; a n-type semiconductor layer disposed below the active layer; and a p-type clad layer disposed above the active layer, wherein the p-type clad layer includes one or more p-type In1-xAlxP layers, the Al composition x of each of the one or more p-type In1-xAlxP layers is equal to or greater than a value corresponding to the doping concentration of a p-type dopant, and the absolute value of the average strain amount of the whole of the p-type clad layer is equal to or less than the absolute value of a critical strain amount obtained by Matthews' relational expression, using the entire layer thickness of the whole of the p-type clad layer as a critical layer thickness.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 4, 2019
    Assignee: Oclaro Japan, Inc.
    Inventors: Takeshi Kitatani, Kaoru Okamoto, Kouji Nakahara
  • Patent number: 10297712
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 21, 2019
    Assignee: Apple Inc.
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 10290614
    Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Valluri Rao, Niloy Mukherjee, Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Jack Kavalieros
  • Patent number: 10290709
    Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros
  • Patent number: 10283636
    Abstract: A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10276699
    Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 30, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
  • Patent number: 10269933
    Abstract: A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor strip is etched to form a recess, wherein the recess is located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. After the recessing, a dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions, wherein the dielectric mask layer further extends on a sidewall of the gate stack.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 10269971
    Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Martin Christopher Holland
  • Patent number: 10256239
    Abstract: A method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates. The method further includes removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers including a first portion proximate the top surface of the substrate having a first width and a second portion above the first portion with a second width smaller than the first width.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian Pranatharthiharan, Eric R. Miller, Soon-Cheon Seo, John R. Sporre
  • Patent number: 10256157
    Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 9, 2019
    Assignee: IMEC VZW
    Inventors: Clement Merckling, Guillaume Boccardi
  • Patent number: 10256301
    Abstract: A semiconductor device includes a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers, a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures, and a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventor: Alexander Reznicek
  • Patent number: 10249736
    Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Chun-chen Yeh
  • Patent number: 10249490
    Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
  • Patent number: 10243102
    Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a light-emitting diode (LED) includes a substrate, a carrier confinement (CC) region positioned over the substrate, and an active region positioned over the CC region. The CC region includes a first CC layer comprising indium gallium phosphide and a second CC layer positioned over the first CC layer. The second CC layer includes gallium arsenide phosphide. The active region is configured to have a transient response time of less than 500 picoseconds (ps).
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 26, 2019
    Assignee: LUMEOVA, INC.
    Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami
  • Patent number: 10229997
    Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel
  • Patent number: 10211203
    Abstract: A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Xi Lin, Yi Hua Shen, Jian Pan
  • Patent number: 10205021
    Abstract: Method of fabrication of a semiconductor substrate including fabrication of a semiconducting layer such that a first part of the semiconducting layer comprises a compressively strained semiconductor and such that a second part of the semiconducting layer comprises a material different from the compressively strained semiconductor. The second part of the semiconducting layer is located in a principal plane of the semiconducting layer in contact with at least two opposite edges of the first part of the semiconducting layer. The method further includes etching of a trench through the semiconducting layer, delimiting the first part of the semiconducting layer and portions of the second part of the semiconducting layer located in contact with the opposite edges of the first part of the semiconducting layer, relative to the remaining part of the semiconducting layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 12, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGEES ALTERNATIVES
    Inventor: Shay Reboh
  • Patent number: 10192968
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gun You, Myung-Yoon Um, Young-Joon Park, Jeong-Hyo Lee, Ji-Yong Ha, Jun-Sun Hwang
  • Patent number: 10177235
    Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10177150
    Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junggil Yang, Sangsu Kim, TaeYong Kwon, Sung Gi Hur
  • Patent number: 10163904
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first circuit, a second circuit, and a dielectric dummy gate over a substrate. The first circuit includes a first N-type fin field-effect transistor (FinFET) and a first P-type fin field-effect transistor (FinFET). The second circuit includes a second N-type fin field-effect transistor (FinFET) and a second P-type fin field-effect transistor (FinFET) beside the second N-type FinFET. The dielectric dummy gate is positioned on a common boundary portion shared by the first circuit and the second circuit. The dielectric dummy gate includes a first portion and a second portion. The first portion is positioned between the first N-type FinFET and the second N-type FinFET and formed of a first strain material. The second portion is positioned between the first P-type FinFET and the second P-type FinFET and formed of a second strain material.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10163677
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser
  • Patent number: 10164099
    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
  • Patent number: 10145518
    Abstract: The present invention relates to a nano-scale light emitting diode (LED) electrode assembly emitting polarized light, a method of manufacturing the same, and a polarized LED lamp having the same, and more particularly, to a nano-scale LED electrode assembly in which partially polarized light close to light that is linearly polarized having one direction is emitted as an emitted light when applying a driving voltage to the nano-scale LED electrode assembly and also nano-scale LED devices are connected to a nano-scale electrode without defects such as an electrical short circuit while maximizing a light extraction efficiency, a method of manufacturing the same, and a polarized LED lamp having the same.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yeon Goog Sung
  • Patent number: 10141432
    Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 10141470
    Abstract: The invention relates to a photodiode type structure (comprising: a support (100) including at least one semiconductor layer, the semiconductor layer (120) including of a first semiconductor zone (10) of a first type of conductivity and a mesa (130) in contact with the semiconductor layer (120). The mesa (130) includes of a second semiconductor zone (20), known as absorption zone, said second semiconductor zone (20) being of a second type of conductivity. The second semiconductor zone has a concentration of majority carriers such that the second semiconductor zone (30) is depleted in the absence of polarization of the structure (1). The structure (1) further comprises a third semiconductor zone (30) of the second type of conductivity made of a third material transparent in the absorbed wavelength range. The third semiconductor zone (30) is interposed between the first and the second semiconductor zones (10, 20) while being at least partially arranged in the semiconductor layer (120).
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Boulard, Giacomo Badano, Olivier Gravrand
  • Patent number: 10141312
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin. The semiconductor device includes a second insulating material in a second fin. The first and second insulating materials have different respective sizes. For example, in some embodiments, the first and second insulating materials have different respective widths and/or depths in the first and second fins, respectively.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Jeon, Young-Gun Ko, Gi-Gwan Park, Je-Min Yoo
  • Patent number: 10121788
    Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Wei Zhao, Hong Yu, Xusheng Wu, Hui Zang, Zhenyu Hu
  • Patent number: 10121706
    Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rinus T. P. Lee, Bharat V. Krishnan, Hui Zang, Matthew W. Stoker
  • Patent number: 10121881
    Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: November 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
  • Patent number: 10121960
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The method includes providing a free layer, providing a pinned layer and providing a nonmagnetic spacer between the free and pinned layers. The free layer is switchable between stable magnetic states using a write current passed through the magnetic junction. At least one of the step of providing the free layer and the step of providing the pinned layer includes depositing a magnetic layer; depositing an adsorber layer on the magnetic layer and performing at least one anneal. The magnetic layer is amorphous as-deposited and includes an interstitial glass-promoting component. The adsorber layer attracts the interstitial glass-promoting component and has a lattice mismatch with the nonmagnetic spacer layer of not more than ten percent. Each of the anneal(s) is at a temperature greater than 300 degrees Celsius and not more than 425 degrees Celsius.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Roman Chepulskyy, Dmytro Apalkov
  • Patent number: 10109763
    Abstract: A light-emitting device that may be manufactured includes an n-type semiconductor layer including a first dopant on a substrate, an active layer on the n-type semiconductor layer, and a p-type semiconductor layer including a second dopant on the active layer. The light-emitting device may be formed according to at least one of a first layering process and a second layering process. The first layering process may include implanting the first dopant into the n-type semiconductor layer into the n-type semiconductor layer according to an ion-implantation process, and the second layering process may include implanting the second dopant into the p-type semiconductor layer according to an ion-implantation process. Forming a semiconductor layer that includes an ion-implanted dopant may include thermally annealing the semiconductor layer subsequent to the ion implantation.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Jae-sung Hyun, Dong-yul Lee, Jung-kyu Park
  • Patent number: 10101303
    Abstract: A capacitive micromachined ultrasonic transducer includes a first insulating film and a second insulating film disposed with a gap therebetween, a first electrode and a second electrode disposed on outer surfaces of the first and second insulating films, respectively, with the gap therebetween, at least one cell having an electrostatic capacitance between the first and second electrodes that varies with a variation of a thickness of the gap caused by displacement of the second insulating film and the second electrode, and a voltage applying unit configured to apply a voltage to between the first electrode and the second electrode. An electric field strength applied to the first insulating film is closer to an electric field strength that causes dielectric breakdown than an electric field strength applied to the second insulating film.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ayako Kato, Kazutoshi Torashima
  • Patent number: 10103263
    Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Van H. Le, Harold W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack Kavalieros, Niloy Mukherjee
  • Patent number: 10096523
    Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alexander Kalnitsky, Kong-Beng Thei
  • Patent number: 10084043
    Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Sanaz K. Gardner, Marko Radosavljevic, Glenn A. Glass