With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 10784371
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10763368
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 10755984
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Ying Pang, Nabil G. Mistkawi, Anand S. Murthy, Tahir Ghani, Huang-Lin Chao
  • Patent number: 10734527
    Abstract: A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si1-xGex, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10734374
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Patent number: 10727349
    Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Dong Hyun Roh, Koung Min Ryu, Sang Jin Hyun
  • Patent number: 10727312
    Abstract: A nitride semiconductor device includes: an electron transit layer including GaxIn1-xN (0<x?1); an electron supply layer formed on the electron transit layer and including AlyIn1-yN (0<y?1); a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween, wherein, in the electron transit layer, a portion contacting the gate insulating film and a portion contacting the electron transit layer are flush with each other.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: July 28, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Shinya Takado, Minoru Akutsu, Taketoshi Tanaka, Norikazu Ito
  • Patent number: 10727054
    Abstract: A nitride-based semiconductor device includes a patterned substrate having an etched surface that is formed with a plurality of protrusions, an aluminum nitride (AlN)-based film disposed on the etched surface, and a nitride-based semiconductor stacked structure disposed on the aluminum nitride-based film. Each of the protrusions has a side face. The AlN-based film includes a plurality of crystal defects formed on the side face of each protrusion. Each of the crystal defects has a width of smaller than 20 nm and/or the number of the crystal defects that are formed on the side face of each protrusion and that have a width of greater than 10 nm is less than 10. A method for preparing the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Xueliang Zhu, Jianming Liu, Chang-Cheng Chuo, Bing-Yang Chen, Chen-ke Hsu, Chung-Ying Chang
  • Patent number: 10727303
    Abstract: Provided is a Group III nitride epitaxial substrate that can suppress the occurrence of breakage during a device formation process and a method for manufacturing the same. A Group III nitride epitaxial substrate according to the present invention includes a Si substrate, an initial layer in contact with the Si substrate, and a superlattice laminate, formed on the initial layer, including a plurality of sets of laminates, each of the laminates including, in order, a first layer made of AlGaN with an Al composition ratio greater than 0.5 and 1 or less and a second layer made of AlGaN with an Al composition ratio greater than 0 and 0.5 or less. The Al composition ratio of the second layer progressively decreases with distance from the substrate.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: July 28, 2020
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Tomohiko Shibata
  • Patent number: 10720426
    Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 21, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Kuang-Hao Chiang, Dai-Ying Lee
  • Patent number: 10707332
    Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo
  • Patent number: 10692865
    Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Patent number: 10693038
    Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure on the active region; a first In-containing layer between the active region and the electron blocking structure; and a second In-containing layer on the electron blocking structure; wherein the first In-containing layer has a first indium content, the second In-containing layer has a second indium content, and the second indium content is different from the first indium content.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 23, 2020
    Assignee: EPISTAR Corporation
    Inventors: Huan-Yu Lai, Li-Chi Peng
  • Patent number: 10680150
    Abstract: The invention comprises a solid state infrared source and method of use thereof comprising: (1) an electrically conductive film, comprising a semi-transparent material, the semi-transparent material comprising a transmission property of at least forty percent, wherein at least forty percent of internal infrared emissions from the electrically conductive film transmit to an outer surface of the electrically conductive film, wherein the infrared emissions comprise a peak intensity between 3.9 and 6 micrometers; (2) a first silicon nitride layer; and (3) a second silicon nitride layer, the electrically conductive film positioned between the first silicon nitride layer and the second silicon nitride layer, where applying an electric current of less than one Watt through the electrically conductive film raises a temperature of the electrically conductive film to in excess of eight hundred degrees centigrade in less than twenty milliseconds resultant in the infrared emissions.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 9, 2020
    Inventors: Dragan Grubisik, Davorin Babic, Alex Kropachev, Arshey Patadia, Viet Nguyen
  • Patent number: 10672899
    Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
  • Patent number: 10672889
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate. A trench is formed in an <xyz> crystallographic direction of the semiconductor substrate in the isolation region. An epitaxial layer is grown in the trench. The epitaxial layer is patterned to form a semiconductor fin orientated along an <x?y?z?> crystallographic direction of the semiconductor substrate, wherein <x?y?z?>?<xyz>.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis
  • Patent number: 10665750
    Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer including a first dopant of a first conductivity type and a second dopant of a second conductivity type, wherein the first dopant has a doping concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant including a doping concentration higher than the doping concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, and the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Epistar Corporation
    Inventors: Jing-Jie Dai, Tzu-Chieh Hu
  • Patent number: 10658541
    Abstract: According to at least some embodiments of the present disclosure, a method of manufacturing semiconductor wafers comprises: selectively growing a nitride buffer layer on a first surface of a patterned substrate, the patterned substrate including at least the first surface and a second surface; and growing an epitaxial layer on the nitride buffer layer, wherein a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate. The epitaxial layer does not include multiple crystal surfaces having different crystal growth directions that cause a stress at a junction interface where the crystal surfaces having the different crystal growth directions meet.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Zhiwei Lin, Xiangjing Zhou, Gang Yao, Aimin Wang
  • Patent number: 10651308
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10644106
    Abstract: Disclosed is a semiconductor device that comprises a substrate including a first active pattern vertically protruding from a top surface of the substrate, and a first source/drain pattern filing a first recess formed on an upper portion of the first active pattern. The first source/drain pattern comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern. The first semiconductor pattern has a first face, a second face, and a first corner edge defined when the first face and the second face meet with each other. The second semiconductor pattern covers the first face and the second face of the first semiconductor pattern and exposes the first corner edge.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choeun Lee, Seokhoon Kim, Sanggil Lee, Seung Hun Lee, Min-Hee Choi
  • Patent number: 10615178
    Abstract: In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Effendi Leobandung, Brent A. Wacaser
  • Patent number: 10600676
    Abstract: Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 ?/sq or less.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: March 24, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Akihiro Hachigo, Yuki Hiromura, Naoki Matsumoto, Seiji Nakahata, Fumitake Nakanishi, Takuya Yanagisawa, Koji Uematsu, Yuki Seki, Yoshiyuki Yamamoto, Yusuke Yoshizumi, Hidenori Mikami
  • Patent number: 10600914
    Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren, Hui Zang, Scott H. Beasor, Ruilong Xie
  • Patent number: 10573782
    Abstract: Disclosed is an infrared light emitting device including: a semiconductor substrate; a first layer formed on the semiconductor substrate and having a first conductivity type; a light emitting layer formed on the first layer; and a second layer formed on the light emitting layer and having a second conductivity type, wherein the first layer includes, in the stated order: a layer containing Alx(1)In1?x(1)Sb; a layer having a film thickness ty(1) in nanometers and containing Aly(1)In1?y(1)Sb; and a layer containing Alx(2)In1?x(2)Sb, where ty(1), x(1), x(2), and y(1) satisfy the following relations: for j=1, 2, 0<ty(1)?2360×(y(1)?x(j))?240 (0.11?y(1)?x(j)?0.19), 0<ty(1)??1215×(y(1)?x(j))+427 (0.19<y(1)?x(j)?0.33), and 0<x(j)<0.18.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 25, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Morohara, Hiromi Fujita, Hirotaka Geka
  • Patent number: 10559692
    Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Xin Miao, Jingyun Zhang, Choonghyun Lee
  • Patent number: 10553712
    Abstract: The present disclosure provides a superjunction based design for normally-OFF HEMT that has two key components: (i) a recessed high-K metal gate and (ii) a superjunction layer under the gate, which is embedded within the N-type GaN buffer layers and separated from recessed gate. Recess gate is to deplete the 2 DEG from the channel region (under the gate) when the transistor is under OFF state. The present disclosure provides a new, improved, efficient and technically advanced HEMT device which can provide higher breakdown voltage, when compared to designs available in the prior-art, without affecting the performance figure of merits. Further, the new HEMT device offers improved breakdown voltage as compared to ON-resistance trade-off, improved the short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device lowers gate-to-drain (miller) capacitance and is available at low cost.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 4, 2020
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY
    Inventor: Mayank Shrivastava
  • Patent number: 10546878
    Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10541372
    Abstract: A light-emitting device having a curved light-emitting surface is provided. Further, a highly-reliable light-emitting device is provided. A substrate with plasticity is used. A light-emitting element is formed over the substrate in a flat state. The substrate provided with the light-emitting element is curved and put on a surface of a support having a curved surface. Then, a protective layer for protecting the light-emitting element is formed in the same state. Thus, a light-emitting device having a curved light-emitting surface, such as a lighting device or a display device can be manufactured.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yohei Momma, Tomohiko Suganoya, Saki Obana
  • Patent number: 10541238
    Abstract: A method is provided for fabricating a FinFET. The method includes providing a substrate including an NMOS region; forming a plurality of fins on the substrate; forming an isolation layer between adjacent fins and on the substrate; forming a gate structure across a length portion of the fin; forming a first mask layer on the top surface and sidewalls of the fin; etching the first mask layer to expose the top surface of the fin on both sides of the gate structure; removing a thickness portion of the fin on both sides of the gate structure, wherein the etched fin and the remaining first mask layer form a first trench; performing a thinning treatment of the remaining first mask layer on a sidewall of the first trench to increase width of the first trench; and forming an N-type in-situ doped epitaxial layer to fill up the first trench.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 21, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10538858
    Abstract: In a method for manufacturing a group 13 nitride crystal, a seed crystal made of a group 13 nitride crystal is arranged in a mixed melt containing an alkali metal and a group 13 element, and nitrogen is supplied to the mixed melt to grow the group 13 nitride crystal on a principal plane of the seed crystal. The seed crystal is manufactured by vapor phase epitaxy. At least a part of contact members coming into contact with the mixed melt in a reaction vessel accommodating the mixed melt is made of Al2O3. An interface layer having a photoluminescence emission peak whose wavelength is longer than the wavelength of a photoluminescence emission peak of the grown group 13 nitride crystal is formed between the seed crystal and the grown group nitride crystal.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: January 21, 2020
    Assignee: SCIOCS COMPANY LIMITED
    Inventors: Masahiro Hayashi, Takashi Satoh, Naoya Miyoshi, Junichi Wada, Seiji Sarayama
  • Patent number: 10535685
    Abstract: Thin-film electronic devices such as LED devices and field effect transistor devices are fabricated using a non-destructive epitaxial lift-off technique that allows indefinite reuse of a growth substrate. The method includes providing an epitaxial protective layer on the growth substrate and a sacrificial release layer between the protective layer and an active device layer. After the device layer is released from the growth substrate, the protective layer is selectively etched to provide a newly exposed surface suitable for epitaxial growth of another device layer. The entire thickness of the growth substrate is preserved, enabling continued reuse. Inorganic thin-film device layers can be transferred to a flexible secondary substrate, enabling formation of curved inorganic optoelectronic devices.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: January 14, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Stephen R. Forrest, Kyusang Lee
  • Patent number: 10522537
    Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwa Kim, Kyungin Choi, Hwichan Jun, Inchan Hwang
  • Patent number: 10522345
    Abstract: A method includes receiving a semiconductor substrate including a first semiconductor material; etching a portion of the semiconductor substrate, thereby forming a recess, a bottom portion of the recess having a first sidewall and a second sidewall intersecting with each other, one of the first and second sidewalls exposing a (111) crystallographic plane of the semiconductor substrate; and epitaxially growing a second semiconductor material in the recess, the second semiconductor material having lattice mismatch to the first semiconductor material, dislocations in the second semiconductor material due to the lattice mismatch propagating from the first sidewall to the second sidewall in a direction parallel to a top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hsien Wu, I-Sheng Chen
  • Patent number: 10504887
    Abstract: The present disclosure provides a method for forming an electrostatic discharge (ESD) protection device, including: providing a substrate including an input region; forming a plurality of fins on the substrate in the input region; forming a well region, doped with first-type ions, in the plurality of fins and in the substrate; and forming an epitaxial layer on each fin in the input region. The method further includes: forming a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; forming an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and forming a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 10, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10497797
    Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: December 3, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Kun-Hsin Chen, Tien-I Wu, Yu-Ru Yang, Huai-Tzu Chiang
  • Patent number: 10490652
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: November 26, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 10483263
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method therefor.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 19, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manfacturing International (Beijing) Corp.
    Inventor: Fei Zhou
  • Patent number: 10483353
    Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: November 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Willy Rachmady, Gilbert Dewey, Tahir Ghani, Jack T. Kavalieros
  • Patent number: 10475744
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: November 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kuan-Hung Chen, Rung-Yuan Lee, Chun-Tsen Lu
  • Patent number: 10461184
    Abstract: A semiconductor device includes a semiconductor substrate having a first source or drain (S/D) region and a channel. The channel includes a first semiconductor material having a first band gap, and extends vertically from a lower channel portion formed on the first S/D region to an upper channel portion located opposite the lower channel portion. A gate structure is around sidewalls of the channel, and a second S/D region is on the upper channel portion. A band-gap enhancing region is interposed between the second S/D region and the channel. The band-gap enhancing region includes a second semiconductor material having a second band gap that is greater than the first band gap to reduce a gate-induced-drain leakage (GIDL) between the second S/D region and the channel.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee
  • Patent number: 10461216
    Abstract: Gallium nitride based devices and, more particularly to the generation of holes in gallium nitride based devices lacking p-type doping, and their use in light emitting diodes and lasers, both edge emitting and vertical emitting. By tailoring the intrinsic design, a wide range of wavelengths can be emitted from near-infrared to mid ultraviolet, depending upon the design of the adjacent cross-gap recombination zone. The innovation also provides for novel circuits and unique applications, particularly for water sterilization.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: October 29, 2019
    Assignee: Wright State University
    Inventors: Elliott R. Brown, Weidong Zhang, Tyler Growden, Paul R. Berger, David Storm, David Meyer
  • Patent number: 10439066
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 8, 2019
    Assignee: United Miccroelectronics Corp.
    Inventors: Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 10431729
    Abstract: According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.
    Type: Grant
    Filed: July 8, 2017
    Date of Patent: October 1, 2019
    Assignee: Ambature, Inc.
    Inventors: Michael S. Lebby, Davis H. Hartmann
  • Patent number: 10424657
    Abstract: A tri-gate FinFET device includes a fin that is positioned vertically above and spaced apart from an upper surface of a semiconductor substrate, wherein the fin has an upper surface, a lower surface opposite of the upper surface, a first side surface, and a second side surface opposite of the first side surface. The axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the semiconductor substrate, and the first side surface of the fin contacts an insulating material. A gate structure is positioned around the upper surface, the second side surface, and the lower surface of the fin, and a gate contact structure is conductively coupled to the gate structure.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr
  • Patent number: 10418240
    Abstract: A nitride semiconductor structure includes a substrate, a nitride semiconductor layer, and a buffer stack layer between the substrate and the nitride semiconductor layer. The buffer stack layer includes a plurality of metal nitride multilayers repeatedly stacked, wherein each of the metal nitride multilayers consists of a first, a second, and a third metal nitride thin films in sequence, or consists of the first, the third, the second, and the third metal nitride thin films in sequence. The aluminum concentration of the first metal nitride thin film is higher than that of the third metal nitride thin film, and the aluminum concentration of the third metal nitride thin film is higher than that of the second metal nitride thin film.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: ELITE ADVANCED LASER CORPORATION
    Inventors: Kun-Chuan Lin, Jin-Hsiang Liu, Yu-Lin Hsiao
  • Patent number: 10410859
    Abstract: An epitaxial substrate for semiconductor elements which suppresses the occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer adjacent to the free-standing substrate; a channel layer adjacent to the buffer layer; and a barrier layer provided on an opposite side of the buffer layer with the channel layer provided therebetween, wherein the buffer layer is a diffusion suppressing layer that suppresses the diffusion of Zn from the free-standing substrate into the channel layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 10, 2019
    Assignee: NGK INSULATORS, LTD.
    Inventors: Mikiya Ichimura, Sota Maehara, Yoshitaka Kuraoka
  • Patent number: 10411112
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki Tsunomura, Toshiaki Iwamatsu
  • Patent number: 10411125
    Abstract: A semiconductor device includes a semiconductor structure including a first doped layer for forming a carrier channel having a carrier charge, a second doped layer having a conductivity type identical to a conductivity type of the first doped layer, a barrier layer arranged in proximity to the semiconductor structure via the second doped layer, wherein the barrier layer includes a partially doped layer having a conductivity type opposite to the conductivity type of the second doped layer, and a set of electrodes for providing and controlling the carrier charge in the carrier channel.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: September 10, 2019
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Chenjie Tang
  • Patent number: 10396153
    Abstract: A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 27, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 10396203
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi