With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 11121285
    Abstract: A semiconductor device includes a conductive layer, a semiconductor stack, a first contact structure, an intermediate structure, a second contact structure, a first electrode and a second electrode. The semiconductor stack is disposed on the conductive layer. The first contact structure is disposed on the semiconductor stack. The intermediate structure encloses the first contact structure. The second contact structure is between the conductive layer and the semiconductor stack. The first electrode is on the conductive layer and separated from the semiconductor stack. The second electrode is on the intermediate structure.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Epistar Corporation
    Inventors: Yung-Fu Chang, Hui-Fang Kao, Yi-Tang Lai, Shih-Chang Lee, Wen-Luh Liao, Mei Chun Liu, Yao-Ru Chang, Yi Hisao
  • Patent number: 11101268
    Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Ritesh Jhaveri, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy, Tahir Ghani
  • Patent number: 11094812
    Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 17, 2021
    Assignee: Soitec Belgium
    Inventor: Joff Derluyn
  • Patent number: 11081570
    Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 11043494
    Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie, Deepika Priyadarshini, Indira Priyavarshini Seshadri, Nicole A. Saulnier
  • Patent number: 11031393
    Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Jeehwan Kim
  • Patent number: 11031290
    Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.
    Type: Grant
    Filed: January 21, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Shu-Yuan Ku, I-Wei Yang, Yi-Hsuan Hsiao, Ming-Ching Chang, Ryan Chia-Jen Chen
  • Patent number: 11031298
    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11024740
    Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11015263
    Abstract: Bulk single crystal of aluminum nitride (AlN) having an areal planar defect density?100 cm?2. Methods for growing single crystal aluminum nitride include melting an aluminum foil to uniformly wet a foundation with a layer of aluminum, the foundation forming a portion of an AlN seed holder, for an AlN seed to be used for the AlN growth. The holder may consist essentially of a substantially impervious backing plate.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: CRYSTAL IS, INC.
    Inventors: Robert T. Bondokov, Leo J. Schowalter, Kenneth Morgan, Glen A. Slack, Shailaja P. Rao, Shawn Robert Gibb
  • Patent number: 11001938
    Abstract: Provided are a diamond composite body capable of shortening a separation time for separating a substrate and a diamond layer, the substrate, and a method for manufacturing a diamond, as well as a diamond obtained from the diamond composite body and a tool including the diamond. The diamond composite body includes a substrate including a diamond seed crystal and having grooves in a main surface, a diamond layer formed on the main surface of the substrate, and a non-diamond layer formed on a substrate side at a constant depth from an interface between the substrate and the diamond layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: May 11, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Nishibayashi, Natsuo Tatsumi, Hitoshi Sumiya
  • Patent number: 11004688
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Patent number: 11004951
    Abstract: A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • Patent number: 10998435
    Abstract: An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 4, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10978486
    Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 13, 2021
    Inventors: Ho-Jun Kim, Jaehyeoung Ma, Geumjong Bae
  • Patent number: 10978582
    Abstract: Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10971605
    Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Patent number: 10971648
    Abstract: An embodiment relates to an ultraviolet light-emitting device, a method for manufacturing the ultraviolet light-emitting element, a light-emitting element package, and a lighting device. An ultraviolet light-emitting element according to an embodiment includes: a first conductive type first semiconductor layer having a light extraction structure; an etching-blocking layer on the first conductive type first semiconductor layer; a first conductive type second semiconductor layer on the etching-blocking layer, an active layer on the first conductive type second semiconductor layer; a second conductive type semiconductor layer on the active layer; and an electron spreading layer disposed between the etching-blocking layer and the active layer, wherein the electron spreading layer includes a first conductive type or an undoped AlGaN-based or a GaN-based semiconductor layer, an undoped AlN, and a first conductive type AlGaN-based second semiconductor layer.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: April 6, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chan Keun Park, Sul Hee Kim
  • Patent number: 10932684
    Abstract: In some embodiments, a microelectronic sensor includes an open-gate pseudo-conductive high-electron mobility transistor and used for air quality monitoring. The transistor comprises a substrate, on which a multilayer hetero-junction structure is deposited. This hetero-junction structure comprises a buffer layer and a barrier layer, both grown from III-V single-crystalline or polycrystalline semiconductor materials. A two-dimensional electron gas (2DEG) conducting channel is formed at the interface between the buffer and barrier layers and provides electron current in the system between source and drain electrodes. The source and drain contacts are non-ohmic (capacitively-coupled) and connected to the formed 2DEG channel and to the electrical metallizations, the latter are placed on top of the transistor and connect it to the sensor system. The metal gate electrode is placed between the source and drain areas on or above the barrier layer, which may be recessed or grown to a specific thickness.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 2, 2021
    Assignee: EPITRONIC HOLDINGS PTE LTD.
    Inventor: Ayal Ram
  • Patent number: 10930766
    Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner
  • Patent number: 10923403
    Abstract: Embodiments of the invention are directed to fin-based field effect transistor (FET) devices formed on a substrate. In a non-limiting example, the devices a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin includes a top region, a central region, and a bottom region. The central region of the first fin includes an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level. The top region of the first fin includes the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level, along with an anneal-induced second concentration level of the first type of semiconductor material. A final concentration level of the first type of semiconductor material in the top region includes the first concentration level and the second concentration level.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 10896992
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson
  • Patent number: 10886269
    Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Shi-Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10867993
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 15, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
  • Patent number: 10867848
    Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
  • Patent number: 10854748
    Abstract: A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly SU, Pang-Yen Tsai, Tze-Liang Lee, Chii-Horng Li, Yen-Ru Lee, Ming-Hua Yu
  • Patent number: 10854607
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Patent number: 10833063
    Abstract: A multi-gate High Electron Mobility Transistor (HEMT) can include a Two-Dimension Electron Gas (2DEG) channel between the drain and the source. A first gate can be disposed proximate the 2DEG channel between the drain and source. The first gate can be configured to deplete majority carriers in the 2DEG channel proximate the first gate when a potential applied between the first gate and the source is less than a threshold voltage associated with the first gate. A second gate can be disposed proximate the 2DEC channel, between the drain and the first gate. The second gate can be electrically coupled to the drain. The second gate can be configured to deplete majority carriers in the 2DEG channel proximate the second gate when a potential applied between the second gate and the 2DEG channel between the second gate and the first gate is less than a threshold voltage associated with the second gate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 10, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Muhammad Ayman Shibib, Chungchi Gina Liao
  • Patent number: 10825895
    Abstract: A nitride semiconductor substrate can effectively reduce leakage current in the vertical direction. The nitride semiconductor substrate comprises a buffer layer and an operation layer, both of which are made of nitride semiconductor, deposited on a silicon single crystal substrate, wherein the buffer layer comprises a single-layered first initial layer in contact with the silicon single crystal layer, and a single-layered second initial layer in contact with the first initial layer, the first initial layer is made of AlN, the second initial layer is made of AlzGa1-zN (0.12?z?0.65), and in an X-Y graph where the X-axis denotes z×100 and the Y-axis denotes carbon concentration in the second initial layer, X ranges from 12 to 65 and Y is within a range between Y=1E+17×exp(?0.05×X) and Y=1E+21×exp(?0.05×X).
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 3, 2020
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Jun Komiyama
  • Patent number: 10818757
    Abstract: There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually decreased from a substrate side toward a surface side of the drift layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 27, 2020
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Yoshinobu Narita
  • Patent number: 10784371
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10763368
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 10755984
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Ying Pang, Nabil G. Mistkawi, Anand S. Murthy, Tahir Ghani, Huang-Lin Chao
  • Patent number: 10734374
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Patent number: 10734527
    Abstract: A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si1-xGex, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10727312
    Abstract: A nitride semiconductor device includes: an electron transit layer including GaxIn1-xN (0<x?1); an electron supply layer formed on the electron transit layer and including AlyIn1-yN (0<y?1); a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween, wherein, in the electron transit layer, a portion contacting the gate insulating film and a portion contacting the electron transit layer are flush with each other.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: July 28, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Shinya Takado, Minoru Akutsu, Taketoshi Tanaka, Norikazu Ito
  • Patent number: 10727349
    Abstract: A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Dong Hyun Roh, Koung Min Ryu, Sang Jin Hyun
  • Patent number: 10727054
    Abstract: A nitride-based semiconductor device includes a patterned substrate having an etched surface that is formed with a plurality of protrusions, an aluminum nitride (AlN)-based film disposed on the etched surface, and a nitride-based semiconductor stacked structure disposed on the aluminum nitride-based film. Each of the protrusions has a side face. The AlN-based film includes a plurality of crystal defects formed on the side face of each protrusion. Each of the crystal defects has a width of smaller than 20 nm and/or the number of the crystal defects that are formed on the side face of each protrusion and that have a width of greater than 10 nm is less than 10. A method for preparing the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Xueliang Zhu, Jianming Liu, Chang-Cheng Chuo, Bing-Yang Chen, Chen-ke Hsu, Chung-Ying Chang
  • Patent number: 10727303
    Abstract: Provided is a Group III nitride epitaxial substrate that can suppress the occurrence of breakage during a device formation process and a method for manufacturing the same. A Group III nitride epitaxial substrate according to the present invention includes a Si substrate, an initial layer in contact with the Si substrate, and a superlattice laminate, formed on the initial layer, including a plurality of sets of laminates, each of the laminates including, in order, a first layer made of AlGaN with an Al composition ratio greater than 0.5 and 1 or less and a second layer made of AlGaN with an Al composition ratio greater than 0 and 0.5 or less. The Al composition ratio of the second layer progressively decreases with distance from the substrate.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: July 28, 2020
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Tomohiko Shibata
  • Patent number: 10720426
    Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 21, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Kuang-Hao Chiang, Dai-Ying Lee
  • Patent number: 10707332
    Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo
  • Patent number: 10693038
    Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure on the active region; a first In-containing layer between the active region and the electron blocking structure; and a second In-containing layer on the electron blocking structure; wherein the first In-containing layer has a first indium content, the second In-containing layer has a second indium content, and the second indium content is different from the first indium content.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 23, 2020
    Assignee: EPISTAR Corporation
    Inventors: Huan-Yu Lai, Li-Chi Peng
  • Patent number: 10692865
    Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Patent number: 10680150
    Abstract: The invention comprises a solid state infrared source and method of use thereof comprising: (1) an electrically conductive film, comprising a semi-transparent material, the semi-transparent material comprising a transmission property of at least forty percent, wherein at least forty percent of internal infrared emissions from the electrically conductive film transmit to an outer surface of the electrically conductive film, wherein the infrared emissions comprise a peak intensity between 3.9 and 6 micrometers; (2) a first silicon nitride layer; and (3) a second silicon nitride layer, the electrically conductive film positioned between the first silicon nitride layer and the second silicon nitride layer, where applying an electric current of less than one Watt through the electrically conductive film raises a temperature of the electrically conductive film to in excess of eight hundred degrees centigrade in less than twenty milliseconds resultant in the infrared emissions.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 9, 2020
    Inventors: Dragan Grubisik, Davorin Babic, Alex Kropachev, Arshey Patadia, Viet Nguyen
  • Patent number: 10672889
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region on a semiconductor substrate. A trench is formed in an <xyz> crystallographic direction of the semiconductor substrate in the isolation region. An epitaxial layer is grown in the trench. The epitaxial layer is patterned to form a semiconductor fin orientated along an <x?y?z?> crystallographic direction of the semiconductor substrate, wherein <x?y?z?>?<xyz>.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis
  • Patent number: 10672899
    Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
  • Patent number: 10665750
    Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer including a first dopant of a first conductivity type and a second dopant of a second conductivity type, wherein the first dopant has a doping concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant including a doping concentration higher than the doping concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, and the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Epistar Corporation
    Inventors: Jing-Jie Dai, Tzu-Chieh Hu
  • Patent number: 10658541
    Abstract: According to at least some embodiments of the present disclosure, a method of manufacturing semiconductor wafers comprises: selectively growing a nitride buffer layer on a first surface of a patterned substrate, the patterned substrate including at least the first surface and a second surface; and growing an epitaxial layer on the nitride buffer layer, wherein a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate. The epitaxial layer does not include multiple crystal surfaces having different crystal growth directions that cause a stress at a junction interface where the crystal surfaces having the different crystal growth directions meet.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Zhiwei Lin, Xiangjing Zhou, Gang Yao, Aimin Wang
  • Patent number: 10651308
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10644106
    Abstract: Disclosed is a semiconductor device that comprises a substrate including a first active pattern vertically protruding from a top surface of the substrate, and a first source/drain pattern filing a first recess formed on an upper portion of the first active pattern. The first source/drain pattern comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern. The first semiconductor pattern has a first face, a second face, and a first corner edge defined when the first face and the second face meet with each other. The second semiconductor pattern covers the first face and the second face of the first semiconductor pattern and exposes the first corner edge.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choeun Lee, Seokhoon Kim, Sanggil Lee, Seung Hun Lee, Min-Hee Choi