With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
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Patent number: 11973127Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.Type: GrantFiled: November 4, 2020Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
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Patent number: 11974508Abstract: According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.Type: GrantFiled: December 10, 2021Date of Patent: April 30, 2024Assignee: Ambature, Inc.Inventors: Michael S. Lebby, Davis H. Hartmann
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Patent number: 11973163Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.Type: GrantFiled: January 20, 2023Date of Patent: April 30, 2024Assignee: Tianjin Sanan Optoelectronics Co., Ltd.Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng Liu, Weihuan Li, Liming Shu, Chao Liu
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Patent number: 11972947Abstract: A semiconductor laminate film includes a silicon substrate and a semiconductor layer formed on the silicon substrate and containing silicon and germanium. The semiconductor layer having a surface roughness Rms of 1 nm or less. Further, the semiconductor layer satisfies the following relationship t?0.881×x?4.79 where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer. Also, the semiconductor layer being a mixed crystal semiconductor layer containing silicon and germanium.Type: GrantFiled: March 10, 2021Date of Patent: April 30, 2024Assignees: National University Corporation Tokyo University Of Agriculture And Technology, National Institute of Information and Communications TechnologyInventors: Yoshiyuki Suda, Takahiro Tsukamoto, Akira Motohashi, Kyohei Degura, Katsumi Okubo, Takuma Yagi, Akifumi Kasamatsu, Nobumitsu Hirose, Toshiaki Matsui
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Patent number: 11962900Abstract: In some embodiments, a ToF sensor includes an illumination source module, a transmitter lens module, a receiver lens module, and an integrated circuit that includes a ToF imaging array. The ToF imaging array includes a plurality of SPADs and a plurality of ToF channels coupled to the plurality of SPADs. In a first mode, the ToF imaging array is configured to select a first group of SPADs corresponding to a first FoV. In a second mode, the ToF imaging array is configured to select a second group of SPADs corresponding to a second FoV different than the first FoV.Type: GrantFiled: August 20, 2020Date of Patent: April 16, 2024Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: Neale Dutton, Stuart McLeod, Bruce Rae
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Patent number: 11963457Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.Type: GrantFiled: December 12, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
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Patent number: 11942378Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.Type: GrantFiled: February 18, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11935951Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.Type: GrantFiled: November 7, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung Tsai, Yuan-Ko Hwang
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Patent number: 11935793Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.Type: GrantFiled: May 29, 2020Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11923313Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.Type: GrantFiled: May 30, 2019Date of Patent: March 5, 2024Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 11908839Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.Type: GrantFiled: September 19, 2022Date of Patent: February 20, 2024Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist, Eli Lusky
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Patent number: 11910714Abstract: A thermoelectric conversion material contains a matrix composed of a semiconductor and nanoparticles disposed in the matrix, and the nanoparticles have a lattice constant distribution ?d/d of 0.0055 or more.Type: GrantFiled: August 11, 2021Date of Patent: February 20, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masahiro Adachi, Makoto Kiyama, Yoshiyuki Yamamoto, Ryo Toyoshima
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Patent number: 11901445Abstract: A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench.Type: GrantFiled: November 13, 2020Date of Patent: February 13, 2024Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jiacheng Lei, James Jerry Joseph, Lawrence Selvaraj Susai, Shyue Seng Tan
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Patent number: 11901433Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.Type: GrantFiled: August 24, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11894275Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.Type: GrantFiled: July 26, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ying-Keung Leung
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Patent number: 11887999Abstract: In a photodetector using GePDs, a photodetector having small change in light sensitivity due to temperature is provided. A photodetector includes a plurality of photodiodes formed on a silicon substrate and having germanium or a germanium compound in a light absorption layer, and two chips of integrated circuits arranged parallel to two sides connected to one corner of the silicon substrate, respectively, the two integrated circuits are connected to photodiodes formed on the silicon substrate, two or more of the photodiodes are arranged equidistantly from the integrated circuit that is parallel to one side connected to the one corner, and the numbers of equidistantly arranged photodiodes are equal, when viewed from the integrated circuits.Type: GrantFiled: January 15, 2020Date of Patent: January 30, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventor: Kotaro Takeda
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Patent number: 11854905Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
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Patent number: 11855187Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: GrantFiled: October 11, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
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Patent number: 11855142Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
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Patent number: 11855223Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.Type: GrantFiled: December 13, 2021Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
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Patent number: 11843032Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.Type: GrantFiled: March 30, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Siang Lan, Sathaiya Mahaveer Dhanyakumar, Tzer-Min Shen, Zhiqiang Wu
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Patent number: 11829786Abstract: Computer-readable media, methods, and systems for generating a collaboration hub for display within a graphical user interface of a group-based communication system. The collaboration hub comprises a list of recommended active users, a list of recommended active synchronous multimedia collaboration sessions, and a feed of recommended asynchronous collaboration threads such that relevant activity within the group-based communication system is viewable and accessible to users of the group-based communication system.Type: GrantFiled: September 21, 2022Date of Patent: November 28, 2023Assignee: Slack Technologies, LLCInventors: Noah Weiss, John Rodgers, Pedro Carmo, Michael Hahn
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Patent number: 11810977Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.Type: GrantFiled: March 31, 2021Date of Patent: November 7, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Teng-Yen Huang
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Patent number: 11799009Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.Type: GrantFiled: December 17, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani
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Patent number: 11791159Abstract: A method of producing a crystalline silicon film includes forming a first silicon film that is amorphous at formation, forming a doped film of silicon or germanium on the first silicon film, the doped film being amorphous at formation; and annealing the structure to crystallize the doped film and the first silicon film. A method of producing a crystalline silicon film includes forming a Six1Ge1-x1 film on a substrate, forming a Six2Ge1-x2 film on the Six1Ge1-x1 film, the Six1Ge1-x1 film being amorphous at formation and having a first thermal budget for crystallization, the Six2Ge1-x2 film being amorphous at formation and having a second thermal budget for crystallization, the second thermal budget being lower than the first thermal budget, forming a silicon film on the Six2Ge1-x2 film, the silicon film being amorphous at formation; and annealing to crystallize the Six1Ge1-x1 film, the Six2Ge1-x2 film, and the silicon film.Type: GrantFiled: July 24, 2020Date of Patent: October 17, 2023Inventor: Ramesh kumar Harjivan Kakkad
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Patent number: 11756938Abstract: A light emitting device includes: a substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; a light emitting diode between the first electrode and the second electrode and connected to the first and second electrodes; a first contact on the first electrode; and a second contact on the second electrode. The first contact contacts the first electrode and a first portion of the light emitting diode, and the second contact contacts the second electrode and a second portion of the light emitting diode.Type: GrantFiled: August 17, 2021Date of Patent: September 12, 2023Assignee: Samsung Display Co., Ltd.Inventors: Yeoung Keol Woo, Chui Min Bae, Heon Sik Ha
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Patent number: 11757257Abstract: A laser diode including a double heterostructure comprising a top layer, a buffer layer formed on a substrate, and an intrinsic active layer formed between the top layer and the buffer layer. The top layer and the buffer layer have opposite types of conductivity. The active layer has a bandgap smaller than that of the buffer layer or the top layer. The double heterostructure includes Ge, SiGe, GeSn, and/or SiGeSn materials.Type: GrantFiled: September 28, 2021Date of Patent: September 12, 2023Assignee: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSASInventors: Shui-Qing Yu, Yiyin Zhou, Wei Du
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Patent number: 11742202Abstract: A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers including stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The method may further include forming a body above the RF ground plane layer, forming spaced apart source and drain regions adjacent the body and defining a channel region in the body, and forming a gate overlying the channel region.Type: GrantFiled: March 3, 2022Date of Patent: August 29, 2023Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Robert J. Mears
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Patent number: 11744155Abstract: A piezoelectric element 10 includes a lower electrode, constituted of a Pt/Ti laminated film, a PLT seed layer, formed on the lower electrode, a PZT piezoelectric film, formed on the PLT seed layer, and an upper electrode, formed on the PZT piezoelectric film. A curve Q1 is a curve drawn such as to pass through a plurality of plotted points, each expressing a PLT (100) peak intensity with respect to a Pt (111) peak intensity according to a substrate setting temperature during forming of the Pt/Ti laminated film. A relationship of the PLT (100) peak intensity with respect to the Pt (111) peak intensity is within a range in the curve Q1 until the PLT (100) peak intensity decreases by 5% from a peak point P, at which the PLT (100) peak intensity is the maximum, and a (100) orientation rate of PLT constituting the seed layer is not less than 85%.Type: GrantFiled: February 15, 2022Date of Patent: August 29, 2023Assignee: ROHM CO., LTD.Inventors: Koji Nomura, Nobufumi Matsuo, Tomohiro Date
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Patent number: 11734031Abstract: Computer-readable media, methods, and systems for generating a collaboration hub for display within a graphical user interface of a group-based communication system. The collaboration hub comprises a list of recommended active users, a list of recommended active synchronous multimedia collaboration sessions, and a feed of recommended asynchronous collaboration threads such that relevant activity within the group-based communication system is viewable and accessible to users of the group-based communication system.Type: GrantFiled: September 21, 2022Date of Patent: August 22, 2023Assignee: Slack Technologies, LLCInventors: Noah Weiss, John Rodgers, Pedro Carmo, Michael Hahn
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Patent number: 11735483Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.Type: GrantFiled: February 26, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yao-Sheng Huang, I-Ming Chang, Huang-Lin Chao
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Patent number: 11714231Abstract: A semiconductor structure comprises a substrate; an oxide layer on the substrate; a set of group III nitride layers on the oxide layer; and a set of silicon carbide layers located on the set of group III nitride layers.Type: GrantFiled: May 14, 2020Date of Patent: August 1, 2023Assignee: The Boeing CompanyInventors: Samuel J. Whiteley, Daniel Yap, Edward H. Chen, Danny M. Kim, Thaddeus D. Ladd
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Patent number: 11715766Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.Type: GrantFiled: December 22, 2021Date of Patent: August 1, 2023Assignee: AZUR SPACE Solar Power GmbHInventors: Daniel Fuhrmann, Gregor Keller, Clemens Waechter
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Patent number: 11710704Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.Type: GrantFiled: May 30, 2019Date of Patent: July 25, 2023Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 11705489Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.Type: GrantFiled: December 19, 2018Date of Patent: July 18, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
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Patent number: 11695052Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.Type: GrantFiled: February 25, 2021Date of Patent: July 4, 2023Assignee: Finwave Semiconductor, Inc.Inventors: Bin Lu, Dongfei Pei, Mark Dipsey, Hal Emmer
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Patent number: 11670637Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.Type: GrantFiled: February 19, 2019Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Paul B. Fischer, Walid M. Hafez
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Patent number: 11659722Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.Type: GrantFiled: December 19, 2018Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Willy Rachmady, Prashant Majhi, Ravi Pillarisetty, Elijah Karpov, Brian Doyle, Anup Pancholi, Abhishek Sharma
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Patent number: 11653579Abstract: Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.Type: GrantFiled: February 3, 2021Date of Patent: May 16, 2023Inventors: Paolo Giuseppe Cappelletti, Gabriele Navarro
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Patent number: 11626401Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.Type: GrantFiled: August 12, 2020Date of Patent: April 11, 2023Inventors: Jaemun Kim, Gyeom Kim, Dahye Kim, Jinbum Kim, Kyungin Choi, Ilgyou Shin, Seunghun Lee
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Patent number: 11621371Abstract: An epitaxial structure, a preparation method thereof, and a light-emitting diode (LED) are provided. The epitaxial structure includes a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer stacked in sequence.Type: GrantFiled: September 30, 2019Date of Patent: April 4, 2023Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD.Inventor: Shungui Yang
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Patent number: 11610971Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.Type: GrantFiled: December 17, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Johann Rode, Paul Fischer, Walid Hafez
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Patent number: 11605633Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.Type: GrantFiled: January 4, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
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Patent number: 11594413Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.Type: GrantFiled: September 30, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 11581406Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: GrantFiled: November 1, 2021Date of Patent: February 14, 2023Assignee: Daedalus Prime LLCInventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
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Patent number: 11581435Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.Type: GrantFiled: June 8, 2020Date of Patent: February 14, 2023Inventors: Ju-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Patent number: 11575021Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.Type: GrantFiled: May 10, 2021Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
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Patent number: 11569350Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.Type: GrantFiled: July 9, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanggil Lee, Namkyu Cho, Seokhoon Kim, Kang Hun Moon, Hyun-Kwan Yu, Sihyung Lee
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Patent number: 11549177Abstract: Methods are disclosed herein for depositing a passivation layer comprising fluorine over a dielectric material that is sensitive to chlorine, bromine, and iodine. The passivation layer can protect the sensitive dielectric layer thereby enabling deposition using precursors comprising chlorine, bromine, and iodine over the passivation layer.Type: GrantFiled: December 10, 2019Date of Patent: January 10, 2023Assignee: ASM INTERNATIONAL, N.V.Inventors: Tom E. Blomberg, Eva E. Tois, Robert Huggare, Jan Willem Maes, Vladimir Machkaoutsan, Dieter Pierreux
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Patent number: 11552204Abstract: An apparatus for light detection includes a light, or photon, detector assembly and a dielectric resonator layer coupled to the detector assembly. The dielectric resonator layer is configured to receive transmission of incident light that is directed into the detector assembly by the dielectric resonator layer. The dielectric resonator layer resonates with a range of wavelengths of the incident light.Type: GrantFiled: February 3, 2020Date of Patent: January 10, 2023Assignees: Ohio State Innovation Foundation, THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Sanjay Krishna, Anthony Grbic, Christopher Ball, Theodore Ronningen, Alireza Kazemi, Mohammadamin Ranjbaraskari, Qingyuan Shu