With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 11437517
    Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11411103
    Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
  • Patent number: 11387362
    Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Georgios Vellianitis, Gerben Doornbos, Marcus Van Dal
  • Patent number: 11361963
    Abstract: A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 14, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11362177
    Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 14, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Frank W. Mont, Ali Razavieh, Julien Frougier
  • Patent number: 11349022
    Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
  • Patent number: 11342179
    Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 24, 2022
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Chieh-Hsi Chuang, Jessie Lin
  • Patent number: 11335808
    Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 17, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Patent number: 11335680
    Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 17, 2022
    Inventors: Jaeyeol Song, Seungha Oh, Rakhwan Kim, Minjung Park, Dongsoo Lee
  • Patent number: 11335793
    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung
  • Patent number: 11322399
    Abstract: Semiconductor structure and method for forming the semiconductor structure are provided. An exemplary method includes: providing a substrate, including a first region and a second region; forming a gate structure over the substrate; forming a first interlayer dielectric layer over the substrate; forming a plurality of metal plugs in the first interlayer dielectric layer; forming a second interlayer dielectric layer over the first interlayer dielectric layer; forming a first via in the first region exposing a metal plug, and a second via in the second region exposing the first interlayer dielectric layer by etching the second interlayer dielectric layer; fully filling the first via with a first tungsten layer; forming an adhesion layer over the first tungsten layer, the second interlayer dielectric layer, and a sidewall and bottom of the second via; and fully filling the second via with a second tungsten layer.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 3, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Li Jiang
  • Patent number: 11322578
    Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Jin Lim, Ki Nam Kim, Hyung Suk Jung, Kyoo Ho Jung, Ki Hyun Hwang
  • Patent number: 11316035
    Abstract: A method making a fin device structure includes: forming a plurality of fin structures arranged spaced out from each other in a longitudinal direction and covered with a thin oxide layer; forming a plurality of gate structures in a transverse direction; depositing sidewalls covering the thin oxide layer of the gate structures and the fin structures; removing the sidewalls on the gate structures and the sidewalls of the fin structures; removing the thin oxide layer on the sidewalls of the trenches to expand the volume of each trench; forming an epitaxial layer structure at the trenches; the method further includes removing the oxides on the sidewalls to increase the volume of the subsequently grown epitaxial layer, such that it is conducive to increasing the stress and reducing the source and drain resistance, thus improving the performance of the device.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 26, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventor: Yong Li
  • Patent number: 11296479
    Abstract: A power sourcing equipment (PSE) device of an optical power supply system includes a semiconductor laser that oscillates with electric power, thereby outputting feed light. The semiconductor laser includes a semiconductor region exhibiting a light-electricity conversion effect. A semiconductor material of the semiconductor region is a laser medium having a laser wavelength of 500 nm or less. A powered device of the optical power supply system includes a photoelectric conversion element that converts feed light into electric power. The photoelectric conversion element includes a semiconductor region exhibiting a light-electricity conversion effect. A semiconductor material of the semiconductor region is a laser medium having a laser wavelength of 500 nm or less.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: April 5, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Tomonori Sugime
  • Patent number: 11296227
    Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Chun Chang, Guan-Jie Shen
  • Patent number: 11271370
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 8, 2022
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11257915
    Abstract: A semiconductor element includes an enhancement-type transistor structure with a layer construction including a base substrate, a first semiconductor layer, and a second semiconductor layer, which are arranged one on top of the other along a first direction. The transistor structure further has a source electrode, a gate electrode, and a drain electrode, which are spaced apart from one another along a second direction that is transverse to the first direction. The first and second semiconductor layers are formed by different group III nitride materials, such that a 2D electron gas forms in a boundary region of the first and second semiconductor layers. The first and second semiconductor layers have holes in the region of the gate electrode, between which holes multiple fins including the group III nitride materials remain. The gate electrode has a plurality of gate fingers extending into the holes.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: February 22, 2022
    Assignee: Institut für Mikroelektronik Stuttgart
    Inventors: Joachim N. Burghartz, Mohammed Alomari, Muhammad Alshahed
  • Patent number: 11257934
    Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 11251195
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 15, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Patent number: 11245012
    Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 8, 2022
    Assignee: AZUR SPACE Solar Power GmbH
    Inventors: Daniel Fuhrmann, Gregor Keller, Clemens Waechter
  • Patent number: 11239802
    Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 1, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Qianli Mu, Zulhazmi Mokhti, Jia Guo, Scott Sheppard
  • Patent number: 11233143
    Abstract: A semiconductor device includes a III-nitride buffer layer and a III-nitride barrier layer. A boron nitride alloy interlayer interposed between the III-nitride buffer layer and the III-nitride barrier layer. A portion of the III-nitride buffer layer includes a two-dimensional electron gas (2DEG) channel that is on a side of the III-nitride buffer layer adjacent to the boron nitride alloy interlayer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: January 25, 2022
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Xiaohang Li
  • Patent number: 11227799
    Abstract: Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventor: Rishabh Mehandru
  • Patent number: 11227919
    Abstract: A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 18, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xi Lin, Yi Hua Shen, Jian Pan
  • Patent number: 11205716
    Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 21, 2021
    Assignee: IMEC VZW
    Inventors: Veeresh Vidyadhar Deshpande, Bertrand Parvais
  • Patent number: 11201278
    Abstract: According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 14, 2021
    Assignee: Ambature, Inc.
    Inventors: Michael S. Lebby, Davis H. Hartmann
  • Patent number: 11195944
    Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Sanaz K. Gardner, Marko Radosavljevic, Seung Hoon Sung, Robert S. Chau
  • Patent number: 11164781
    Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Xinghua Sun, Yen-Tien Lu, Angelique Raley, David O'Meara, Jeffrey Smith
  • Patent number: 11152313
    Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Rimvydas Mickevicius
  • Patent number: 11152210
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 11145572
    Abstract: A semiconductor structure includes a semiconductor substrate, a porous semiconductor region within the semiconductor substrate, and through-substrate via (TSV) within the porous semiconductor region. The porous semiconductor region causes the semiconductor structure and/or the TSV to withstand thermal and mechanical stresses. Alternatively, the semiconductor structure includes a semiconductor buffer ring within the porous semiconductor region, and the TSV within the semiconductor buffer ring.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Newport Fab, LLC
    Inventor: David J. Howard
  • Patent number: 11145750
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
  • Patent number: 11127837
    Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 11127642
    Abstract: A test circuit layout structure for a display panel is disclosed and includes a chip on film (COF) bonding region having two ends connected to two power conductor regions extending toward an active area; a test circuit region located between the COF bonding region and the two power conductor regions; two test pad regions and two electrostatic protection regions are both distributed around two sides of the COF bonding region; wherein a plurality of wires extend from the test pad regions and are configured to couple the electrostatic protection regions, the COF bonding region, and the test circuit region; wherein resistivity of the wires and resistivity of the power conductor regions are the same; and wherein the wires bypass the power conductor regions disposed in the same layer as the wires, alternatively, the wires and the power conductor regions are overlapped in an insulation manner.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 21, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xue Li
  • Patent number: 11121285
    Abstract: A semiconductor device includes a conductive layer, a semiconductor stack, a first contact structure, an intermediate structure, a second contact structure, a first electrode and a second electrode. The semiconductor stack is disposed on the conductive layer. The first contact structure is disposed on the semiconductor stack. The intermediate structure encloses the first contact structure. The second contact structure is between the conductive layer and the semiconductor stack. The first electrode is on the conductive layer and separated from the semiconductor stack. The second electrode is on the intermediate structure.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Epistar Corporation
    Inventors: Yung-Fu Chang, Hui-Fang Kao, Yi-Tang Lai, Shih-Chang Lee, Wen-Luh Liao, Mei Chun Liu, Yao-Ru Chang, Yi Hisao
  • Patent number: 11101268
    Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Ritesh Jhaveri, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy, Tahir Ghani
  • Patent number: 11094812
    Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 17, 2021
    Assignee: Soitec Belgium
    Inventor: Joff Derluyn
  • Patent number: 11081570
    Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 11043494
    Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie, Deepika Priyadarshini, Indira Priyavarshini Seshadri, Nicole A. Saulnier
  • Patent number: 11031298
    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11031393
    Abstract: A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Jeehwan Kim
  • Patent number: 11031290
    Abstract: A semiconductor structure with cutting depth control and method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, fins protruding from a substrate are formed. Next, source/drain devices are grown on both ends of the fins. Then, an inter-layer dielectric layer crossing the fins and enclosing the source/drain devices is deposited. A metal gate structure enclosed by the inter-layer dielectric layer is formed between the source/drain devices. And then, a replacement operation is performed to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion that adjoins the metal gate structure and is located between the adjacent source/drain devices. Thereafter, a metal gate cut operation is performed, thereby forming an opening in the metal gate structure and an opening in the isolation portion, and an insulating material is deposited in the openings.
    Type: Grant
    Filed: January 21, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Shu-Yuan Ku, I-Wei Yang, Yi-Hsuan Hsiao, Ming-Ching Chang, Ryan Chia-Jen Chen
  • Patent number: 11024740
    Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11015263
    Abstract: Bulk single crystal of aluminum nitride (AlN) having an areal planar defect density?100 cm?2. Methods for growing single crystal aluminum nitride include melting an aluminum foil to uniformly wet a foundation with a layer of aluminum, the foundation forming a portion of an AlN seed holder, for an AlN seed to be used for the AlN growth. The holder may consist essentially of a substantially impervious backing plate.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: CRYSTAL IS, INC.
    Inventors: Robert T. Bondokov, Leo J. Schowalter, Kenneth Morgan, Glen A. Slack, Shailaja P. Rao, Shawn Robert Gibb
  • Patent number: 11001938
    Abstract: Provided are a diamond composite body capable of shortening a separation time for separating a substrate and a diamond layer, the substrate, and a method for manufacturing a diamond, as well as a diamond obtained from the diamond composite body and a tool including the diamond. The diamond composite body includes a substrate including a diamond seed crystal and having grooves in a main surface, a diamond layer formed on the main surface of the substrate, and a non-diamond layer formed on a substrate side at a constant depth from an interface between the substrate and the diamond layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: May 11, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Nishibayashi, Natsuo Tatsumi, Hitoshi Sumiya
  • Patent number: 11004688
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Patent number: 11004951
    Abstract: A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • Patent number: 10998435
    Abstract: An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 4, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10978582
    Abstract: Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10978486
    Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 13, 2021
    Inventors: Ho-Jun Kim, Jaehyeoung Ma, Geumjong Bae