With Lattice Constant Mismatch (e.g., With Buffer Layer To Accommodate Mismatch) Patents (Class 257/190)
  • Patent number: 9437688
    Abstract: A GaN HFET includes a silicon substrate with an Al2O3 layer above the silicon substrate. The Al2O3 layer has voids formed therein. A plurality of alternating GaN and AlN layers are above the Al2O3 layer. The GaN and AlN layers are under continuous compressive stress.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 6, 2016
    Assignee: Power Integrations, Inc.
    Inventors: Jamal Ramdani, John P. Edwards, Linlin Liu
  • Patent number: 9437738
    Abstract: In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien-Ming Lin
  • Patent number: 9437495
    Abstract: A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ming Lee, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 9431243
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Patent number: 9425355
    Abstract: A semiconductor light emitting device including a first conductive semiconductor base layer on a substrate; an insulating layer on the first conductive semiconductor base layer, the insulating layer including a plurality of openings through which the first conductive semiconductor base layer is exposed; and a plurality of nanoscale light emitting structures on the first conductive semiconductor base layer, the nanoscale light emitting structures respectively including a first conductive semiconductor core on an exposed region of the first conductive semiconductor base layer, and an active layer, and a second conductive semiconductor layer sequentially disposed on a surface of the first conductive semiconductor core, wherein a lower edge of a side portion of each nanoscale light emitting structure is on an inner side wall of the opening in the insulating layer.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Ho Yoo, Han Kyu Seong, Nam Goo Cha, Tae Woong Kim
  • Patent number: 9425260
    Abstract: A lateral bipolar junction transistor including a base region on a dielectric substrate layer. The base region includes a layered stack of alternating material layers of a first lattice dimension semiconductor material and a second lattice dimension semiconductor material. The first lattice dimension semiconductor material is different from the second lattice dimension semiconductor material to provide a strained base region. A collector region is present on the dielectric substrate layer in contact with a first side of the base region. An emitter region is present on the dielectric substrate in contact with a second side of the base region that is opposite the first side of the base region.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 9419078
    Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material. The fin has a first side surface opposite a second side surface. The semiconductor structure has a portion of a second semiconductor material that has a third side surface opposite a fourth side surface. The fourth side surface of the second semiconductor material abuts and covers the first side surface of the fin. The semiconductor structure has a portion of a third semiconductor material that abuts and covers the second side surface of the fin. The semiconductor structure has a single gate structure that covers the fin, the portion of the second semiconductor material and the portion of the third semiconductor material. The fin manifests an asymmetry due to the portion of the second semiconductor material and the portion of the third semiconductor material.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9406778
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 9397149
    Abstract: A display device that includes a first flexible substrate, a first bonding layer over the first flexible substrate, a first insulating film over the first bonding layer, a first element layer over the first insulating film, a second element layer over the first element layer, a second insulating film over the second element layer, a second bonding layer over the second insulating film, and a second flexible substrate over the second bonding layer is provided. The first element layer includes a pixel portion and a circuit portion. The pixel portion includes a display element and a first transistor, and the circuit portion includes a second transistor. The second element layer includes a coloring layer and a light-blocking layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunihiko Suzuki, Masakatsu Ohno, Hiroki Adachi, Satoru Idojiri, Koichi Takeshima
  • Patent number: 9391144
    Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9385199
    Abstract: A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 5, 2016
    Assignee: NATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Jamal Ramdani
  • Patent number: 9379240
    Abstract: A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 28, 2016
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Wayne Bao
  • Patent number: 9379285
    Abstract: Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 28, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Tae Yun Kim
  • Patent number: 9373703
    Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 21, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JinBum Kim, Jungho Yoo, Byeongchan Lee, Choeun Lee, Hyun Jung Lee, Seong Hoon Jeong, Bonyoung Koo
  • Patent number: 9368359
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 14, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihide Kikkawa
  • Patent number: 9362405
    Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Witold P. Maszara, Jody A. Fronheiser
  • Patent number: 9362123
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si1-xGex and x is less than about 30%.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, I-Ming Chang, Yasutoshi Okuno, Chih-Hao Chang, Shou Zen Chang, Clement Hsingjen Wann
  • Patent number: 9362360
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 9356117
    Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1?xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Patent number: 9355920
    Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Matthias Passlack, Richard Kenneth Oxland
  • Patent number: 9356091
    Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: May 31, 2016
    Assignee: The Royal Institute for the Advancement of Learning/McGill University
    Inventor: Zetian Mi
  • Patent number: 9349861
    Abstract: A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of relaxed silicon germanium (SiGe); epitaxially growing a silicon device layer on the surface of the donor wafer, wherein the silicon device layer comprises tensile strained silicon on the regions of relaxed silicon germanium of the donor wafer, and wherein the silicon device layer comprises relaxed silicon on the regions of relaxed silicon of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining regions of tensile strained silicon and regions of relaxed silicon.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 24, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Devendra K. Sadana
  • Patent number: 9349837
    Abstract: A method includes forming a semiconductor fin over top surfaces of insulation regions, and forming a gate stack on a top surface and sidewalls of a middle portion of the semiconductor fin. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor fin is etched to form a recess located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. A dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions. The dielectric mask layer further extends on a sidewall of the gate stack.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 9337390
    Abstract: A method for manufacturing a sapphire substrate in which a plurality of projections are formed on a C-plane of the sapphire substrate by etching, includes: forming a patterned etching mask on the C-plane of the sapphire substrate; etching the sapphire substrate until the projections are formed, wherein each of the projections formed by the etching has a substantially triangular pyramidal-shape and has a plurality of side surfaces, a pointed top and a bottom, wherein the bottom of each of the projections has a substantially triangular shape having three outwardly curved arc-shaped sides. The projections are arranged on vertexes of a triangular lattice, and an orientation of the bottom of the projections conforms with an orientation that is rotated by about 30 degrees from an orientation of a triangle of the triangular lattice; and removing the etching mask from the sapphire substrate.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 10, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Naoya Sako, Takashi Ohara, Yoshiki Inoue, Yuki Shibutani, Yoshihito Kawauchi, Kazuyuki Takeichi, Yasunori Nagahama
  • Patent number: 9337265
    Abstract: A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stefan Abel, Lukas Czornomaz, Jean Fompeyrine, Mario El Kazzi
  • Patent number: 9337377
    Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 10, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Patent number: 9324865
    Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Tsan-Chun Wang, De-Wei Yu
  • Patent number: 9318489
    Abstract: A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Kern Rim
  • Patent number: 9306068
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 9306016
    Abstract: The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: April 5, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES
    Inventors: Huicai Zhong, Chao Zhao, Qingqing Liang
  • Patent number: 9299824
    Abstract: A FET disclosed herein comprises a substrate, a first semiconductor layer disposed over the substrate, a second semiconductor layer disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas. The E-mode FET further comprises a p+ III-V semiconductor layer disposed over the second semiconductor layer and a depolarization layer disposed between the second semiconductor layer and the p+ III-V semiconductor layer.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 29, 2016
    Assignees: EPISTAR CORPORATION, HUGA OPTOTECH INC.
    Inventors: Heng-Kuang Lin, Chien-Kai Tung
  • Patent number: 9293550
    Abstract: The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 22, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Mieno Fumitake
  • Patent number: 9293593
    Abstract: A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Judson R. Holt, Viorel C. Ontalus, Keith H. Tabakman
  • Patent number: 9293523
    Abstract: Embodiments of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one embodiment, a first trench is formed in a dielectric layer formed on a substrate to expose a surface of the substrate, a multi-stack layer structure is formed within the first trench, and a third semiconductor compound layer is formed on the second semiconductor compound layer, wherein the second semiconductor compound layer has an etching resistance against an etchant lower than that of the first and third semiconductor compound layers, a second trench is formed in the dielectric layer to partially expose at least the second semiconductor compound layer and the third semiconductor compound layer, and the second semiconductor compound layer is selectively removed so that the first semiconductor compound layer is isolated from the third semiconductor compound layer by an air gap.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez
  • Patent number: 9293534
    Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee, Da-Wen Lin
  • Patent number: 9287369
    Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9263248
    Abstract: A pseudo-substrate (1, 11) for use in the production of semiconductor components, having a carrier substrate (2, 12) with a crystalline structure and a first buffer (3, 13), which is arranged on a surface of the carrier substrate (2, 12), if appropriate on further intervening intermediate layers, wherein the first buffer (3, 13) is embodied as a single layer or as a multilayer system and includes, at least at the surface facing away from the carrier substrate (2, 12), arsenic (As) and at least one of the elements aluminum (Al) and indium (In).
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: February 16, 2016
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Arnulf Leuther, Axel Tessmann, Rainer Losch
  • Patent number: 9263454
    Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Pooja R. Batra, Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Reinaldo A. Vega
  • Patent number: 9257557
    Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: February 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: David P. Brunco
  • Patent number: 9245887
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Patent number: 9245805
    Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • Patent number: 9236463
    Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9231058
    Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more signal crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a minor polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 5, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Masaki Ueno
  • Patent number: 9224827
    Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 9224656
    Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: December 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deborah Jean Riley, Seung-Chul Song
  • Patent number: 9219152
    Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Jeffrey Junhao Xu, Chih-Hao Chang, Wen-Hsing Hsieh
  • Patent number: 9202916
    Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
  • Patent number: 9202689
    Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: December 1, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9184202
    Abstract: This invention relates to multiband detector and multiband image sensing devices, and their manufacturing technologies. The innovative detector (or image sensing) provides significant broadband capability covering the wavelengths from within ultra-violet (UV) to long-Infrared, and it is achieved in a single element. More particularly, this invention is related to the multiband or dual band detectors, which can not only detect the broad spectrum wavelengths ranges from within as low as UV to the wavelengths as high as 25 ?m, but also band selection capability. This invention is also related to the multiband detector arrays or image sensing device for multicolor imaging, sensing, and advanced communication.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Assignee: BANPIL PHOTONICS, INC.
    Inventor: Achyut Dutta
  • Patent number: 9184244
    Abstract: A high voltage gallium nitride based semiconductor device includes an n-type gallium nitride freestanding substrate, and an n-type gallium nitride based semiconductor layer including a drift layer formed on the surface of the n-type gallium nitride freestanding substrate so as to have a reverse breakdown voltage of not less than 3000 V. The drift layer is configured such that a carbon concentration is not less than 3.0×1016/cm3 in a region which has an electric field intensity of not more than 1.5 MV/cm when a maximum allowable voltage where there occurs no breakdown phenomenon is applied as a reverse bias voltage.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: November 10, 2015
    Assignee: Sciocs Company Limited
    Inventor: Naoki Kaneda