Heterojunction Device Patents (Class 257/183)
  • Patent number: 11495631
    Abstract: A system includes a pixel including a diffusion layer in contact with an absorption layer. The diffusion layer and absorption layer are in contact with one another along an interface that is inside of a mesa. A trench is defined in the absorption layer surrounding the mesa. An overflow contact is seated in the trench.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 8, 2022
    Assignee: Sensors Unlimited, Inc.
    Inventors: Wei Huang, Douglas Stewart Malchow, Michael J. Evans, John Liobe, Wei Zhang
  • Patent number: 11444606
    Abstract: Provided is a spike pulse generation circuit comprising a single silicon device configured to non-periodically or periodically generate a spike pulse. More particularly, the spike pulse generation circuit comprising the single silicon device can utilize a positive feedback loop and a negative feedback loop to be mutually connected so as to selectively output a spike pulse related to a neural oscillation function similar to biological oscillation, thereby being capable of serving as a ring oscillator and performing a neuron function operation.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: September 13, 2022
    Assignee: Korea University Research and Business Foundation
    Inventors: Sang Sig Kim, Kyoung Ah Cho, Doo Hyeok Lim
  • Patent number: 11444429
    Abstract: A photonics device includes a silicon wafer including an upper surface region, a trench region, and a ridge structure. The ridge structure electrically isolates the upper surface region from the trench region. A laser diode chip flip-bonded onto the silicon wafer includes an electrode region bonded with the upper surface region, a gain region bonded with the trench region, and an isolation region bonded with the ridge structure. The isolation region electrically isolates the gain region from the electrode region. A conductor layer arranged between the silicon wafer and the laser diode chip includes a first section electrically connecting the gain region to a first electrode of the photonics device and a second section configured to electrically connect the electrode region to a second electrode of the photonics device. The first section is electrically isolated from the second section by the isolation region.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: September 13, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Xiaoguang He, Radhakrishnan L. Nagarajan
  • Patent number: 11342220
    Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 24, 2022
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Noboru Fukuhara
  • Patent number: 11335802
    Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 17, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaejoon Oh, Jongseob Kim
  • Patent number: 11309886
    Abstract: A current blocking element is provided. The current blocking element includes a first electrode layer, an ion conductive layer, and a second electrode layer, which are laminated in this order, wherein the first electrode layer is configured to hold ions; the ion conductive layer has ionic conductivity and does not have electronic conductivity; and the second electrode layer is configured to hold ions. Ions held in the first electrode layer are moved to the second electrode layer when current is configured to flow between the first electrode layer and the second electrode layer. Current flow between the first electrode layer and the second electrode layer is blocked when ions held in one of the first and second electrode layers are depleted saturated.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 19, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Jusuke Shimura, Kenji Kishimoto, Masahiro Morooka, Keisuke Shimizu
  • Patent number: 11233144
    Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate lever 15, and satisfying the following formula (1): d G ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? B > 0 ( 1 )
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 25, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 11226505
    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 18, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Adams, Prakash B. Gothoskar, Vipulkumar Patel, Mark Webster
  • Patent number: 11227856
    Abstract: A multi-chip package power module according to the present disclosure, comprising: multiple chips, including a first chip and a second chip that are arranged adjacently; a first conductive member, at least partially arranged between the first chip and the second chip, and a second conductive member, at least partially arranged between the first chip and the second chip, where the first conductive member is electrically connected to a power pin of the first chip, the second conductive member is electrically connected to a power pin of the second chip, and the multiple chips, the first conductive member and the second conductive member are all embedded in an insulating package material. For the multi-chip package power module according to the present disclosure, the power output current of the chip can be directly led out from two opposite sides through the conductive member to obtain a symmetrical path.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: January 18, 2022
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Pengkai Ji, Xiaoni Xin, Yan Chen, Qingdong Chen, Shouyu Hong, Jianhong Zeng, Zhenqing Zhao
  • Patent number: 11213800
    Abstract: Multilayer structures comprising a covalent organic framework (COF) film in contact with a polyaromatic carbon (PAC) film. The multilayer structures can be made by combining precursor compounds in the presence of a PAC film. The PAC film can be for example, a single layer graphene film. The multilayer structures can be used in a variety of applications such as solar cells, flexible displays, lighting devices, RFID tags, sensors, photoreceptors, batteries, capacitors, gas-storage devices, and gas-separation devices.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: January 4, 2022
    Assignee: CORNELL UNIVERSITY
    Inventors: William R. Dichtel, Jiwoong Park, Arnab Mukherjee, Mark Philip Levendorf, Arthur Woll, Eric Spitler, John Colson
  • Patent number: 11211366
    Abstract: The present disclosure relates to an assembly substrate used for a display device manufacturing method in which semiconductor light-emitting diodes are placed on the assembly substrate at preset positions using electric field and magnetic field. Specifically, the assembly substrate includes a base portion, a plurality of assembly electrodes extending in one direction and disposed on the base portion, a dielectric layer stacked on the base portion to cover the assembly electrodes, a barrier wall formed on the base portion and having a plurality of recesses for guiding the semiconductor light-emitting diodes to the preset positions, and a metal shielding layer formed on the base portion, wherein the metal shielding layer overlaps the barrier wall so that an electric field formed between the assembly electrodes is shielded.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 28, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Changseo Park, Jinhyung Lee, Jungsub Kim, Seongmin Moon, Younho Heo
  • Patent number: 11201218
    Abstract: A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: December 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeshi Tawara
  • Patent number: 11189696
    Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 30, 2021
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Yuangang Wang, Yuanjie Lv, Zhihong Feng, Cui Yu, Chuangjie Zhou, Zezhao He, Xubo Song, Shixiong Liang
  • Patent number: 11127856
    Abstract: A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 21, 2021
    Assignee: NXP USA, INC.
    Inventors: Xin Lin, Zhihong Zhang, Xu Cheng, Ronghua Zhu
  • Patent number: 11081509
    Abstract: A detector device for detection of electromagnetic radiation impinging on a substrate and generating pairs of majority and minority charge carriers in the substrate, comprises at least one minority charge detection structure for, in a first mode, injecting a majority current so as to create an electric field for directing minority charge carriers towards the at least one minority charge detection structure for detecting minority charge carriers generated in the substrate; two or more minority charge removal structures per minority charge detection structure for, in a second mode, injecting a majority current so as to create an electric field, for draining minority charge carriers towards the two or more minority charge removal structures, away from the associated charge detection structure; and at least one substrate majority charge current sink for extracting the injected majority current.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 3, 2021
    Assignee: VRIJE UNIVERSITEIT BRUSSEL
    Inventor: Hans Ingelberts
  • Patent number: 11018254
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10951003
    Abstract: A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 16, 2021
    Assignee: INPHI CORPORATION
    Inventors: Xiaoguang He, Radhakrishnan L. Nagarajan
  • Patent number: 10840347
    Abstract: Provided is a semiconductor device with negative differential transconductance. The semiconductor device includes a substrate, a gate electrode formed on the substrate, an insulating layer formed on the gate electrode, a source electrode material layer formed on the insulating layer, a semiconductor material layer formed on the insulating layer to be hetero-joined to the source electrode material layer, a source electrode formed on the source electrode material layer, and a drain electrode formed on the semiconductor material layer. A work function of the source electrode material layer is controlled by a gate voltage applied through the gate electrode, and the source electrode material layer shows negative differential transconductance depending on a level of the gate voltage.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jaewoo Shim, Dong Ho Kang
  • Patent number: 10784353
    Abstract: A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 22, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Lain-Jong Li, Hao-Ling Tang, Ming-Hui Chiu
  • Patent number: 10770556
    Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 8, 2020
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCE
    Inventors: Xinhong Cheng, Lingyan Shen, Zhongjian Wang, Duo Cao, Li Zheng, Qian Wang, Dongliang Zhang, Jingjie Li, Yuehui Yu
  • Patent number: 10734508
    Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 4, 2020
    Assignee: ADVANTEST CORPORATION
    Inventors: Jun'ichi Okayasu, Taku Sato
  • Patent number: 10665465
    Abstract: Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 26, 2020
    Assignees: KWANSEI GAKUIN EDUCATIONAL FOUNDATION, TOYO TANSO CO., LTD.
    Inventors: Tadaaki Kaneko, Koji Ashida, Yasunori Kutsuma, Satoshi Torimi, Masato Shinohara, Youji Teramoto, Norihito Yabuki, Satoru Nogami
  • Patent number: 10651317
    Abstract: High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 12, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Anthony Kaleta, Douglas Carlson, Timothy E. Boles
  • Patent number: 10600935
    Abstract: A nitride based semiconductor device including a buffer layer, a three-dimensional stress tuning layer formed on the buffer layer, a first-type semiconductor layer formed on the three-dimensional stress tuning layer, an active layer formed on the first-type semiconductor layer, and a second-type semiconductor layer formed on the active layer. The three-dimensional stress tuning layer and the buffer layer cooperatively define an interface therebetween. The interface has a three-dimensional composition distribution.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 24, 2020
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Chang-Cheng Chuo, Shengchang Chen, Heqing Deng
  • Patent number: 10600889
    Abstract: A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10566389
    Abstract: Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 18, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jaewoo Shim, Hae Won Lee
  • Patent number: 10540916
    Abstract: A semiconductor light-emitting device according to an embodiment of the present disclosure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer and including a plurality of well layers. In the plurality of well layers included in the active layer, a band gap inclination angle ?1 of a second well layer located relatively close to the p-type semiconductor layer is smaller than a band gap inclination angle ?2 of a first well layer located relatively close to the n-type semiconductor layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 21, 2020
    Assignee: SONY CORPORATION
    Inventors: Kota Tokuda, Takayuki Kawasumi
  • Patent number: 10534152
    Abstract: The approach presented here provides a membrane unit (105) comprising micro-optical structures (115), which comprises a wafer (110) as carrier basis of the micro-optical structures (115), an intermediate substrate (300) connected to the wafer (110), and a carrier (130) connected to the intermediate substrate (300), wherein the coefficients of thermal expansion of the wafer (100), of the intermediate substrate (300) and of the carrier (130) are dimensioned such that a coefficient of expansion of the carrier (130) is greater than a coefficient of expansion of the intermediate substrate (300) and the coefficient of expansion of the intermediate substrate (300) is greater than or equal to a coefficient of expansion of the wafer (110).
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 14, 2020
    Assignee: JENOPTIK Optical Systems GmbH
    Inventor: Christian Ziener
  • Patent number: 10510868
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 10461074
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Wolfgang Werner
  • Patent number: 10418472
    Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Jia Guo, Ali Salih, Chun-Li Liu
  • Patent number: 10418483
    Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 17, 2019
    Assignee: NXP B.V.
    Inventors: Bernhard Grote, Xin Lin, Saumitra Raj Mehrotra, Ljubo Radic, Ronghua Zhu
  • Patent number: 10381470
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 13, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Patent number: 10355105
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 10347748
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Muhammad Rahman, Srikanth Balaji Samavedam
  • Patent number: 10325800
    Abstract: Techniques are disclosed for methods and apparatuses for increasing the breakdown voltage while substantially reducing the voltage leakage of an electrostatic chuck at temperatures exceeding about 300 degrees Celsius in a processing chamber.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 18, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kulshreshtha, Kwangduk Douglas Lee, Bok Hoen Kim, Zheng John Ye, Swayambhu Prasad Behera, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Jian J. Chen
  • Patent number: 10312358
    Abstract: III-nitride based high electron mobility transistors (HEMTs), such as AlGaN/GaN HEMTs on Silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 4, 2019
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Fan Ren, Stephen John Pearton, Mark E. Law, Ya-Hsi Hwang
  • Patent number: 10283633
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 7, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10256352
    Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 9, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Min Sun, Tomas Apostol Palacios
  • Patent number: 10249757
    Abstract: A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong Cheol Kim, Hyung Suk Lee, Eun Shoo Han
  • Patent number: 10230146
    Abstract: Disclosed are synthetic garnets and related devices that can be used in radio-frequency (RF) applications. In some embodiments, such RF devices can include garnets having reduced or substantially nil Yttrium or other rare earth metals. Such garnets can be configured to yield high dielectric constants, and ferrite devices, such as TM-mode circulators/isolators, formed from such garnets can benefit from reduced dimensions. Further, reduced or nil rare earth content of such garnets can allow cost-effective fabrication of ferrite-based RF devices. In some embodiments, such ferrite devices can include other desirable properties such as low magnetic resonance linewidths. Examples of fabrication methods and RF-related properties are also disclosed.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Bowie Cruickshank, Rickard Paul O'Donovan, Iain Alexander MacFarlane, Brian Murray, Michael David Hill
  • Patent number: 10204682
    Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
  • Patent number: 10193504
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 29, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10186591
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 22, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10177284
    Abstract: A sidewall light emitting ultraviolet light emitting diode and a method of manufacturing thereof are disclosed. A light emitting structure is formed in an active region recessed from a substrate surface, and the light emitting structure is formed by growth in a direction parallel to the surface of the substrate. Also, a reflective metal layer is formed above or below the light emitting structure such that ultraviolet light can be released in a second direction perpendicular to a first direction which is the growth direction of the light emitting structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 8, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Dong-Seon Lee, Duk-Jo Kong, Jun-Yeob Lee, Mun-Do Park
  • Patent number: 10177046
    Abstract: A technique relates to forming a semiconductor device. A first substrate is provided adjacent to a second substrate. The first substrate has a first surface orientation, and the second substrate has a second surface orientation different from the first surface orientation. An n-type field effect transistor (NFET) device is formed with the first substrate. The NFET device includes a first source, a first drain, and one or more first fins. The first source and the first drain have a vertical relationship with respect to the one or more first fins. A p-type field effect transistor (PFET) device is formed with the second substrate. The PFET device includes a second source, a second drain, and one or more second fins. The second source and the second drain have a vertical relationship with respect to the one or more second fins.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10163912
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Patent number: 10162200
    Abstract: An electro-optic (EO) phase modulator is disclosed. The EO phase modulator includes: an insulating layer; a central optical waveguide over the insulating layer; a first region having a first type doping adjacent to a first sidewall of the central optical waveguide; a second region having a second type doping opposite to the first type doping adjacent to a second sidewall of the central optical waveguide opposite to the first sidewall; and a first dielectric layer passing through the central optical waveguide from a top surface of the central optical waveguide to a bottom surface of the central optical waveguide. A method of manufacturing the same is disclosed as well.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Feng Wei Kuo
  • Patent number: 10141371
    Abstract: Disclosed herein are wide band gap integrated circuits, such as gallium nitride (GaN) integrated circuits, including a plurality of groups of epitaxial layers formed on an engineered substrate, and methods of making the WBG integrated circuits. The epitaxial layers have a coefficient of thermal expansion (CTE) substantially matching the CTE of the engineered substrate. Mesas, internal interconnects, and electrodes configure each group of epitaxial layers into a WBG device. External interconnects connect different WBG devices into a WBG integrated circuit. The CTE matching allows the formation of epitaxial layers with reduced dislocation density and an overall thickness of greater than 10 microns on a six-inch or larger engineered substrate. The large substrate size and thick WBG epitaxial layers allow a large number of high density WBG integrated circuits to be fabricated on a single substrate.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: November 27, 2018
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri