Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Abstract: Structures including an ohmic contact for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack on a substrate and a device structure including an ohmic contact. The layer stack includes a plurality of semiconductor layers each comprising a compound semiconductor material. The ohmic contact includes a metal layer in a contacting relationship with a portion of at least one of the semiconductor layers of the layer stack and a region comprising oxygen atoms, and the metal layer is positioned between the region and the portion of the at least one of the semiconductor layers of the layer stack.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first field plate, and a second field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate structure is disposed above the second nitride-based semiconductor layer. The first field plate is disposed over the gate structure and is electrically coupled with the source electrode and the drain electrode. The second field plate is disposed over the gate structure and is electrically coupled with the gate structure. The first field plate and the second field plate are parallel with each other. A top surface of the first field plate faces a bottom surface of the second field plate to overlap with each other.

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

Abstract: A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

Abstract: The present invention discloses a bidirectional ultraviolet light emitting diode (UV LED) based on N—ZnO/N—GaN/N—ZnO heterojunction as well as its preparation method. The LED includes: N—ZnO microwires, a N—GaN film, a PMMA protective layer and alloy electrodes; and its preparation method includes the following steps: lay two N—ZnO microwires on the N—GaN film, then spin-coat a PMMA protective layer on the film to fix the N—ZnO microwires until the PMMA protective layer spreads over the N—ZnO microwires, and then place the film on a drying table to solidify the PMMA protective layer; then etch the PMMA protective layer with O2 to expose the N—ZnO microwires, and prepare alloy electrodes on different N—ZnO microwires to construct a N—ZnO/N—GaN/N—ZnO heterojunction to constitute a complete device. The present invention constructs an N/N/N symmetrical structure; the device is composed of N—ZnO and N—GaN, emits light in the ultraviolet region and has a small turn-on voltage.

Abstract: A system includes a pixel including a diffusion layer in contact with an absorption layer. The diffusion layer and absorption layer are in contact with one another along an interface that is inside of a mesa. A trench is defined in the absorption layer surrounding the mesa. An overflow contact is seated in the trench.

Abstract: Provided is a spike pulse generation circuit comprising a single silicon device configured to non-periodically or periodically generate a spike pulse. More particularly, the spike pulse generation circuit comprising the single silicon device can utilize a positive feedback loop and a negative feedback loop to be mutually connected so as to selectively output a spike pulse related to a neural oscillation function similar to biological oscillation, thereby being capable of serving as a ring oscillator and performing a neuron function operation.

Abstract: A photonics device includes a silicon wafer including an upper surface region, a trench region, and a ridge structure. The ridge structure electrically isolates the upper surface region from the trench region. A laser diode chip flip-bonded onto the silicon wafer includes an electrode region bonded with the upper surface region, a gain region bonded with the trench region, and an isolation region bonded with the ridge structure. The isolation region electrically isolates the gain region from the electrode region. A conductor layer arranged between the silicon wafer and the laser diode chip includes a first section electrically connecting the gain region to a first electrode of the photonics device and a second section configured to electrically connect the electrode region to a second electrode of the photonics device. The first section is electrically isolated from the second section by the isolation region.

Abstract: There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition.

Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer.

Abstract: A current blocking element is provided. The current blocking element includes a first electrode layer, an ion conductive layer, and a second electrode layer, which are laminated in this order, wherein the first electrode layer is configured to hold ions; the ion conductive layer has ionic conductivity and does not have electronic conductivity; and the second electrode layer is configured to hold ions. Ions held in the first electrode layer are moved to the second electrode layer when current is configured to flow between the first electrode layer and the second electrode layer. Current flow between the first electrode layer and the second electrode layer is blocked when ions held in one of the first and second electrode layers are depleted saturated.

Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate lever 15, and satisfying the following formula (1): d G ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? B > 0 ( 1 )

Abstract: A multi-chip package power module according to the present disclosure, comprising: multiple chips, including a first chip and a second chip that are arranged adjacently; a first conductive member, at least partially arranged between the first chip and the second chip, and a second conductive member, at least partially arranged between the first chip and the second chip, where the first conductive member is electrically connected to a power pin of the first chip, the second conductive member is electrically connected to a power pin of the second chip, and the multiple chips, the first conductive member and the second conductive member are all embedded in an insulating package material. For the multi-chip package power module according to the present disclosure, the power output current of the chip can be directly led out from two opposite sides through the conductive member to obtain a symmetrical path.

Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.

Abstract: Multilayer structures comprising a covalent organic framework (COF) film in contact with a polyaromatic carbon (PAC) film. The multilayer structures can be made by combining precursor compounds in the presence of a PAC film. The PAC film can be for example, a single layer graphene film. The multilayer structures can be used in a variety of applications such as solar cells, flexible displays, lighting devices, RFID tags, sensors, photoreceptors, batteries, capacitors, gas-storage devices, and gas-separation devices.

Abstract: The present disclosure relates to an assembly substrate used for a display device manufacturing method in which semiconductor light-emitting diodes are placed on the assembly substrate at preset positions using electric field and magnetic field. Specifically, the assembly substrate includes a base portion, a plurality of assembly electrodes extending in one direction and disposed on the base portion, a dielectric layer stacked on the base portion to cover the assembly electrodes, a barrier wall formed on the base portion and having a plurality of recesses for guiding the semiconductor light-emitting diodes to the preset positions, and a metal shielding layer formed on the base portion, wherein the metal shielding layer overlaps the barrier wall so that an electric field formed between the assembly electrodes is shielded.

Abstract: A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Abstract: A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

Abstract: A detector device for detection of electromagnetic radiation impinging on a substrate and generating pairs of majority and minority charge carriers in the substrate, comprises at least one minority charge detection structure for, in a first mode, injecting a majority current so as to create an electric field for directing minority charge carriers towards the at least one minority charge detection structure for detecting minority charge carriers generated in the substrate; two or more minority charge removal structures per minority charge detection structure for, in a second mode, injecting a majority current so as to create an electric field, for draining minority charge carriers towards the two or more minority charge removal structures, away from the associated charge detection structure; and at least one substrate majority charge current sink for extracting the injected majority current.

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.

Abstract: Provided is a semiconductor device with negative differential transconductance. The semiconductor device includes a substrate, a gate electrode formed on the substrate, an insulating layer formed on the gate electrode, a source electrode material layer formed on the insulating layer, a semiconductor material layer formed on the insulating layer to be hetero-joined to the source electrode material layer, a source electrode formed on the source electrode material layer, and a drain electrode formed on the semiconductor material layer. A work function of the source electrode material layer is controlled by a gate voltage applied through the gate electrode, and the source electrode material layer shows negative differential transconductance depending on a level of the gate voltage.

Abstract: A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.

Abstract: Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.

Abstract: High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.

Abstract: A nitride based semiconductor device including a buffer layer, a three-dimensional stress tuning layer formed on the buffer layer, a first-type semiconductor layer formed on the three-dimensional stress tuning layer, an active layer formed on the first-type semiconductor layer, and a second-type semiconductor layer formed on the active layer. The three-dimensional stress tuning layer and the buffer layer cooperatively define an interface therebetween. The interface has a three-dimensional composition distribution.

Abstract: A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

Abstract: Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.

Abstract: A semiconductor light-emitting device according to an embodiment of the present disclosure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer and including a plurality of well layers. In the plurality of well layers included in the active layer, a band gap inclination angle ?1 of a second well layer located relatively close to the p-type semiconductor layer is smaller than a band gap inclination angle ?2 of a first well layer located relatively close to the n-type semiconductor layer.

Abstract: The approach presented here provides a membrane unit (105) comprising micro-optical structures (115), which comprises a wafer (110) as carrier basis of the micro-optical structures (115), an intermediate substrate (300) connected to the wafer (110), and a carrier (130) connected to the intermediate substrate (300), wherein the coefficients of thermal expansion of the wafer (100), of the intermediate substrate (300) and of the carrier (130) are dimensioned such that a coefficient of expansion of the carrier (130) is greater than a coefficient of expansion of the intermediate substrate (300) and the coefficient of expansion of the intermediate substrate (300) is greater than or equal to a coefficient of expansion of the wafer (110).

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

Abstract: Techniques are disclosed for methods and apparatuses for increasing the breakdown voltage while substantially reducing the voltage leakage of an electrostatic chuck at temperatures exceeding about 300 degrees Celsius in a processing chamber.

Abstract: III-nitride based high electron mobility transistors (HEMTs), such as AlGaN/GaN HEMTs on Silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.

Abstract: A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.

Abstract: Disclosed are synthetic garnets and related devices that can be used in radio-frequency (RF) applications. In some embodiments, such RF devices can include garnets having reduced or substantially nil Yttrium or other rare earth metals. Such garnets can be configured to yield high dielectric constants, and ferrite devices, such as TM-mode circulators/isolators, formed from such garnets can benefit from reduced dimensions. Further, reduced or nil rare earth content of such garnets can allow cost-effective fabrication of ferrite-based RF devices. In some embodiments, such ferrite devices can include other desirable properties such as low magnetic resonance linewidths. Examples of fabrication methods and RF-related properties are also disclosed.