Heterojunction Device Patents (Class 257/183)
  • Patent number: 10784353
    Abstract: A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 22, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Lain-Jong Li, Hao-Ling Tang, Ming-Hui Chiu
  • Patent number: 10770556
    Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 8, 2020
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCE
    Inventors: Xinhong Cheng, Lingyan Shen, Zhongjian Wang, Duo Cao, Li Zheng, Qian Wang, Dongliang Zhang, Jingjie Li, Yuehui Yu
  • Patent number: 10734508
    Abstract: A compound semiconductor device includes a first transistor formed on a GaN epitaxial layer. The first transistor includes a gate electrode, a source electrode, a drain electrode, and a protective film covering them. End portions of the first transistor do not overhang the protective film, and the concentration of fluorine in the GaN epitaxial layer in the region where the gate electrode of the first transistor is formed is substantially zero.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 4, 2020
    Assignee: ADVANTEST CORPORATION
    Inventors: Jun'ichi Okayasu, Taku Sato
  • Patent number: 10665465
    Abstract: Provided is a surface treatment method for a SiC substrate (40), the method being capable of controlling whether to generate a step bunching or the type of step bunching that is generated. In the surface treatment method in which the surface of the SiC substrate (40) is etched by heating the SiC substrate (40) under Si vapor pressure, an etching mode and an etching depth which are determined at least on the basis of an etching rate, are controlled to etch the SiC substrate (40), so that a surface pattern of the SiC substrate (40) after etching treatment is controlled.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 26, 2020
    Assignees: KWANSEI GAKUIN EDUCATIONAL FOUNDATION, TOYO TANSO CO., LTD.
    Inventors: Tadaaki Kaneko, Koji Ashida, Yasunori Kutsuma, Satoshi Torimi, Masato Shinohara, Youji Teramoto, Norihito Yabuki, Satoru Nogami
  • Patent number: 10651317
    Abstract: High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 12, 2020
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Anthony Kaleta, Douglas Carlson, Timothy E. Boles
  • Patent number: 10600889
    Abstract: A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10600935
    Abstract: A nitride based semiconductor device including a buffer layer, a three-dimensional stress tuning layer formed on the buffer layer, a first-type semiconductor layer formed on the three-dimensional stress tuning layer, an active layer formed on the first-type semiconductor layer, and a second-type semiconductor layer formed on the active layer. The three-dimensional stress tuning layer and the buffer layer cooperatively define an interface therebetween. The interface has a three-dimensional composition distribution.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 24, 2020
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Chang-Cheng Chuo, Shengchang Chen, Heqing Deng
  • Patent number: 10566389
    Abstract: Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 18, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jaewoo Shim, Hae Won Lee
  • Patent number: 10540916
    Abstract: A semiconductor light-emitting device according to an embodiment of the present disclosure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer and including a plurality of well layers. In the plurality of well layers included in the active layer, a band gap inclination angle ?1 of a second well layer located relatively close to the p-type semiconductor layer is smaller than a band gap inclination angle ?2 of a first well layer located relatively close to the n-type semiconductor layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 21, 2020
    Assignee: SONY CORPORATION
    Inventors: Kota Tokuda, Takayuki Kawasumi
  • Patent number: 10534152
    Abstract: The approach presented here provides a membrane unit (105) comprising micro-optical structures (115), which comprises a wafer (110) as carrier basis of the micro-optical structures (115), an intermediate substrate (300) connected to the wafer (110), and a carrier (130) connected to the intermediate substrate (300), wherein the coefficients of thermal expansion of the wafer (100), of the intermediate substrate (300) and of the carrier (130) are dimensioned such that a coefficient of expansion of the carrier (130) is greater than a coefficient of expansion of the intermediate substrate (300) and the coefficient of expansion of the intermediate substrate (300) is greater than or equal to a coefficient of expansion of the wafer (110).
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 14, 2020
    Assignee: JENOPTIK Optical Systems GmbH
    Inventor: Christian Ziener
  • Patent number: 10510868
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 10461074
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Wolfgang Werner
  • Patent number: 10418472
    Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Jia Guo, Ali Salih, Chun-Li Liu
  • Patent number: 10418483
    Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 17, 2019
    Assignee: NXP B.V.
    Inventors: Bernhard Grote, Xin Lin, Saumitra Raj Mehrotra, Ljubo Radic, Ronghua Zhu
  • Patent number: 10381470
    Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 13, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alessandro Chini
  • Patent number: 10355105
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 10347748
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Muhammad Rahman, Srikanth Balaji Samavedam
  • Patent number: 10325800
    Abstract: Techniques are disclosed for methods and apparatuses for increasing the breakdown voltage while substantially reducing the voltage leakage of an electrostatic chuck at temperatures exceeding about 300 degrees Celsius in a processing chamber.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 18, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kulshreshtha, Kwangduk Douglas Lee, Bok Hoen Kim, Zheng John Ye, Swayambhu Prasad Behera, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Jian J. Chen
  • Patent number: 10312358
    Abstract: III-nitride based high electron mobility transistors (HEMTs), such as AlGaN/GaN HEMTs on Silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 4, 2019
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Fan Ren, Stephen John Pearton, Mark E. Law, Ya-Hsi Hwang
  • Patent number: 10283633
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 7, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10256352
    Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 9, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Min Sun, Tomas Apostol Palacios
  • Patent number: 10249757
    Abstract: A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong Cheol Kim, Hyung Suk Lee, Eun Shoo Han
  • Patent number: 10230146
    Abstract: Disclosed are synthetic garnets and related devices that can be used in radio-frequency (RF) applications. In some embodiments, such RF devices can include garnets having reduced or substantially nil Yttrium or other rare earth metals. Such garnets can be configured to yield high dielectric constants, and ferrite devices, such as TM-mode circulators/isolators, formed from such garnets can benefit from reduced dimensions. Further, reduced or nil rare earth content of such garnets can allow cost-effective fabrication of ferrite-based RF devices. In some embodiments, such ferrite devices can include other desirable properties such as low magnetic resonance linewidths. Examples of fabrication methods and RF-related properties are also disclosed.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Bowie Cruickshank, Rickard Paul O'Donovan, Iain Alexander MacFarlane, Brian Murray, Michael David Hill
  • Patent number: 10204682
    Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
  • Patent number: 10193504
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 29, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10186591
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 22, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10177046
    Abstract: A technique relates to forming a semiconductor device. A first substrate is provided adjacent to a second substrate. The first substrate has a first surface orientation, and the second substrate has a second surface orientation different from the first surface orientation. An n-type field effect transistor (NFET) device is formed with the first substrate. The NFET device includes a first source, a first drain, and one or more first fins. The first source and the first drain have a vertical relationship with respect to the one or more first fins. A p-type field effect transistor (PFET) device is formed with the second substrate. The PFET device includes a second source, a second drain, and one or more second fins. The second source and the second drain have a vertical relationship with respect to the one or more second fins.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10177284
    Abstract: A sidewall light emitting ultraviolet light emitting diode and a method of manufacturing thereof are disclosed. A light emitting structure is formed in an active region recessed from a substrate surface, and the light emitting structure is formed by growth in a direction parallel to the surface of the substrate. Also, a reflective metal layer is formed above or below the light emitting structure such that ultraviolet light can be released in a second direction perpendicular to a first direction which is the growth direction of the light emitting structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 8, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Dong-Seon Lee, Duk-Jo Kong, Jun-Yeob Lee, Mun-Do Park
  • Patent number: 10162200
    Abstract: An electro-optic (EO) phase modulator is disclosed. The EO phase modulator includes: an insulating layer; a central optical waveguide over the insulating layer; a first region having a first type doping adjacent to a first sidewall of the central optical waveguide; a second region having a second type doping opposite to the first type doping adjacent to a second sidewall of the central optical waveguide opposite to the first sidewall; and a first dielectric layer passing through the central optical waveguide from a top surface of the central optical waveguide to a bottom surface of the central optical waveguide. A method of manufacturing the same is disclosed as well.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Feng Wei Kuo
  • Patent number: 10163912
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
  • Patent number: 10141371
    Abstract: Disclosed herein are wide band gap integrated circuits, such as gallium nitride (GaN) integrated circuits, including a plurality of groups of epitaxial layers formed on an engineered substrate, and methods of making the WBG integrated circuits. The epitaxial layers have a coefficient of thermal expansion (CTE) substantially matching the CTE of the engineered substrate. Mesas, internal interconnects, and electrodes configure each group of epitaxial layers into a WBG device. External interconnects connect different WBG devices into a WBG integrated circuit. The CTE matching allows the formation of epitaxial layers with reduced dislocation density and an overall thickness of greater than 10 microns on a six-inch or larger engineered substrate. The large substrate size and thick WBG epitaxial layers allow a large number of high density WBG integrated circuits to be fabricated on a single substrate.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: November 27, 2018
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 10134591
    Abstract: This invention is directed toward a method for manufacturing a semiconductor device with a heterostructure comprises covering a semiconductor structure with a seed layer structure; forming one or more separated circularly shaped openings in the seed layer structure to expose the semiconductor structure therein, and leave the seed layer structure outside the one or more separated circularly shaped openings; forming an insulator layer thereon; etching the obtained structure to (i) expose at least a portion of the seed layer structure, such that the exposed at least portion of the seed layer structure surrounds each of the one or more separated circularly shaped openings, and (ii) optionally expose the semiconductor structure, in the one or more separated circularly shaped openings; and epitaxially growing a semiconductor layer from the exposed at least portion of the seed layer structure, firstly mainly vertically and then into each of the one or more separated circularly shaped openings until the epitaxially g
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 20, 2018
    Assignee: Tandem Sun AB
    Inventor: Yanting Sun
  • Patent number: 10115589
    Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 30, 2018
    Assignees: SHIN-ETSU HANDOTAI CO., LTD., SANKEN ELECTRIC CO., LTD.
    Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi
  • Patent number: 10109535
    Abstract: A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10074739
    Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, one or more nitride layers containing aluminum located on the second nitride semiconductor layer, a source electrode located on the second nitride semiconductor layer, a drain electrode located on one of the second nitride semiconductor layer or the nitride layer, and a gate electrode located between the source electrode and the drain electrode. An end of the nitride layer on the source electrode side thereof is located between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 11, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Yoshioka, Kohei Oasa, Hung Hung, Yasuhiro Isobe
  • Patent number: 9984931
    Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongwoo Han, Kwang-Yong Yang, Jinwook Lee, Kyungyub Jeon, Haegeon Jung, Dohyoung Kim
  • Patent number: 9978672
    Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dirk Ahlers, Gilles Delarozee, Daniel Schleisser, Christopher Spielman, Thomas Stoek
  • Patent number: 9966377
    Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mirco Cantoro, YeonCheol Heo
  • Patent number: 9882039
    Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 30, 2018
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Patent number: 9842777
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 12, 2017
    Assignee: IMEC vzw
    Inventors: Liesbeth Witters, Kurt Wostyn
  • Patent number: 9834863
    Abstract: Bulk crystal of group III nitride having thickness greater than 1 mm with improved crystal quality, reduced lattice bowing and/or reduced crack density and methods of making. Bulk crystal has a seed crystal, a first crystalline portion grown on the first side of the seed crystal and a second crystalline portion grown on the second side of the seed crystal. Either or both crystalline portions have an electron concentration and/or an oxygen concentration similar to the seed crystal. The bulk crystal can have an additional seed crystal, with common faces (e.g. same polarity, same crystal plane) of seed crystals joined so that a first crystalline part grows on the first face of the first seed crystal and a second crystalline part grows on the first face of the second seed crystal. Each crystalline part's electron concentration and/or oxygen concentration may be similar to its corresponding seed crystal.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: December 5, 2017
    Assignees: SixPoint Materials, Inc., Seoul Semiconductor Co., Ltd.
    Inventors: Tadao Hashimoto, Edward Letts
  • Patent number: 9831254
    Abstract: An anti-fuse structure is provided that contains multiple breakdown points which result in low resistance after the anti-fuse structure is blown. The anti-fuse structure is provided using a method that is compatible with existing FinFET device processing flows without requiring any additional processing steps.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Adra V. Carr, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9812445
    Abstract: A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 7, 2017
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Patrick B. Shea, Michael Rennie, Sandro J. Di Giacomo
  • Patent number: 9806407
    Abstract: Safety radio devices are described herein. One method of constructing a safety radio device includes mounting a radio module on a first layer of a circuit board, fabricating an antenna on a second layer of the circuit board, and constructing a safety radio device by connecting the radio module to the antenna through an aperture formed in the second layer of the circuit board.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: October 31, 2017
    Assignee: Honeywell International Inc.
    Inventors: Dale Broemer, Kelly Englot, Patrick Gonia, AnjayaChary Boddupally
  • Patent number: 9780791
    Abstract: A switch comprising a spin-transistor and a first control wire. The spin-transistor is configured so that when a magnetic field applied to the spin-transistor is less than a threshold value, the transistor is in a conductive state in which electric current flows through the spin-transistor. When the magnetic field applied to the spin-transistor is greater than the threshold value, the spin-transistor is in a resistive state in which the electric current flowing through the spin-transistor is substantially reduced. The first control wire is for receiving a current to affect the magnetic field applied to the spin-transistor.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: October 3, 2017
    Assignee: Northwestern University
    Inventors: Joseph S. Friedman, Gokhan Memik, Bruce W. Wessels
  • Patent number: 9766410
    Abstract: Techniques for forming a photonic integrated circuit having a facet coupler and a surface coupler are described. The photonic integrated circuit may be on a wafer, which may be diced to form an integrated device. The facet coupler may be positioned proximate to an edge of the integrated device, and the surface coupler may be positioned on a surface of the integrated device. The surface coupler may allow for evaluation and assessment of the circuit's performance, which may facilitate wafer-level testing of the circuit and diagnosis of the circuit before and after packaging.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: September 19, 2017
    Assignee: Acacia Communications, Inc.
    Inventor: Long Chen
  • Patent number: 9722067
    Abstract: A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tasuku Ono, Takashi Onizawa, Yoshikazu Suzuki
  • Patent number: 9704784
    Abstract: A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP USA, Inc.
    Inventors: Matthieu Lagouge, Qing Zhang, Mohommad Choudhuri, Gul Zeb
  • Patent number: 9685559
    Abstract: A vertically stacked heterostructure device includes: (1) a substrate; and (2) vertically stacked layers disposed over the substrate and including (a) a source electrode including a layer of graphene; (b) a drain electrode; and (c) a semiconducting channel disposed between the source electrode and the drain electrode. During operation of the device, a current is configured to flow between the source electrode and the drain electrode through the semiconducting channel.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 20, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiangfeng Duan, Woojong Yu, Yuan Liu, Yu Huang