Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.

Abstract: A semiconductor memory device includes first and second conductive contact layers (12, 15) and an hydrogenated, silicon-rich, amorphous silicon alloy layer (14), particularly an amorphous silicon nitride or amorphous silicon carbide alloy, extending between the contact layers. A defect band is induced in the amorphous silicon layer which lowers the activation energy level for the transport of carriers through the structure by an amount that is selectable and determined by the defect band. The defect band is created by a programming process, for example, using current stressing or particle bombardment. A memory matrix array device is provided by forming a row and column array of such memory devices from common deposited layers on a common substrate with crossing sets of row and column conductors separated by a layer of the alloy material defining a memory device at each of their cross-over regions.

Abstract: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active layer. A second nitride semiconductor layer having a band gap energy smaller than that of the first layer is provided over the first layer. Further, a third nitride semiconductor layer having a band gap energy larger than that of the second layer is provided over the second layer.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow "hot" electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: A semiconductor photodetector includes a semiconductor substrate of a first conductivity type; a light absorption recombination layer disposed on a front surface of the semiconductor substrate and having a band gap energy smaller than the semiconductor substrate; a first conductivity type barrier layer disposed on the light absorption recombination layer and having a band gap energy larger than the light absorption recombination layer; an undoped light absorption layer disposed on the barrier layer and having a band gap energy larger than the light absorption recombination layer and smaller than the barrier layer; an undoped window layer disposed on the light absorption layer and having a band gap energy larger than the light absorption layer; and an impurity doped region of a second conductivity type in a region extending from the window layer to the light absorption layer.

Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.

Abstract: A hetero-junction bipolar transistor comprising a collector layer, a base layer and an emitter layer formed stepwise in this order wherein the emitter layer comprises a plurality of layers including an AlGaAs layer, and a passivation layer is formed at a stepwise portion between the base layer and the emitter layer, and of a material having a bandgap larger than that of the base layer, and provided with a phosphide layer on the surface thereof.

Abstract: The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al.sub.x Ga.sub.1-x As 0.2.ltoreq.x.ltoreq.1 barrier layer. At temperatures greater than 250.degree. C., the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350.degree. C. ambient temperature.

Abstract: A heterojunction FET includes an electron supply layer formed on a non-doped semiconductor layer serving as a channel forming layer and a current path forming layer formed on the electron supply layer. The electron supply layer has an energy band gap greater than the non-doped semiconductor layer and its portion under a gate electrode is always depleted at any gate bias voltage in a bias voltage range for operating of the field effect transistor. The current path forming layer has a larger electron mobility than the electron supply layer. The gate electrode is formed on the current supply layer. Under a high gate bias voltage condition, parallel conduction does not occur in the electron supply layer but does occur in the current path forming layer. Since the current path forming layer has a larger carrier mobility than the electron supply layer, the mutual conductance value is kept high.

Abstract: A semiconductor laser device in which a housing with an optical fiber inserted in is secured to a header with a semiconductor laser chip mounted on is integrated, the light emitting surface of the semiconductor laser chip and the end surface of the optical fiber are opposed to each other, and there is provided a photodiode chip for detecting the signal light emitted from the backside (rear end surface) of the light emitting surface of the semiconductor laser chip, in the top incidence type photodiode chip having a pn junction area of the structure as a photo-sensing region, the first region is surrounded by a second region of the second conductivity type formed at a portion of the semiconductor layer. The second region has the same or larger depth as or than that of the first region. Thus, even if a light is directed to the outside of the photo-sensing region, extra charges into the photo-sensing region is prevented.

Abstract: An avalanche photo-diode in the InP-InGaAs-InGaAsP system has a thin main photo-absorbing layer for converting light into carriers, and an auxiliary photo-absorbing layer and a protection layer are provided under the main photo-absorbing structure for absorbing residue of the light without attracting toward electrodes, thereby producing an photo-detecting signal with a sharp trailing edge.

Abstract: An optical switching device is comprised of an asymmetrical double barrier resonant tunnelling diode (RTD) connected in series with load resistance apparatus to a power source, apparatus for illuminating the RTD with an infrared incident light beam, apparatus for applying signal power to the RTD, and apparatus for varying the power within the RTD.

Abstract: A static induction semiconductor device has a low-resistance drain region, a high-resistance layer disposed on the drain region, a low-resistance source region spaced from the high-resistance layer, a low-resistance gate region disposed in the high-resistance layer, and a hetero layer disposed in an interface between the high-resistance layer and the source region and an interface between the gate region and a surface protective layer on the gate and source regions. The hetero layer, which may be made of AlGaAs, has a band gap larger than a semiconductor crystal such as GaAs of the drain, source, and gate regions. The static induction semiconductor device has a low resistance turned on and can operate in a bipolar mode.

Abstract: A field effect transistor (FET) has a gate electrode, a source electrode and a drain electrode formed on a GaInAs/GaAs quantum well layer structure having an undoped GaAs layer, an impurity doped GaInAs layer, and an undoped GaAs cap layer. The FET further has low resistivity regions formed by ion-implantation in a source region and the drain region of the GaInAs/GaAs quantum well layer structure, and has the impurity doped GaInAs layer as a channel, and further has an undoped GaAs cap layer with a 30-50 nm thickness. An annealing temperature for activating the low resistivity region is not higher than a temperature at which the GaInAs/GaAs quantum well structure substantially breaks and not lower than a temperature at which the sheet resistivity of the low resistivity region sufficiently reduces. The FET thus manufactured has desired characteristics for the GaInAs/GaAs quantum well structure and the low resistivity region, and attains low noise and high speed operation.

Abstract: An enhanced mobility semiconductor comprising a host quantum well having at least two charge carrier barrier layers of a wide bandgap material, each of the two charge carrier barrier layers being separated by a conducting region containing charge carriers is provided. A number of phonon barriers having a predetermined thickness are formed in the conducting region wherein the predetermined thickness is chosen to allow charge carrier tunneling through the phonon barriers.