Abstract: The present invention provides a novel I/O pad structure and layout methodology which allows the effective wire bonding pitch to be reduced by circumventing the usual constraints of wire bonding technology. The bonding pad layout of the present invention entails the use of two rows of pads on the chip periphery as opposed to the more conventional single row, in-line arrangement. The bonding pads are arranged in a novel way, by radial staggering, to ensure no overlapping of bonding wire trajectories, even when conventional lead frames are used for the package. Comparing the radially staggered arrangement of the bonding pads of the present invention to convention single row, in-line bonding pad configuration, in the radially staggered arrangement every other pad is moved inward in the radial direction to form a second row. The radial direction used is from a projection point, typically the die center, and is dependent on the I/O circuitry height and the total number of pins of the package.

Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.

Abstract: An integrated circuit package allows coupling of an integrated device within the package to the signal terminals of the package according to more than one connection pattern. The connection pattern is realized by coupling multiplexers between the integrated device and the signal terminals such that the pattern of coupling between the integrated device and the signal terminals can be controlled by a control signal. The control signal can be produced external to the package or within the package. In response to a control signal of the first state, the signal terminals are connected to the integrated device in a first pattern. In response to the control signal in the second state, the signal terminals are connected to the integrated device in a second pattern, different from the first pattern. In one embodiment, the first pattern and second pattern are mirror images to allow the packages to be mounted to opposite sides of a module while minimizing routing difficulties.

Abstract: An integrated circuit having an outer ring of bonding pads which is positioned so as to be adjacent to and concentric with the perimeter of the integrated circuit. The outer ring of bonding pads extends for at least a first portion of the perimeter. An inner ring of bonding pads is positioned interior of, adjacent to, and concentric with the first ring of bonding pads. The inner ring of bonding pads extends for at least a second portion of the perimeter. The first portion is greater than the second portion, or in other words, the outer ring of bonding pads extends further around the integrated circuit than the inner ring of bonding pads. In addition, the outer ring of bonding pads has a greater number of bonding pads that the inner ring of bonding pads. Traces are electrically connected to the bonding pads of the inner and outer rings, such that each pad is electrically connected to a unique trace, meaning that each pad has a trace which is associated with just that pad and with no other pad.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A gate array driven by a plurality of source voltages and an electronic equipment using such a gate array are provided. The gate array comprises a plurality of P-well regions and a plurality of N-well regions, all of which are formed in an internal cell region in a first direction and alternately arranged in a second direction perpendicular to the first direction on a semiconductor substrate. A plurality of first basic cells receive a first source voltage VDD1 through a first source wiring layer, these first basic cells being respectively formed on a pair of P-well and N-well regions. A plurality of second basic cells receive a second source voltage VDD2 through a second source wiring layer, these second basic cells being respectively formed on a pair of P-well and N-well regions. A voltage level shifter for shifting the voltage level between data voltages outputted from first and second basic cell trains is formed on an region containing at least three of the P-well and N-well regions.

Abstract: An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: Integrated circuits having single and multiple device modes are described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a "by n" input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a ".times.n" configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a ".times.2n" configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.

Abstract: A monolithic integrated circuit utilizing areas associated with unused devices for wiring signal lines, thereby implementing effective wiring and improving high frequency characteristics. A common substrate consisting of a semiconductor substrate, and active devices, capacitor electrodes and resistors formed on the semiconductor substrate, is followed by a dielectric film, a ground metal, a dielectric film whose thickness is equal to or greater than 1 .mu.m, and signal lines. A desired circuit is formed by connecting the signal lines with electrodes of the active devices and other elements via, holes in the dielectric films, and windows of the ground metal. The windows of the ground metal are formed over portions of active devices which are used as components of the circuit.

Abstract: A semiconductor integrated circuit has a chip check circuit for detecting cracks and other defects in the chip during operation. The chip check circuit extends in the chip from an input terminal to an output terminal so as to scan a predetermined wide area. The chip check circuit has at least one signal line extending near or within a circuit block in the chip so that the signal line can be broken together with the circuit block. The chip check circuit may further comprise one or more inverters, and/or one or more two-wire logic circuits.

Abstract: A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.

Abstract: A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The cell architecture includes a substrate tap area that allows for the accommodation of a plurality of electrically isolated metal lines.

Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Abstract: The invention provides a semiconductor device in the form of an LSI circuit having a large number of terminals wherein an increase of the number of pad terminals for a power source potential and wherein a ground potential does not increase the inductances of wiring lines to the pad terminals and the terminals are arranged efficiently. The semiconductor device includes a semiconductor chip having a semiconductor substrate on which a first pad arrangement region, a buffer arrangement region and a second pad arrangement region are successively assured in this order toward the outer side around an internal circuit formation region and arranged in parallel to each other. A first power source pad and a first grounding pad for an internal circuit are provided in the first pad arrangement region while a plurality of pads for inputting and/or outputting signals are provided in the second pad region. The pads are bonding connected by respective thin metal lines to external lead terminals provided on a support.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). To reduce RFI, on-chip dedoupling capacitors are included in the design. To gain maximum advantage of these decoupling capacitors, they should be placed close to drivers and flip-flops. In a standard cell design approach for fabrication of the ICs, capacitors are embedded below the power supply lines. These capacitors are put in special cells, called cap-cells, which are placed by the place and route software on either side of each row of standard cells. Thin oxide capacitors are preferred because they offer the largest capacitance per area. In addition, first and second metal above the capacitor are increased to form thick oxide capacitors that give additional capacitance.

Abstract: A gate array type semiconductor device has a plurality of basic array block cells. The basic array block cells are made up of at least one basic cell and only one input/output cell. Additionally, the basic array block cells are arranged in a matrix form on a mother wafer. The number of the basic cells in each basic array block cell is determined by a gate scale requirement but the number of input/output cells remain one. Different pellet sizes may be provided on the same mother wafer. This enables to produce various kinds of gate arrays in a short turn around time and a low cost.

Abstract: A semiconductor integrated circuit device includes an internal function circuit formed on a first rectangular region on a rectangular semiconductor chip for implementing a function specific to the device, and a predetermined function control circuit formed on a second rectangular region for implementing a fixed function irrespective of the function implemented by said internal function circuit. First and second rectangular regions are separate regions. In the hierarchical design of an integrated circuit device, the circuit of the first rectangular region can be used as the structure component of another integrated circuit on another chip. The predetermined function control circuit can be laid out on the second rectangular region of another chip. The predetermined function control circuit is a testing circuit of boundary scan method, including a standardized structure component.

Abstract: An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.

Abstract: The I/O buffer layout of a pad-limited die comprises a pad ring having four partially-overlapping I/O-buffer arrays arranged in a pinwheel pattern at the periphery of a square die. To enable electrical interconnection of transversely-overlapping I/O buffers with the core logic of the die, overlapping I/O buffers of adjacent I/O-buffer arrays are separated by routing channels and the circuitry of longitudinally-overlapping buffers is abridged so that each of these buffers is capable of performing only a limited range of functions.

Abstract: An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V.sub.DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

Abstract: In a semiconductor device wherein an active device circuit and electrically conductive lines, such as a power source line for supplying power to the semiconductor active device circuit or signal lines for inputting a signal to the semiconductor active device circuit, are formed together on a single substrate, an improved arrangement wherein a conventional power source or signal line is formed by using a plurally of individual lines of substantially uniform electrical resistance where the electrical resistance of each line is limited to a predetermined value. Moreover, a waveform deterioration response signal component is added to a signal transmitted through the signal lines so as to improve the transmitted signal by compensating for waveform deterioration experienced during circuit operation. In addition, an electrical capacity forming electrode is provided alongside substantial length of the power source line.

Abstract: An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number.

Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Abstract: A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel.

Abstract: A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.

Abstract: This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

Abstract: A high functional capacity semiconductor based system for which the semiconductor material cost increases substantially linearly with functional capacity. The device is manufactured by taking individual, lower functional capacity devices having an extendible architecture and utilizing them in a high interconnect packaging method such as flip-chip technology. Multiple individual chips are interconnected into a single, larger device by means of this packaging technique. Because each individual chip is extendible, the resulting larger capacity device has substantially the same architecture as the smaller devices from which it is made. This means that the final device is essentially equivalent to a higher capacity single device based on the architecture of the smaller component devices.

Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Abstract: A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip, includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the name material am the power electrode.

Abstract: Inter-circuit interference such as a switching noise is suppressed without deteriorating the circuit integration. An output buffer (1) is connected to power source lines (11) and (21) by though holes. In a similar manner, an output buffer (2) is connected to power source lines (11) and (21) and an output buffer (3) is connected to power source lines (22) and (12). The power source lines (21) and (22) are disposed on the same straight line and terminate in an area which is sandwiched by the output buffers (2) and (3). The power source lines (11) and (12) are disposed on the same straight line and terminate in an area which is sandwiched by the output buffers (2) and (3).

Abstract: An integrated circuit analog crosspoint switch FET array which utlilizes considerably reduced silicon substrate area than previously. In a preferred embodiment, pairs of the separate diffused regions of different FETs which are connected to the same input are common, forming separate single diffused regions. The separate single diffused regions and the central single diffused regions alternate continuously in a row, separated by the channel regions forming the various transistors. The result is a continuous row of transistors having common diffused regions, except for the transistors at the end of the row, which have their outer diffused regions not in common with any other.

Abstract: Signal wirings are incorporated in a semiconductor integrated circuit device for propagating a multi-bit signal from an array of pads to input buffer circuits, and either wiring gap or wiring width is changed for canceling difference in time constant due to the different wiring lengths so that the component bits of the multi-bit signal concurrently arrive at the input buffer circuits.

Abstract: A semiconductor integrated circuit device that enables measurement of the capacitance of an insulator film without integration scale reduction in internal circuits. The device has an internal circuit area and an I/O area on a semiconductor substrate. A first bonding pad area redundant for the device and a second bonding pad area used for an I/O terminal are formed in the I/O area. A wiring conductor is formed on the I/O area to extend from the first bonding pad area to the internal circuit area through the second bonding pad area. An interlayer insulator film is formed on the I/O area to cover the wiring conductor. A bonding pad is formed on the interlayer insulator film as the I/O terminal. The bonding pad is provided on the second bonding pad area to be connected to the wiring conductor. An electrode is provided on the first bonding pad area to be opposite to the wiring conductor through the interlayer insulator film, and is isolated from the wiring conductor.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions of high angle ion implantation are required.

Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer.

Abstract: A new configurable gate array is defined in a master slice wafer form without borders of the kind currently known between constituent transistor gates, effectively providing a sea of gates over the wafer, interrupted if at all by islands, containing markers or the like; and a resultant application specific integrated circuit formed of such master slice is defined. In the IC, transistor gate cells, which are the same type of cells used for other purposes in the IC, are configured to serve the input and output function. Accordingly, the input and output function may be placed on any location in the IC. As an incident to personalization of the wafer saw lanes are formed of channels that extend over transistor cells and the latter cells are consequently destroyed in slicing the wafer. Means are also disclosed for an improved E-beam lithographic apparatus which permits an IC chip to be placed on an area of a wafer that is occupied by a marker, providing a wiring or macro design that avoids the marker.

Abstract: A plurality of different power source potentials are optionally selected in a semiconductor integrated circuit. First and second semiconductor segments (3) and (4) are both in the form of a number of rows which are separated from each other by spacings (14). Power source wires (6) and (7) for supplying potentials (V1) and (V2) are disposed above the second semiconductor regions (4). Cells are formed in different wells, and therefore, it is possible that different cells receive different power source potentials. Contacts (61) or (71) are made to the second semiconductor segments (4) so that the second semiconductor segments (4) are connected to the power source wire (6) or (7). Selection of and connection to one of the wires are attained in a slicing process.

Abstract: In a semiconductor device, a signal delay element is configured by using resistance and capacitance components included in a region except regions where logic elements for a gate array exist, and the signal delay element is inserted between a logic element for outputting signals and logic elements for receiving the signals and connected to these logic elements. A placing and wiring apparatus for producing the semiconductor device is disclosed.

Abstract: A semiconductor wafer comprises a plurality of individual dies containing integrated circuits which are substantially isolated from each other. The wafer is severable between the dies to physically singulate the dies from each other. The wafer includes test cycling circuitry for test cycling the individual dies. A Vcc bus and a Vss bus overly a passivation layer and are electrically connected through the passivation layer with Vcc and Vss pads associated with the individual dies.

Abstract: A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.

Abstract: A semiconductor integrated circuit device includes an interface corresponding to a relatively high signal level; an interface corresponding to a relatively low signal level; and an internal circuit made responsive to a signal through either interface for generating a signal to be transmitted to the other interface. The interface corresponding to a relatively high level, the internal circuit, and a drive control circuit constituting the input circuit and output circuit of the interface corresponding to a relatively low level are operated by an operating voltage corresponding to the relatively high level. An output element of the output circuit in the interface corresponding to a relatively low level, which is to be driven by the drive control circuit, is operated by an operating voltage corresponding to the relatively low level.

Abstract: A semiconductor integrated circuit device comprises a plurality of peripheral power supply lines extending along the periphery of an internal circuit region formed in a semiconductor chip. Bonding pads are arranged outside of the peripheral power supply lines, wherein the wiring layers used in the peripheral power supply line arranged at the outermost periphery are made less by one than those used in the inner peripheral power supply line adjacent to the outermost peripheral power supply line. Reduced wiring layers are formed with power leading lines for connecting the inner peripheral power supply line and the bonding pads. Moreover, the power leading lines for connecting the outermost peripheral power supply lines and the bonding pads are formed of the same wiring layer as that of the outermost peripheral power supply line.

Abstract: A semiconductor device comprises a rectangular semiconductor chip provided with an integrated circuit, and a plurality of voltage stress examination pads formed on the semiconductor chip for applying stress examination voltage to the integrated circuit, and having the same function, wherein the voltage stress examination pads are provided on opposite sides of the semiconductor chip.

Abstract: A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.