Gate Arrays Patents (Class 257/202)
  • Patent number: 11049467
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 11018157
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11011545
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 11004923
    Abstract: Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 11, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung-Nam Lim, Yu-Ho Jung, Dong-Young Kim
  • Patent number: 10998327
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Bin Kang, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Patent number: 10998176
    Abstract: The present embodiment relates to an ion detector provided with a structure for suppressing degradation over time in an electron multiplication mechanism in a multi-mode ion detector. The ion detector includes a dynode unit, a first electron detection portion including a semiconductor detector having an electron multiplication function, a second electron detection portion including an electrode, and a gate part. The first and second electron detection portions are capable of ion detection at different multiplication factors. The gate part includes at least a final-stage dynode as a gate electrode, and controls switching between passage and interruption of secondary electrons which are directed toward the first electron detection portion by adjusting a set potential of the gate electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 4, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi Kobayashi, Takeshi Endo, Hiroki Moriya, Toshinari Mochizuki
  • Patent number: 10998241
    Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. Khaderbad, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10916190
    Abstract: A driving circuit, a display panel, and a display device are provided. The display panel comprises a plurality of common electrodes; a plurality of phototransistors, two or more phototransistors among the plurality of phototransistors being disposed in an area corresponding to each of the plurality of common electrodes; a plurality of photo-control lines electrically connected to a gate electrode of at least one phototransistor among the plurality of phototransistors; a plurality of photo-driving lines electrically connected to a first electrode of at least one phototransistor among the plurality of phototransistors, and a plurality of read-out lines, each of the plurality of read-out lines being electrically connected to a single common electrode among the plurality of common electrodes, and electrically connected to second electrodes of all of the phototransistors disposed in the area corresponding to the single common electrode to which each of the plurality of read-out lines are electrically connected.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 9, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HyunGon Kim, DukKeun Yoo
  • Patent number: 10896912
    Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Patent number: 10886273
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 10872935
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byong-Hoo Kim, Min-Joo Kim, Eun-Pyo Hong, Jae-Won Lee, Sang-Hoon Pak, Sang-Hyuk Won, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Patent number: 10867102
    Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10868199
    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10846458
    Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun Li Chen, Li-Chun Tien, Ting Yu Chen, Wei-Ling Chang
  • Patent number: 10817637
    Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Naya Ha, Yong-Durk Kim, Bong-hyun Lee, Hyung-ock Kim, Kwang-ok Jeong, Jae-hoon Kim
  • Patent number: 10811375
    Abstract: An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Arm Limited
    Inventors: Kishan Chanumolu, Vijaya Kumar Vinukonda
  • Patent number: 10812288
    Abstract: A communication system capable of shortening a setting time of an ID and reducing an incorrect setting is provided. A master device, when receiving an ID assignment request from a writing device, turns on all a plurality of semiconductor relays, and after a predetermined time has elapsed, turns all off, sequentially turns on the semiconductor relays and each time turning on the semiconductor relays, sends the corresponding ID. The plurality of slave devices, when receiving the ID assignment request from the writing device after supplying power, stores the fact in the ID request area, waits for a reception of the ID from the master device without confirming reception of the ID assignment request, and sets the ID as its own ID if determining that the ID assignment request has already been received by the ID request area after power is supplied.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 20, 2020
    Assignee: YAZAKI CORPORATION
    Inventor: Yoshihide Nakamura
  • Patent number: 10804225
    Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10777673
    Abstract: A high electron mobility transistor (HEMT) gallium nitride (GaN) bidirectional blocking device includes a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 15, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: David Sheridan
  • Patent number: 10755017
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Laura R. Darden, Albert M. Chu, Alexander J. Suess
  • Patent number: 10714467
    Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jo Kim, Joong-won Jeon
  • Patent number: 10706198
    Abstract: A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 7, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 10707201
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 7, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 10680024
    Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Huang, Jiech-Fun Lu, Yu-Chun Chen
  • Patent number: 10664015
    Abstract: Disclosed is a foldable display apparatus in which a crack prevention layer is disposed on a surface of a display panel. The crack prevention layer includes thin film pattern portions disposed along a folding axis of the foldable display apparatus.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaihyuk Choi, Sukwon Jung, Myungsoo Huh
  • Patent number: 10650909
    Abstract: The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 12, 2020
    Inventors: Pinhan Chen, Dongcheng Wu
  • Patent number: 10643560
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 5, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10622344
    Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 14, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Jonathan Haigh, Elizabeth Lagnese
  • Patent number: 10605859
    Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Rami Salem, Lesly Zaren V. Endrinal, Hyeokjin Lim, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan, Mickael Malabry
  • Patent number: 10593700
    Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Mukul Gupta, Xiangdong Chen, Ohsang Kwon, Foua Vang, Stanley Seungchul Song, Kern Rim
  • Patent number: 10559585
    Abstract: A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Tae-Hee Lee
  • Patent number: 10541273
    Abstract: A method is provided that includes forming a transistor by forming a gate dielectric layer above a substrate, forming a spacer dielectric layer above the gate dielectric layer, and forming a gate adjacent the gate dielectric layer and above the spacer dielectric layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Seje Takaki
  • Patent number: 10535294
    Abstract: A method and system control an OLED display to achieve desired color points and brightness levels in an array of pixels in which each pixel includes at least three sub-pixels having different colors and at least one white sub-pixel. The method and system select a plurality of reference points in the pixel content domain with known color points and brightness levels. For each set of three sub-pixels of different colors, the method and system determine the share of each sub-pixel to produce the color point and brightness level of each selected reference point, and select the maximum share determined for each sub-pixel as peak brightness needed from that sub-pixel.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 14, 2020
    Assignee: Ignis Innovation Inc.
    Inventors: Allyson Giannikouris, Jaimal Soni, Nino Zahirovic, Ricky Yik Hei Ngan, Gholamreza Chaji
  • Patent number: 10529789
    Abstract: A display device includes a substrate, a first thin-film transistor (TFT), a first organic light-emitting diode (OLED), and a second OLED. The TFT is on a first surface of the substrate and includes a first output electrode and a second output electrode. The OLED is on the first surface of the substrate and is electrically connected to the first output electrode of the TFT. The second OLED is on a second surface of the substrate and is electrically connected to the second output electrode of the TFT.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee Na Kim, Sang Jin Park, Yong Hwan Ryu, Tae Hyeok Choi
  • Patent number: 10497702
    Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Da Yang, Jeffrey Junhao Xu
  • Patent number: 10461193
    Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Gilbert Dewey, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz
  • Patent number: 10453934
    Abstract: Structures and methods are presented for forming a vertical field effect transistors. The structure generally includes a top source/drain including an L-shaped spacer on sidewalls and a portion of the bottom surface of the top source/drain. At least one airgap top spacer is provided adjacent top sidewalls of the fin and between the top source/drain and the gate electrode.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10447272
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 10388238
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 20, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10388767
    Abstract: A fin field effect transistor (FinFET) includes a substrate and a fin having a first height over a surface of the substrate. The fin includes a first portion comprising a first sidewall, wherein the first sidewall is angled with respect to the surface of the substrate at a first angle. The fin further includes a second portion comprising a second sidewall, wherein the second sidewall is angled with respect to the surface of the substrate at a second angle, and the second angle is different from the first angle. The FinFET further includes a gate structure over the fin.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10332896
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 10319647
    Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 11, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10290582
    Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim
  • Patent number: 10276587
    Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 10269801
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Patent number: 10217671
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Thomas Francois
  • Patent number: 10217763
    Abstract: An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 26, 2019
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 10204861
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xuelian Zhu, Jia Zeng, Wenhui Wang, Youngtag Woo, Jongwook Kye
  • Patent number: 10192884
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 29, 2019
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard