Gate Arrays Patents (Class 257/202)
  • Patent number: 10714467
    Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jo Kim, Joong-won Jeon
  • Patent number: 10706198
    Abstract: A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 7, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 10707201
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 7, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 10680024
    Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Huang, Jiech-Fun Lu, Yu-Chun Chen
  • Patent number: 10664015
    Abstract: Disclosed is a foldable display apparatus in which a crack prevention layer is disposed on a surface of a display panel. The crack prevention layer includes thin film pattern portions disposed along a folding axis of the foldable display apparatus.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaihyuk Choi, Sukwon Jung, Myungsoo Huh
  • Patent number: 10650909
    Abstract: The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 12, 2020
    Inventors: Pinhan Chen, Dongcheng Wu
  • Patent number: 10643560
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 5, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10622344
    Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 14, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Jonathan Haigh, Elizabeth Lagnese
  • Patent number: 10605859
    Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Rami Salem, Lesly Zaren V. Endrinal, Hyeokjin Lim, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan, Mickael Malabry
  • Patent number: 10593700
    Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Mukul Gupta, Xiangdong Chen, Ohsang Kwon, Foua Vang, Stanley Seungchul Song, Kern Rim
  • Patent number: 10559585
    Abstract: A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Tae-Hee Lee
  • Patent number: 10541273
    Abstract: A method is provided that includes forming a transistor by forming a gate dielectric layer above a substrate, forming a spacer dielectric layer above the gate dielectric layer, and forming a gate adjacent the gate dielectric layer and above the spacer dielectric layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Seje Takaki
  • Patent number: 10535294
    Abstract: A method and system control an OLED display to achieve desired color points and brightness levels in an array of pixels in which each pixel includes at least three sub-pixels having different colors and at least one white sub-pixel. The method and system select a plurality of reference points in the pixel content domain with known color points and brightness levels. For each set of three sub-pixels of different colors, the method and system determine the share of each sub-pixel to produce the color point and brightness level of each selected reference point, and select the maximum share determined for each sub-pixel as peak brightness needed from that sub-pixel.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 14, 2020
    Assignee: Ignis Innovation Inc.
    Inventors: Allyson Giannikouris, Jaimal Soni, Nino Zahirovic, Ricky Yik Hei Ngan, Gholamreza Chaji
  • Patent number: 10529789
    Abstract: A display device includes a substrate, a first thin-film transistor (TFT), a first organic light-emitting diode (OLED), and a second OLED. The TFT is on a first surface of the substrate and includes a first output electrode and a second output electrode. The OLED is on the first surface of the substrate and is electrically connected to the first output electrode of the TFT. The second OLED is on a second surface of the substrate and is electrically connected to the second output electrode of the TFT.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hee Na Kim, Sang Jin Park, Yong Hwan Ryu, Tae Hyeok Choi
  • Patent number: 10497702
    Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: John Jianhong Zhu, Da Yang, Jeffrey Junhao Xu
  • Patent number: 10461193
    Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Gilbert Dewey, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz
  • Patent number: 10453934
    Abstract: Structures and methods are presented for forming a vertical field effect transistors. The structure generally includes a top source/drain including an L-shaped spacer on sidewalls and a portion of the bottom surface of the top source/drain. At least one airgap top spacer is provided adjacent top sidewalls of the fin and between the top source/drain and the gate electrode.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10447272
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 10388238
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 20, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10388767
    Abstract: A fin field effect transistor (FinFET) includes a substrate and a fin having a first height over a surface of the substrate. The fin includes a first portion comprising a first sidewall, wherein the first sidewall is angled with respect to the surface of the substrate at a first angle. The fin further includes a second portion comprising a second sidewall, wherein the second sidewall is angled with respect to the surface of the substrate at a second angle, and the second angle is different from the first angle. The FinFET further includes a gate structure over the fin.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 20, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 10332896
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 10319647
    Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 11, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10290582
    Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim
  • Patent number: 10276587
    Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 10269801
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Patent number: 10217763
    Abstract: An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 26, 2019
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 10217671
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Thomas Francois
  • Patent number: 10204861
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xuelian Zhu, Jia Zeng, Wenhui Wang, Youngtag Woo, Jongwook Kye
  • Patent number: 10192823
    Abstract: In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihoon Yoon, Shincheol Min, Hyun-Min Choi
  • Patent number: 10192884
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 29, 2019
    Assignee: pSemi Corporation
    Inventor: Simon Edward Willard
  • Patent number: 10192940
    Abstract: The present application discloses a double sided organic light-emitting display apparatus, including: a rigid substrate; a transmission flexible substrate and a reflective flexible substrate formed on the rigid substrate; a display substrate having a plurality of switching elements formed on the transmission flexible substrate and the reflective flexible substrate; and a top-emission OLED light-emitting layer and a bottom-emission OLED light-emitting layer formed on the display substrate, wherein the top-emission OLED light-emitting layer is corresponding to the reflective flexible substrate and the bottom-emission OLED light-emitting layer is corresponding to the transmission flexible substrate. The present application also provides a method of manufacturing the OLED display apparatus. The OLED display apparatus can achieve the double sided display, and because of its use of the flexible substrate, it also has the advantage of ease of carrying and flexible property.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 29, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Jhih-jie Huang, Bo Liang, Wei Wang
  • Patent number: 10177139
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 8, 2019
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 10163925
    Abstract: An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Okamoto, Kiyoshi Okuyama
  • Patent number: 10153306
    Abstract: A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first plurality of drain fingers, and a second FET connected in series with the first FET along a first dimension, the second FET having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tzung-Yin Lee, Aniruddha B. Joshi, David Scott Whitefield, Maureen Rosenberg Brongo
  • Patent number: 10153371
    Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 11, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie
  • Patent number: 10134467
    Abstract: A semiconductor memory is disclosed that includes a first data line, a first coupling line, and a second coupling line. The first coupling line is configured to capacitively couple the first coupling line with the first data line. The second coupling line is configured to capacitively couple the second coupling line with the first data line. The first data line and the first coupling line are formed in a first conductive layer, and the second coupling line is formed in a second conductive layer that is different from the first conductive layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10121896
    Abstract: Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 6, 2018
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Stephen L. Smith, Qiang Lu
  • Patent number: 10102327
    Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 16, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Chetan Bisht, Harry Scrivener, III
  • Patent number: 10103128
    Abstract: A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: May 7, 2017
    Date of Patent: October 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Che-Ya Chou, Kun-Ting Hung, Chia-Hao Yang, Nan-Cheng Chen
  • Patent number: 10083667
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 25, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10078800
    Abstract: A circuit for implementing an artificial neuron comprises: an integrator for an input signal to produce a voltage signal; a signal generator linked to the integrator output producing two output signals when the voltage is at or above a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory comprising two terminals switching from a high to low resistance state in a time following a statistical distribution specific to the memory, a first terminal linked to the output of the integrator; a transistor linked to a branch at zero potential to a second terminal of the resistive memory, controlled by the second output signal such that in the presence of a pulse of voltage the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: September 18, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Manan Suri, Giorgio Palma
  • Patent number: 10050028
    Abstract: An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Chung-Hsing Wang, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Yi-Hsun Chiu, Yuan-Te Hou
  • Patent number: 10050036
    Abstract: Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 14, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Xiaoying Meng
  • Patent number: 10043837
    Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 7, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Philippe Are
  • Patent number: 10001684
    Abstract: The present application discloses an array substrate having a signal line; a common electrode line; an electrostatic discharge (ESD) protector comprising a first discharging terminal coupled to the signal line, and a second discharging terminal coupled to the common electrode line; and an ESD protector repair unit comprising a first repair terminal in close proximity to the first discharging terminal but separated from each other, a second repair terminal in close proximity to the common electrode line but separated from each other.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 19, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cuili Gai, Zhongyuan Wu, Jingwen Yin, Longyan Wang
  • Patent number: 9991161
    Abstract: A method for filling a through hole (TH) located on a substrate is provided. The TH is a continuous channel having an upper rim, a lower rim and an interior surface. In one embodiment, the method comprises steps (a)-(d). In the step (a), a conductive material (CM) is deposited over the substrate to thereby deposit a layer of the CM around the rims and on the interior surface. In the step (b), the deposited CM is etched. In particular, the etching step selectively removes more CM deposited at the rims relative to CM deposited at a mid-section of the interior surface of the channel. In the step (c), the steps (a) and (b) are optionally repeated until the channel is sealed at the mid-section by a bridge formed of CM. In the step (d), the CM is further deposited over the substrate to thereby completely fill the TH.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 5, 2018
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Yaofeng Sun, Sha Xu, Shu Kin Yau
  • Patent number: 9991312
    Abstract: An electroluminescence display device and manufacturing method thereof are provided. An electroluminescence display device includes a pixel, having: an electroluminescence diode, a driving transistor configured to supply a current to the electroluminescence diode, and a switching transistor configured to switch a signal supplied to the driving transistor, wherein a size of a channel area of the driving transistor is different from a size of a channel area of the switching transistor, and wherein a taper angle deviation of the channel areas of the driving transistor and the switching transistor is less than or equal to 10°.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 5, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: JungChul Kim, JunYoung Kwon
  • Patent number: 9966277
    Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: May 8, 2018
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Andre Schmenn, Damian Sojka, Isabella Goetz, Gudrun Stranzl, Sebastian Werner, Thomas Fischer, Carsten Ahrens, Edward Fuergut
  • Patent number: 9947679
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukuo Owada, Masaaki Shinohara, Takahiro Maruyama