Gate Arrays Patents (Class 257/202)
  • Patent number: 11423856
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 23, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 11417588
    Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Ren Chen, Chih-Liang Chen, Wei-Ling Chang, Hui-Zhong Zhuang, Li-Chun Tien
  • Patent number: 11374004
    Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Anh Phan, Gilbert Dewey, Willy Rachmady, Stephen M. Cea, Sayed Hasan, Kerryann M. Foley, Patrick Morrow, Colin D. Landon, Ehren Mannebach
  • Patent number: 11329047
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Patent number: 11322199
    Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 11302770
    Abstract: The present disclosure provides an array substrate, a display panel, and a manufacturing method of the array substrate. The array substrate includes a substrate layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, an interlayer insulating layer, an organic filling layer, and a third metal layer being stacked together. The meshed second metal layer is disposed in the display area, and a double-layer power voltage trace structure in the display area is formed by connecting the first via holes and power voltage signal lines of the third metal layer.
    Type: Grant
    Filed: October 12, 2019
    Date of Patent: April 12, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Cheng Chen, Yun Yu
  • Patent number: 11302633
    Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Duk Su Chun
  • Patent number: 11289564
    Abstract: A double-sided display panel and a method for manufacturing the same are provided. The double-sided display panel includes: a first substrate; a second substrate opposite to first substrate; a first display unit between the first substrate and the second substrate, the first display unit including a first luminescent layer and a first reflective layer which is closer to the second substrate than the first luminescent layer, wherein at least a part of light emitted from the first luminescent layer is reflected by the first reflective layer and emitted out through the first substrate; and a second display unit between the first substrate and second substrate, including a second luminescent layer, wherein light emitted from the second luminescent layer is emitted out through the second substrate. The first display unit includes a transparent electrode and a conductive contact layer which electrically connects the transparent electrode with the first reflective layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 29, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 11264435
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 1, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Byong-Hoo Kim, Min-Joo Kim, Eun-Pyo Hong, Jae-Won Lee, Sang-Hoon Pak, Sang-Hyuk Won, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Patent number: 11217565
    Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: January 4, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11189704
    Abstract: The present disclosure proposes a thin film transistor and a related circuit. The thin film includes a gate, a drain and a source. The gate includes one or more gate units. The gate unit includes two or more strip-shaped gate branches, and a first gap is arranged between the two adjacent strip-shaped gate branches to separate them.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 30, 2021
    Assignee: TCL CHINA STAR OPTOFI FCTRONICS TECHNOLOGY CO.. LTD.
    Inventor: Hui Xia
  • Patent number: 11189729
    Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 30, 2021
    Assignee: Tessera, Inc.
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • Patent number: 11152303
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu, Chun-Yi Lee
  • Patent number: 11152290
    Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 19, 2021
    Assignee: Intel Corporatuon
    Inventors: Benjamin Chu-Kung, Van H. Le, Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros, Ashish Agrawal, Seung Hoon Sung
  • Patent number: 11145678
    Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jack Liu, Jiann-Tyng Tzeng, Chih-Liang Chen, Chew-Yuen Young, Sing-Kai Huang, Ching-Fang Huang
  • Patent number: 11133255
    Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 11094090
    Abstract: Some embodiments provide a novel compressive-sensing image capture device and a method of using data captured by the compressive-sensing image capture device. The novel compressive-sensing image capture device includes an array of sensors for detecting electromagnetic radiation. Each sensor in the sensor array has an associated mask that blocks electromagnetic radiation from portions of the sensor. In some embodiments, a diffractive mask is used to direct incoming light from a same object to different sensors in a sensing array. Some embodiments of the invention provide a dynamic mask array. In some embodiments, a novel machine trained network is provided that processes image capture data captured by the compressive-sensing image capture device to predict solutions to problems.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 17, 2021
    Assignee: PERCEIVE CORPORATION
    Inventor: Ilyas Mohammed
  • Patent number: 11049467
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 11018157
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11011545
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 11004923
    Abstract: Disclosed is a display device that is capable of being driven with low power consumption. A first thin-film transistor including a polycrystalline semiconductor layer and a second thin-film transistor including an oxide semiconductor layer are disposed in an active area, thereby reducing power consumption. At least one opening formed in a bending area is formed to have the same depth as any one of contact holes formed in the active area, thereby making it possible to form the opening and the contact holes through the same process and consequently simplifying the process of manufacturing the device. Since a high potential supply line and a low potential supply line overlap each other with a protective film formed of an inorganic insulation material interposed therebetween, short-circuiting of the high potential supply line and the low potential supply line may be prevented.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 11, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung-Nam Lim, Yu-Ho Jung, Dong-Young Kim
  • Patent number: 10998327
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Bin Kang, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Patent number: 10998176
    Abstract: The present embodiment relates to an ion detector provided with a structure for suppressing degradation over time in an electron multiplication mechanism in a multi-mode ion detector. The ion detector includes a dynode unit, a first electron detection portion including a semiconductor detector having an electron multiplication function, a second electron detection portion including an electrode, and a gate part. The first and second electron detection portions are capable of ion detection at different multiplication factors. The gate part includes at least a final-stage dynode as a gate electrode, and controls switching between passage and interruption of secondary electrons which are directed toward the first electron detection portion by adjusting a set potential of the gate electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 4, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi Kobayashi, Takeshi Endo, Hiroki Moriya, Toshinari Mochizuki
  • Patent number: 10998241
    Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. Khaderbad, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10916190
    Abstract: A driving circuit, a display panel, and a display device are provided. The display panel comprises a plurality of common electrodes; a plurality of phototransistors, two or more phototransistors among the plurality of phototransistors being disposed in an area corresponding to each of the plurality of common electrodes; a plurality of photo-control lines electrically connected to a gate electrode of at least one phototransistor among the plurality of phototransistors; a plurality of photo-driving lines electrically connected to a first electrode of at least one phototransistor among the plurality of phototransistors, and a plurality of read-out lines, each of the plurality of read-out lines being electrically connected to a single common electrode among the plurality of common electrodes, and electrically connected to second electrodes of all of the phototransistors disposed in the area corresponding to the single common electrode to which each of the plurality of read-out lines are electrically connected.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 9, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HyunGon Kim, DukKeun Yoo
  • Patent number: 10896912
    Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Patent number: 10886273
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 10872935
    Abstract: Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byong-Hoo Kim, Min-Joo Kim, Eun-Pyo Hong, Jae-Won Lee, Sang-Hoon Pak, Sang-Hyuk Won, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
  • Patent number: 10867102
    Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 10868199
    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10846458
    Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shun Li Chen, Li-Chun Tien, Ting Yu Chen, Wei-Ling Chang
  • Patent number: 10817637
    Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Naya Ha, Yong-Durk Kim, Bong-hyun Lee, Hyung-ock Kim, Kwang-ok Jeong, Jae-hoon Kim
  • Patent number: 10812288
    Abstract: A communication system capable of shortening a setting time of an ID and reducing an incorrect setting is provided. A master device, when receiving an ID assignment request from a writing device, turns on all a plurality of semiconductor relays, and after a predetermined time has elapsed, turns all off, sequentially turns on the semiconductor relays and each time turning on the semiconductor relays, sends the corresponding ID. The plurality of slave devices, when receiving the ID assignment request from the writing device after supplying power, stores the fact in the ID request area, waits for a reception of the ID from the master device without confirming reception of the ID assignment request, and sets the ID as its own ID if determining that the ID assignment request has already been received by the ID request area after power is supplied.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 20, 2020
    Assignee: YAZAKI CORPORATION
    Inventor: Yoshihide Nakamura
  • Patent number: 10811375
    Abstract: An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Arm Limited
    Inventors: Kishan Chanumolu, Vijaya Kumar Vinukonda
  • Patent number: 10804225
    Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10777673
    Abstract: A high electron mobility transistor (HEMT) gallium nitride (GaN) bidirectional blocking device includes a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 15, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: David Sheridan
  • Patent number: 10755017
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Laura R. Darden, Albert M. Chu, Alexander J. Suess
  • Patent number: 10714467
    Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jo Kim, Joong-won Jeon
  • Patent number: 10707201
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 7, 2020
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 10706198
    Abstract: A method for synthesizing a circuit layout, characterized by the following features: primary circuit functions are placed on the circuit layout; secondary circuit functions are placed on the circuit layout; at least one first mask is generated in such a way that the first mask reproduces the primary circuit functions and covers the secondary circuit functions when a semiconductor substrate is structured according to the circuit layout by way of the first mask; and the placement of the circuit functions takes place in such a way that at least one changed mask reproduces the primary circuit functions and the secondary circuit functions when the semiconductor substrate is structured according to the circuit layout by way of at least one second mask.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 7, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 10680024
    Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Huang, Jiech-Fun Lu, Yu-Chun Chen
  • Patent number: 10664015
    Abstract: Disclosed is a foldable display apparatus in which a crack prevention layer is disposed on a surface of a display panel. The crack prevention layer includes thin film pattern portions disposed along a folding axis of the foldable display apparatus.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaihyuk Choi, Sukwon Jung, Myungsoo Huh
  • Patent number: 10650909
    Abstract: The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 12, 2020
    Inventors: Pinhan Chen, Dongcheng Wu
  • Patent number: 10643560
    Abstract: An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 5, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yohsuke Fujikawa
  • Patent number: 10622344
    Abstract: The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 14, 2020
    Assignee: PDF SOLUTIONS, INC.
    Inventors: Jonathan Haigh, Elizabeth Lagnese
  • Patent number: 10605859
    Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Rami Salem, Lesly Zaren V. Endrinal, Hyeokjin Lim, Hadi Bunnalim, Robert Kim, Lavakumar Ranganathan, Mickael Malabry
  • Patent number: 10593700
    Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Mukul Gupta, Xiangdong Chen, Ohsang Kwon, Foua Vang, Stanley Seungchul Song, Kern Rim
  • Patent number: 10559585
    Abstract: A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Tae-Hee Lee
  • Patent number: 10541273
    Abstract: A method is provided that includes forming a transistor by forming a gate dielectric layer above a substrate, forming a spacer dielectric layer above the gate dielectric layer, and forming a gate adjacent the gate dielectric layer and above the spacer dielectric layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Seje Takaki
  • Patent number: 10535294
    Abstract: A method and system control an OLED display to achieve desired color points and brightness levels in an array of pixels in which each pixel includes at least three sub-pixels having different colors and at least one white sub-pixel. The method and system select a plurality of reference points in the pixel content domain with known color points and brightness levels. For each set of three sub-pixels of different colors, the method and system determine the share of each sub-pixel to produce the color point and brightness level of each selected reference point, and select the maximum share determined for each sub-pixel as peak brightness needed from that sub-pixel.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 14, 2020
    Assignee: Ignis Innovation Inc.
    Inventors: Allyson Giannikouris, Jaimal Soni, Nino Zahirovic, Ricky Yik Hei Ngan, Gholamreza Chaji