With Particular Power Supply Distribution Means Patents (Class 257/207)
  • Patent number: 10700281
    Abstract: The present disclosure discloses a resistive random access memory (RRAM) and a method for manufacture the RRAM. The method includes: providing a bottom interconnection layer; forming a bottom dielectric layer above the bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the bottom interconnection layer; and forming a bottom electrode layer in the via, the bottom electrode layer including a first electrode selectively grown above the bottom interconnection layer. The bottom electrode layer manufactured in such a way provides improved filling capability of the bottom electrode layer in the via.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 30, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Changzhou Wang, Jiquan Liu
  • Patent number: 10677657
    Abstract: Systems and methods are directed to contacts for an infrared detector. For example, an infrared imaging device includes a substrate having a first metal layer and an infrared detector array coupled to the substrate via a plurality of contacts. Each contact includes for an embodiment a plurality of metal studs each having a first end and a second end and each disposed between the first metal layer and a second metal layer, wherein the first end of each metal stud is disposed on a portion of the first metal layer that is at least partially on the surface of the substrate.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 9, 2020
    Assignee: FLIR SYSTEMS, INC.
    Inventors: Eric A. Kurth, Patrick Franklin
  • Patent number: 10664639
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10643912
    Abstract: Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Scott K. Pozder, Eng Chye Chua
  • Patent number: 10600476
    Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Zheng Guo, Clifford L. Ong, Eric A. Karl
  • Patent number: 10534258
    Abstract: A method for semiconductor structure design includes performing, by a processor, error processing of an initial design file layout. The processor further detects a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the T2T structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 10527932
    Abstract: An apparatus including a memory storing instructions and a processor executing the instructions to perform a method including: performing error processing of an initial design file layout; detecting a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules; retargeting the Vx for generating a resulting design file layout of the semiconductor structure; and generating a physical semiconductor structure based on the resulting design file layout of the semiconductor structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 10510774
    Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 17, 2019
    Assignee: IMEC vzw
    Inventors: Peter Debacker, Praveen Raghavan, Vassilios Constantinos Gerousis
  • Patent number: 10453781
    Abstract: A semiconductor device comprises a plurality of first conductor portions 10, a plurality of second conductor portions 20 and a sealing portion 50, covering upper surfaces of the first conductor portion 10 and the second conductor portion 20. The first conductor portion 10 and the second conductor portion 20 are connected. Usage mode of the first terminal 11 and the second terminal 12 can be selected, and the second terminal 21 of the second conductor portion 20 serves as an output terminal in a case where the first terminal 11 of the first conductor portion 10 is used as a power supply terminal, and the first terminal 11 of the first conductor portion 10 serves as an output terminal in a case where the second terminal 21 is used as a power supply terminal.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 22, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 10418244
    Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Giridhar Nallapati, Periannan Chidambaram
  • Patent number: 10410917
    Abstract: An electronic design automation method configured to automatically design a semiconductor device includes generating a site-row having a unit height based on a standard cell having the unit height, and generating metal routing tracks which begin at an offset point spaced a specific distance from an origin point of the site-row. The unit height is a non-integer multiple of a spacing of metal lines of one of interconnection layers of the semiconductor device. Using this process, a layout of a plurality of standard cells on a plurality of site-rows, and constituting a Floorplan of the semiconductor device, is generated.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-San Cha, Dongkyu Youn
  • Patent number: 10380307
    Abstract: A method for designing an semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Silicon Technologies, Inc.
    Inventors: Thomas L. Wolf, Kent F. Smith, Tracy L. Johancsik, Kyler C. Fillerup, Thomas G. Wolf
  • Patent number: 10380315
    Abstract: An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Zhong Zhuang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen
  • Patent number: 10374001
    Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Swarnal Borthakur, Marc Sulfridge
  • Patent number: 10325849
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu, Chun-Yi Lee
  • Patent number: 10304792
    Abstract: A packaged Integrated Circuit (IC) includes an IC and a package. The package has a bottom dielectric layer and a plurality of redistribution layers (RDLs) formed on the bottom dielectric layer. Each the RDLs includes patterned conductors, a dielectric layer, and a plurality of vias that extend between the patterned conductors to a differing RDL or to external connections. The package includes a plurality of package pads that have a first lateral separation pitch. The IC includes a plurality of IC pads that electrically connect to the plurality of package pads that have a first lateral separation pitch. The package also includes a plurality of Printed Circuit Board (PCB) pads that extend through the bottom dielectric layer and contact the plurality of patterned conductors of the first RDL. Power PCB pads and ground PCB pads of the plurality of PCB pads have a second lateral separation pitch that exceeds the first lateral separation pitch.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 28, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Shiqun Gu, Hongying Zhang, HongLiang Cai
  • Patent number: 10304771
    Abstract: Some embodiments include an apparatus having first, second, third and fourth wiring tracks. The first and third wiring tracks sandwich the second wiring track therebetween, and the second and fourth wiring tracks sandwich the third wiring track therebetween. A lower-level wiring layer includes a first wiring which has a first portion extending along the second wiring track, a second portion extending along the first wiring track, and a third portion extending along the third wiring track. An upper-level wiring layer includes a second wiring electrically connected to the first wiring and having a fourth portion extending along the third wiring track. The third portion of the first wiring is coupled with the fourth portion of the second wiring.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Sato, Ryota Suzuki
  • Patent number: 10290639
    Abstract: A method of forming a VNW SRAM device with a vertical cross-couple/PD/PU contact landed on a PD/PU gate and a bottom nRX and pRX interface and the resulting device are provided. Embodiments include forming a first and a second bottom nRX and pRX over an NW upon a p-sub, the pRX formed between the nRX; forming fins over the first nRX, the first pRX, the second pRX, and over the second nRX; forming a first GAA perpendicular to and over the second pRX and nRX, a second GAA perpendicular to and over the first nRX and pRX, a third GAA perpendicular to and over a portion the first nRX, and a fourth GAA perpendicular to and over a portion of the second nRX; and forming a first and a second metal gate contact on the first GAA, nRX, and pRX and on the second GAA, pRX, and nRX, respectively.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Hui Zang
  • Patent number: 10277227
    Abstract: A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Shun-Li Chen
  • Patent number: 10216886
    Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 26, 2019
    Assignee: MegaChips Corporation
    Inventor: Daiki Moteki
  • Patent number: 10204883
    Abstract: A semiconductor device includes a semiconductor die, an insulative layer, a conductive feature and a shield. The insulative layer surrounds the semiconductor die, and the insulative layer has a first surface and a second surface opposite to each other. The conductive feature is extended from the first surface to be proximal to the second surface of the insulative layer, and the conductive feature has a first end exposed by the first surface of the insulative layer. The shield covers the first surface of the insulative layer and is grounded through the first end of the conductive feature exposed by the first surface of the insulative layer.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMIDONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 10186510
    Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 22, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10170404
    Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin
  • Patent number: 10134450
    Abstract: A semiconductor memory device includes a peripheral circuit including first and second circuit blocks that are respectively disposed in second and third regions adjacent to each other in a first direction with a first region interposed therebetween, first power lines disposed in a first metal layer and connected to the first unit circuit block, second power lines disposed in the first metal layer and connected to the second unit circuit block, and bridge power lines disposed in a second metal layer in the first region and extending in a second direction intersecting with the first direction. The first power lines extend from the second region to the first region and are meshed with the bridge power lines. The second power lines extend from the third region to the first region and are meshed the bridge power lines.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventor: Nam-Hea Jang
  • Patent number: 10121747
    Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Keisuke Nakayama
  • Patent number: 10074640
    Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 10074576
    Abstract: A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided. The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 10062646
    Abstract: A semiconductor integrated circuit comprising: a first macro cell including a first power line in a first wiring layer; a second macro cell adjacent to the first macro cell, the second macro cell including a second power line in the first wiring layer; a first connection part in the first wiring layer, the first connection part electrically connecting the first power line with the second power line; and a third power line in a second wiring layer different from the first wiring layer, the third power line electrically connected to the first power line; wherein the second power line is electrically connected to the third power line through the first connection part.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hun Heo
  • Patent number: 10048742
    Abstract: The present invention provides an integrated circuit. The integrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: August 14, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chih-Ching Lin, Yi-Ping Kao, Chun-Sung Su
  • Patent number: 10002832
    Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 19, 2018
    Assignee: Socionext, Inc.
    Inventors: Tooru Matsui, Masahiro Yoshimura
  • Patent number: 9911856
    Abstract: One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or ?30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Hideyuki Kishida, Junichiro Sakata
  • Patent number: 9900005
    Abstract: A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chi-Yeh Yu, Ho Che Yu
  • Patent number: 9886544
    Abstract: A method includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Jen Hsieh, Kai-Ming Liu
  • Patent number: 9885951
    Abstract: A method for structure design including detecting, by a processor, a tip-to-tip (T2T) structure design violation for a metal layer above (Ma) a via (Vx) at a tip of the Ma for a design file layout for the structure. Upon detection of the T2T structure design violation, retargeting, by the processor, of the Vx based on adjusting of both the Ma and a metal layer (Mb) below the Vx that connects the Ma through the Vx for the design file layout of the structure to improve performance of the structure based on fixing metal tip or metal ending across cell boundaries.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Geng Han, Dongbing Shao
  • Patent number: 9872397
    Abstract: The present disclosure provides techniques for creating a symmetrical ball grid array pattern for an integrated circuit package. The ball grid array includes a symmetrical pattern of circuit connection points, wherein the symmetrical pattern is derived from a base hexagonal pattern that is repeated in at least one or more sections of the ball grid array.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventor: Gary Brist
  • Patent number: 9865732
    Abstract: An integrated circuit includes a gate electrode and spacers along sidewalls of the gate electrode. The integrated circuit further includes a source/drain (S/D) region adjacent to the gate electrode. The S/D region includes a diffusion barrier structure at least partially in a recess of the substrate. The diffusion barrier structure includes an epitaxial layer having a first region and a second region. The first region is thinner than the second region, and the first region is misaligned with respect to the sidewalls of the gate electrode. The S/D region includes a doped silicon-containing structure over the diffusion barrier structure. The first region of the diffusion barrier structure is configured to partially prevent dopants of the doped silicon-containing structure from diffusing into the substrate. The second region of the diffusion barrier structure is configured to substantially completely prevent the dopants of the doped silicon-containing structure from diffusing into the substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Su-Hao Liu, Chien-Tai Chan, King-Yuen Wong, Chien-Chang Su
  • Patent number: 9842848
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 9812396
    Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason Eugene Stephens, Guillaume Bouche, Shreesh Narasimha, Patrick Ryan Justison, Byoung Youp Kim, Craig Michael Child, Jr.
  • Patent number: 9793211
    Abstract: The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect layer having a lower metal wire extending in a first direction. A second metal interconnect layer has a plurality of connection pins coupled to the lower metal wire by way of a first via layer and extending over the lower metal wire in a second direction perpendicular to the first direction. A third metal interconnect layer has an upper metal wire extending over the lower metal wire and the connection pins in the first direction. The upper metal wire is coupled to the connection pins by way of a second via layer arranged over the first via layer. Connecting the connection pins to the lower and upper metal wires reduces current density in connections to the connection pins, thereby reducing electromigration and/or IR issues.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Yung-Sung Yen
  • Patent number: 9793192
    Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 9786685
    Abstract: A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hoijin Lee
  • Patent number: 9786663
    Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Seid Hadi Rasouli, Animesh Datta, Ohsang Kwon
  • Patent number: 9780082
    Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seong Lee, Dae-Young Moon, Min-Su Kim
  • Patent number: 9768226
    Abstract: A solid-state imaging device includes: a first electrode formed above a semiconductor substrate; a photoelectric conversion film formed on the first electrode and for converting light into signal charges; a second electrode formed on the photoelectric conversion film; a charge accumulation region electrically connected to the first electrode and for accumulating the signal charges converted from the light by the photoelectric conversion film; a reset gate electrode for resetting the charge accumulation region; an amplification transistor for amplifying the signal charges accumulated in the charge accumulation region; and a contact plug in direct contact with the charge accumulation region, comprising a semiconductor material, and for electrically connecting to each other the first electrode and the charge accumulation region.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 19, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Sakata, Mitsuyoshi Mori, Yutaka Hirose, Hiroshi Masuda, Hitoshi Kuriyama, Ryohei Miyagawa
  • Patent number: 9767243
    Abstract: A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien
  • Patent number: 9740092
    Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ayman Hamouda
  • Patent number: 9741724
    Abstract: An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Seshadri, Steve Prins, Russell McMullan
  • Patent number: 9710588
    Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9679887
    Abstract: A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is electrically coupled to a drain/source end of the second transistor.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tien-Chien Huang
  • Patent number: 9679805
    Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Mark A. Zaleski