Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.

Abstract: The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving the characteristics of a film formed on a substrate. The method of manufacturing a semiconductor device may include: (a) forming a first film containing a predetermined element, oxygen, carbon and nitrogen on a substrate; and (b) forming a second film thinner than the first film on a top surface of the first film, the second film having an oxygen concentration lower than an oxygen concentration of the first film or having oxygen and carbon concentrations lower than oxygen and carbon concentrations of the first film.

Abstract: Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.

Abstract: Processing methods comprising selectively orthogonally growing a first material through a mask to provide an expanded first material are described. The mask can be removed leaving the expanded first material extending orthogonally from the surface of the first material. Further processing can create a self-aligned via.

Abstract: A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other.

Abstract: A color filter layer and a light transmissive layer have a groove between a first color filter and a second color filter and between a first light transmissive portion and a second light transmissive portion. The groove contains a member located at least between the first color filter and the second color filter. The member has a refractive index higher than 1.0.

Abstract: A process of forming a HEMT that makes the contact resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050° C. and growing an AlN spacer layer with a flow rate of NH3 at most 10% smaller than a summed flow rate of NH3 and H2. The grown GaN channel layer includes a substantial density of threading dislocations and the grown AlN layer includes a substantial density of pits.

Abstract: An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.

Abstract: Processing methods comprising selectively orthogonally growing a first material through a mask to provide an expanded first material are described. The mask can be removed leaving the expanded first material extending orthogonally from the surface of the first material. Further processing can create a self-aligned via.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.

Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: A nonvolatile semiconductor storage device includes a word line, a first electrode, a high resistance ion diffusion layer, a second electrode, and a bit line. The word line is made of a conductive material extending in a first direction. The first electrode is provided on the word line. The high resistance ion diffusion layer is provided on the first electrode. The second electrode is provided on the ion diffusion layer and configured to supply a metal into the ion diffusion layer upon application of a positive voltage relative to the first electrode. The bit line is provided on the second electrode and made of a conductive material extending in a second direction orthogonal to the first direction. The ion diffusion layer contains oxygen at a higher concentration on the word line side than on the bit line side.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.

Abstract: A two-color detector includes a first absorber layer. The first absorber layer exhibits a first valence band energy characterized by a first valence band energy function. A barrier layer adjoins the first absorber layer at a first interface. The barrier layer exhibits a second valence band energy characterized by a second valence band energy function. The barrier layer also adjoins a second absorber layer at a second interface. The second absorber layer exhibits a third valence band energy characterized by a third valence band energy function. The first and second valence band energy functions are substantially functionally or physically continuous at the first interface and the second and third valence band energy functions are substantially functionally or physically continuous at the second interface.

Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.

Abstract: A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body.

Abstract: A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.

Abstract: Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.

Abstract: A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.

Abstract: An image pickup device includes a plurality of first electrodes, a second electrode, a third electrode, a photoelectric conversion layer, a plurality of signal reading portions, at least one of electric potential adjusting portions. The plurality of first electrodes is arranged on an upper side of a substrate in two dimensions with a predetermined gap interposed between one of the first electrodes and another first electrode adjacent to the one of the first electrode. The second electrode is arranged next to the first electrodes arranged on an outermost side of the first electrodes with the predetermined gap interposed between the first electrodes arranged on the outermost side and the second electrode. The third electrode faces both of the plurality of first electrodes and the second electrode. The photoelectric conversion layer is disposed between the plurality of first electrodes and the second electrode and the third electrode.

Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.

Abstract: A light-emitter includes a first electrode and a layered body over the first electrode. The layered body includes a charge injection layer and a light-emitting layer. A bank defines a position of the light-emitting layer of the layered body, and a second electrode is over the layered body. The charge injection layer is formed by oxidation of an upper portion of a metal. The first electrode includes a metal layer that is a lower portion of the metal. An inner portion of the charge injection layer is depressed to define a recess. A portion of the bank is on an outer portion of the charge injection layer.

Abstract: A simulation of a multiplication process includes tracing histories of a plurality of carriers, increasing a weight factor of a carrier to simulate a multiplication of the carrier, and summing the number of the plurality of carriers. Each of the plurality of carriers is multiplied by its respective weight factor.

Abstract: A solid-state imaging device that includes: a pixel array section configured by an array of a unit pixel, including an optoelectronic conversion section that subjects an incoming light to optoelectronic conversion and stores therein a signal charge, a transfer transistor that transfers the signal charge stored in the optoelectronic conversion section, a charge-voltage conversion section that converts the signal charge provided by the transfer transistor into a signal voltage, and a reset transistor that resets a potential of the charge-voltage conversion section; and voltage setting means for setting a voltage of a well of the charge-voltage conversion section to be negative.

Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

Abstract: A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.

Abstract: A solid-state imaging device capable of securing sufficient sensitivity and obtaining favorable characteristics is provided. The solid-state imaging device includes a charge-transfer portion 2 provided on one side of each column of light-receiving sensor portions 1, each forming a pixel, arranged in the form of a matrix and a transfer electrode of the charge-transfer portion 2 including a first transfer electrode formed of first electrode layers 3A and 3C and a second transfer electrode formed by electrically connecting first electrode layers 3B and 3D and a second electrode layer 4; the first electrode layers 3B and 3D in the second transfer electrode are independently formed in each of the charge-transfer portion 2; and the first transfer electrodes 3A and 3C and the second electrode layer 4 are laminated in a portion between pixels adjacent to each other in the direction of the charge-transfer portions 2.

Abstract: A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.

Abstract: Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device and a manufacturing method thereof that can reduce RC delay within the semiconductor device. Embodiments provide a semiconductor device including: a first interlayer dielectric layer formed over the a semiconductor substrate, a first metal wire and a second metal wire formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first and second metal wires, and a phase change material layer formed between the first and second metal wires.

Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.

Abstract: In some embodiments, the present invention is directed to processes for the combination of injecting charge in a material electrochemically via non-faradaic (double-layer) charging, and retaining this charge and associated desirable properties changes when the electrolyte is removed. The present invention is also directed to compositions and applications using material property changes that are induced electrochemically by double-layer charging and retained during subsequent electrolyte removal. In some embodiments, the present invention provides reversible processes for electrochemically injecting charge into material that is not in direct contact with an electrolyte. Additionally, in some embodiments, the present invention is directed to devices and other material applications that use properties changes resulting from reversible electrochemical charge injection in the absence of an electrolyte.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a first pixel having a first photodiode and a first readout circuit and a second pixel having a second photodiode and a second readout circuit. The second pixel is aligned at one side of the first pixel, and a light receiving area of the first photodiode is different from a light receiving area of the second photodiode.

Abstract: A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed.

Abstract: A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

Abstract: A back irradiating type solid state imaging device comprises: a first semiconductor substrate; a plurality of photoelectric converting devices that receives a light incident from a back side of the first semiconductor substrate and are formed in a two-dimensional array on a surface side of the first semiconductor substrate; a CCD type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices; and a MOS type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices.

Abstract: Disclosed is a CMOS image sensor including a gate electrode of a finger type transfer transistor for controlling the saturation state of a floating diffusion region according to the luminance level (i.e. low luminance or high luminance). The CMOS image sensor includes first and second photodiode regions for generating electrons in response to incident light, and a transfer transistor positioned between the first and second photodiodes for receiving the generated electrons transferred from the first and/or second photodiode.

Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Abstract: A phase change memory (PCM) device includes a substrate, bottom electrodes disposed in the substrate, a first dielectric layer disposed on the substrate, second dielectric layers, third dielectric layers, cup-shaped thermal electrodes, top electrodes, and PC material spacers. In the PCM device, each cup-shaped thermal electrode contacts with each bottom electrode. Second and third dielectric layers are disposed over the substrate in different directions, wherein each of the second and third dielectric layers covers a portion of the area surrounded by each cup-shaped thermal electrode, and the third dielectric layers overlay the second dielectric layers. The top electrodes are disposed on the third dielectric layers, wherein a plurality of stacked structure composed of the third dielectric layers and the top electrodes are formed thereon.

Abstract: A miniaturized floating gate (FG) MOSFET radiation sensor system is disclosed, The sensor preferably comprises a matched pair of sensor and reference FGMOSFETs wherein the sensor FGMOSFET has a larger area floating gate with an extension over a field oxide layer, for accumulation of charge and increased sensitivity. Elimination of a conventional control gate and injector gate reduces capacitance, and increases sensitivity, and allows for fabrication using standard low cost CMOS technology. A sensor system may be provided with integrated signal processing electronics, for monitoring a change in differential channel current ID, indicative of radiation dose, and an integrated negative bias generator for automatic pre-charging from a low voltage power source. Optionally, the system may be coupled to a wireless transmitter. A compact wireless sensor System on Package solution is presented, suitable for dosimetry for radiotherapy or other biomedical applications.

Abstract: A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.

Abstract: In a method of fabricating a phase change memory (PCM) device, a substrate having bottom electrodes formed therein is provided. A first dielectric layer having cup-shaped thermal electrodes is formed over the substrate. Second dielectric layers are formed on the substrate. Stacked structures are formed on the substrate. A PC material film is formed over the substrate and covers the stacked structures and the second dielectric layers. The PC material film is anisotropically etched to form PC material spacers on sidewalls of the stacked structures, and each of the PC material spacers physically and electrically contacts each of the cup-shaped thermal electrodes and top electrodes. The PC material spacers include phase change material. The PC material spacers are over-etched to remove the PC material film on the sidewalls of the second dielectric layers.

Abstract: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.