Abstract: A charge or carrier injection transistor including a substrate, a gate electrode and an electric potential barrier layer forming an electric potential barrier against charges (either holes or electrons) injected by the gate electrode towards the substrate. A source and a drain are formed in the substrate on opposite sides of the gate electrode. A conduction channel, between the source and the drain, is formed on the substrate by charges passing through the electric potential barrier by a voltage applied to the gate electrode. When the applied voltage is removed, this channel disappears. That is, the transistor is ON when the charges from the gate electrode pass through the electric potential barrier and is OFF when no charges pass through it, thereby the charges perform a transistor switching function.

Abstract: A device for producing an output voltage which is proportional to an applied magnetic field. The device includes a plurality charge injection regions, a corresponding plurality of charge exit regions, and a charge transfer region. The charge transfer region includes gate electrodes which serve to propagate at least one isolated charge packet across the charge transfer region in a predetermined direction from the charge input region to the charge output region. The charge packet is subject to the applied magnetic field which is perpendicular to the charge transfer region so as to induce a resultant potential that is orthogonal to both the applied magnetic field and the predetermined direction. Furthermore, the resultant potential effects a lateral redistribution of charge carriers in the packet. A recirculation configuration allows for a recycling of the packet from the output region back to the input region in order to accommodate a continuation of the redistribution of charge carriers.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

Abstract: In an array of charge injection device (CID) detectors, integer amplification is incorporated into each respective detector of the array. The amplifier for each CID detector in the array performs multiple nondestructive readouts. This provides a gain of N amplification of the signal charge in that detector wherein the signal charge is accurately replicated in a separate charge storage well defined by a magnitude capacitor coupled to the detector. Thus, at the end of the readout process, this separate well contains charge equal to N times the signal charge, N being the number of nondestructive readout cycles in the readout process.

Abstract: An analog MOS transistor device allows the user to set the threshold characteristics of the device. This transistor device is fabricated using conventional CMOS fabrication materials and methods. An insulated gate spans across a source junction, a drain junction, and a control junction. This gate can be charged or discharged to a desired voltage level by injecting or removing charge at the insulated gate. The insulated gate has no conductor connection, and is only capacitively coupled to the source junction, drain junction and control junction. The user sets the voltage on the insulated gate, then varies the voltage impressed on the control junction as the application requires. The user can set the channel conductivity characteristics of the device by setting the charge level on the insulated gate, and by varying the voltage on the control junction, both of which may be dynamically adjusted in-circuit.

Abstract: Monolithic InSb array devices are described for staring infrared imaging systems operating in the 3-5 .mu.m spectral region. These devices are fabricated with only 4 mask levels compared to 5 mask levels for prior devices and have higher output dynamic ranges and greater wafer yield compared to previous designs. The devices are fabricated to include a substrate (15) having a field oxide (16) pattern thereon. A first gate oxide (17) is deposited over the field oxide with columns (21) patterned on the first gate oxide. A second gate oxide (19) is next deposited with rows (22) patterned on the second gate oxide. The devices can further include a passivation layer (29) deposited on the rows (22).