Channel Confinement Patents (Class 257/243)
  • Patent number: 10848690
    Abstract: Imaging apparatus (1300, 1400, 1500) includes a semiconductor substrate (1302), which includes at least first and second sensing areas (1306, 1308, 1502, 1514) with a predefined separation between the sensing areas. First and second arrays of pixel circuits (1312) are formed respectively on the first and second sensing areas and define respective first and second matrices of pixels. First and second photosensitive films (1314, 1316, 1402) are disposed respectively over the first and second arrays of pixel circuits, and are configured to output photocharge to the pixel circuits in response to radiation incident on the apparatus in different, respective first and second spectral bands.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 24, 2020
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Naveen Kolli, Emanuele Mandelli, Nicola Galante
  • Patent number: 10313622
    Abstract: A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 4, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Yung-Ho Alex Chuang, Jingjing Zhang, Sharon Zamek, John Fielden, Devis Contarato, David L. Brown
  • Patent number: 9401472
    Abstract: Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 26, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Chakravarthy Gopalan, Antonio R. Gallo, Yi Ma
  • Patent number: 9362271
    Abstract: A capacitive device includes a substrate, a well structure buried in the substrate, a first stacked layer that includes a first dielectric layer and a first conductive layer, a cap dielectric layer, and a first electrode. The well has a predetermined doping type. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench between the first and second shoulder portions. The first trench has sidewalls and a bottom surface. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: June 7, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yen Chou, Po-Ken Lin, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 9054171
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Patent number: 8969190
    Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Joachim Patzer
  • Patent number: 8946777
    Abstract: High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: February 3, 2015
    Assignee: Cree, Inc.
    Inventors: Adam William Saxler, Scott Sheppard, Richard Peter Smith
  • Patent number: 8835994
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8809925
    Abstract: An image sensor pixel includes a photosensitive element, a floating diffusion (“FD”) region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is disposed in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: August 19, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Hsin-Chih Tai, Duli Mao, Zhenhong Fu
  • Patent number: 8785981
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8703558
    Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 22, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qingqing Liang, Zhi Jin, Wenwu Wang, Huicai Zhong, Xinyu Liu, Huilong Zhu
  • Patent number: 8697487
    Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: April 15, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai
  • Patent number: 8466498
    Abstract: In a solid state imaging device with an electron multiplying function, in a section normal to an electron transfer direction of a multiplication register EM, an insulating layer 2 is thicker at both side portions than in a central region. A pair of overflow drains 1N is formed at a boundary between a central region and both side portions of an N-type semiconductor region 1C. Each overflow drain 1N extends along the electron transfer direction of the multiplication register EM. Overflow gate electrodes G extend from the thin portion to the thick portion of the insulating layer 2. The overflow gate electrodes G are disposed between both ends of each transfer electrode 8 in a longitudinal direction and the insulating layer 2, and they also function as shield electrodes for each electrode 8 (8A and 8B).
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: June 18, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hisanori Suzuki, Yasuhito Yoneta, Shin-ichiro Takagi, Kentaro Maeta, Masaharu Muramatsu
  • Patent number: 8436350
    Abstract: In forming a thin film transistor, an oxide semiconductor layer is used and a cluster containing a titanium compound whose electrical conductance is higher than that of the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hideyuki Kishida
  • Patent number: 8330156
    Abstract: In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata
  • Patent number: 8329521
    Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company. Ltd.
    Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Sheng-Chen Chung, Kai-Shyang You, Jin-Aun Ng, Wei Cheng Wu, Ming Zhu
  • Patent number: 8309997
    Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 13, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
  • Patent number: 8203151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 19, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8148749
    Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: April 3, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Mark Rinehimer, Joseph Yedinak, Dean E. Probst, Gary Dolny, John Benjamin
  • Patent number: 8115237
    Abstract: A solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, and a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion. The solid-state image pickup element also includes a first-conductive type high-concentration impurity-doped element isolation region, a second-conductive type photoelectric conversion region, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 14, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8039889
    Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Weon-Ho Park
  • Patent number: 8030687
    Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alberto Escobar, Brian J. Greene, Edward J. Nowak
  • Patent number: 7994552
    Abstract: An object of the present invention is to provide a photoelectric conversion device, wherein improvement of charge transfer properties when charge is output from a charge storage region and suppression of dark current generation during charge storage are compatible with each other. This object is achieved by forming a depletion voltage of a charge storage region in the range from zero to one half of a power source voltage (V), forming a gate voltage of a transfer MOS transistor during a charge transfer period in the range from one half of the power source voltage to the power source voltage (V) and forming a gate voltage of the transfer MOS transistor during a charge storage period in the range from minus one half of the power source voltage to zero (V).
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 9, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Seiichi Tamura, Ryuichi Mishima
  • Patent number: 7956388
    Abstract: It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a light-receiving area. The solid-state image pickup element comprises a p-type planar semiconductor, a hole formed in the p-type planar semiconductor, a p+-type region formed in a bottom of the hole, a p+-type isolation region formed in a part of a sidewall of the hole and connected to the p+-type region, an n-type photoelectric conversion region formed beneath the p+-type region, a transfer electrode formed on the entire sidewall of the hole through a gate dielectric film, a CCD channel region formed in a top of the p-type planar semiconductor, and a read channel formed in a region of the p-type planar semiconductor between the n-type photoelectric conversion region and the CCD channel region.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: June 7, 2011
    Assignee: Unisantis Electronics (Japan) Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 7851205
    Abstract: A DNA sensor including a p-channel field-effect transistor having as a gate an electrolyte solution and having as a channel a diamond surface which contains a mixture of at least a hydrogen-terminated surface and a surface terminated by an amino group or a molecule with an amino group as an amino termination; a probe DNA constituted of a single-stranded DNA with known nucleotide sequence which is directly immobilized by a linker to the amino termination of the diamond surface; and a target DNA constituted of an unknown single-stranded DNA which is dropped on said diamond surface, wherein the hybridization of the target and probe is ascertained by detecting a shift of the threshold voltage of said p-channel field effect transistor toward positive direction which is due to increase in hole density of the p-channel resulting from doubling the negative electric charge of the phosphate groups upon hybridization.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: December 14, 2010
    Assignee: Japan Science and Technology Agency
    Inventor: Hiroshi Kawarada
  • Patent number: 7821043
    Abstract: An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper surface of the n-type base layer; an n-type source layer provided in part of an upper surface of the p-type base layer; a trench extending through the n-type source layer and the p-type base layer to the n-type base layer; a gate electrode provided in the trench; and a gate insulating film provided between the gate electrode and an inner surface of the trench. The p-type emitter layer has a thickness of 5 to 50 ?m and a dopant concentration of 2×1016 to 1×1018 cm?3.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akio Nakagawa
  • Patent number: 7709859
    Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Cree, Inc.
    Inventors: Richard Peter Smith, Adam William Saxler, Scott T. Sheppard
  • Patent number: 7619675
    Abstract: A solid-state image pickup apparatus includes one or a plurality of photoelectric converting sections for photoelectric converting incident light into a signal charge on a semiconductor substrate, and a vertical charge-transferring section for charge-transferring the signal charge photoelectric converted at the photoelectric converting section, in which the vertical charge-transferring section is located under the photoelectric converting section on the side of the semiconductor substrate.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: November 17, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shinji Horii
  • Patent number: 7592654
    Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 22, 2009
    Assignee: Aptina Imaging Corporation
    Inventors: Sandeep R. Bahl, Fredrick P. LaMaster, David W. Bigelow
  • Patent number: 7511320
    Abstract: The invention is directed to an improvement of reliability in a chip-size package type semiconductor device and a manufacturing method thereof. A semiconductor substrate formed with a pad electrode is prepared, and a first protection layer formed of epoxy resin is formed on a front surface of the semiconductor substrate. Then, a via hole is formed from a back surface of the semiconductor substrate to the pad electrode. A wiring layer is then formed from the via hole of the semiconductor substrate, being electrically connected with the pad electrode through the via hole. Then, a second protection layer and a conductive terminal are formed, and the semiconductor substrate is separated into individual semiconductor dies by dicing.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: March 31, 2009
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
    Inventor: Isao Ochiai
  • Patent number: 7471326
    Abstract: A solid-state imaging device can improve a detection sensitivity of a signal detecting means by decreasing a parasitic capacity of a horizontal signal line. In a solid-state imaging device in which a plurality of pixels are arranged in a matrix fashion, a pixel signal is flowed through a horizontal switch (39) to a horizontal signal line (40) as a signal charge, and a signal is outputted by a signal detecting means connected to the end off the horizontal signal line (40), an insulating gate-type field-effect transistor comprising the horizontal switch (39) includes channels extended at least in two directions between its source electrode connected to the horizontal signal line (40) and other drain electrode.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: December 30, 2008
    Assignee: Sony Corporation
    Inventor: Kazuya Yonemoto
  • Patent number: 7368769
    Abstract: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within the active region to cross the active region. A gate insulating layer is disposed to cover sidewalls and a bottom of the channel trench region. The MOS transistor has a gate pattern that fills the channel trench region and crosses above the active region. A portion of the sidewall of the gate pattern is recessed at an upper corner of the channel trench region and has a width smaller than the width of the top of the gate pattern and smaller than the width of the channel trench region.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Choel Paik
  • Patent number: 7294875
    Abstract: A programmable structure and device and methods of forming and using the structure and device are disclosed. The structure includes a soluble electrode, an ion conductor, and an inert electrode. Upon application of a sufficient voltage, a conductive region forms within or on the ion conductor and between the electrodes. The presence or absence of the conductive region can be used to store information in memory devices.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: November 13, 2007
    Assignee: Axon Technologies Corporation
    Inventor: Michael N. Kozicki
  • Patent number: 7084441
    Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 1, 2006
    Assignee: Cree, Inc.
    Inventor: Adam William Saxler
  • Patent number: 7038276
    Abstract: A thin-film transistor (TFT) with body contacts is disclosed. It is used in polysilicon TFT LCD's. A body contact region for separating the gate electrode, a source region, and a drain region is made in the TFT. Through the dopants in the body contact region and different impurities in the source region and the drain region, a body-trigger bias is imposed on the body of the TFT. This method reduces the threshold voltage of the TFT driving circuit, thereby increasing the driving current.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 2, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Ming-Dou Ker, Wen-Hsia Kung, Ya-Hsiang Tai
  • Patent number: 7005761
    Abstract: A circuit configuration is used for off-load switching. The circuit configuration can be used as a component in a switch mode power supply, a clocked supply, a voltage regulator, and a lamp switch, wherein the circuit configuration is embodied as an IGBT, especially a field stop IGBT or alternately and additionally as a PT IGBT. A method for using the circuit configuration include three operating modes: in a first operating mode, power for a load is modulated by pulse modulation; in a second operating mode, the power is modulated by changing a switching-on time; and, in a third operating mode, both are implemented.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: February 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Holger Huesken, Thomas Laska
  • Patent number: 6888182
    Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Mitani, Yasumori Fukushima
  • Patent number: 6873362
    Abstract: A solid-state imaging device can improve a detection sensitivity of a signal detecting means by decreasing a parasitic capacity of a horizontal signal line. In a solid-state imaging device in which a plurality of pixels are arranged in a matrix fashion, a pixel signal is flowed through a horizontal switch (39) to a horizontal signal line (40) as a signal charge, and a signal is outputted by a signal detecting means connected to the end off the horizontal signal line (40), an insulating gate-type field-effect transistor comprising the horizontal switch (39) includes channels extended at least in two directions between its source electrode connected to the horizontal signal line (40) and other drain electrode.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: March 29, 2005
    Assignee: Sony Corporation
    Inventor: Kazuya Yonemoto
  • Patent number: 6847066
    Abstract: A thin film passive element includes at least one of a capacitance element having a plurality of conductive layers and a dielectric material layer and an inductance element formed of a patterned conductive layer is stacked on a circuit element-forming region of a semiconductor substrate provided with a plurality of connection pads and is connected to the circuit element of the circuit element-forming region.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: January 25, 2005
    Assignees: Oki Electric Industry Co., Ltd., Casio Computer Co., Ltd.
    Inventors: Iwao Tahara, Ichiro Mihara, Yutaka Aoki
  • Patent number: 6830984
    Abstract: Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: December 14, 2004
    Assignee: LSI Logic Corporation
    Inventors: Richard T. Schultz, Peter J. Wright
  • Patent number: 6831350
    Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: December 14, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chun-Li Liu, Alexander L. Barr, John M. Grant, Bich-Yen Nguyen, Marius K. Orlowski, Tab A. Stephens, Ted R. White, Shawn G. Thomas
  • Patent number: 6777726
    Abstract: In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends away from a semiconductor body and forms a body region. A filling insulator surrounds the semiconductor pillar and is situated on the semiconductor body for insulating the MOSFET.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: August 17, 2004
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Publication number: 20040135176
    Abstract: A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 15, 2004
    Inventor: Ji-young Kim
  • Patent number: 6727559
    Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: April 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Masahiro Uekawa, Koichi Hirata, Mikito Sakakibara
  • Patent number: 6661043
    Abstract: A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 9, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Ching Huang, Wen-Cheng Chen, Wen-Chuan Chiang, Kuo-Chuang Tseng
  • Patent number: 6597024
    Abstract: A charge coupled device has a hydrogen diffusion path to diffuse hydrogen to a silicon surface. The hydrogen diffusion path extends through a top silicon oxide layer that itself extends through a first aperture in a top silicon nitride layer. The first aperture overlays a conductor formed of polycrystalline silicon at a location that transversely overlays a channel stop. The hydrogen diffusion path extends through the conductor and through an extension of the conductor that itself extends through a second aperture in a lower silicon nitride layer. The lower silicon nitride layer being one part of a gate dielectric film. The gate dielectric film also includes a lower silicon oxide layer disposed between the lower silicon nitride layer and the silicon surface. The hydrogen diffusion path extends through the lower silicon oxide layer to reach the silicon surface.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: July 22, 2003
    Assignee: Dalsa Corporation
    Inventors: Hermanus Leonardus Peek, Joris Pieter Valentijn Maas, Daniel Wihelmus Elisabeth Verbugt
  • Publication number: 20030127667
    Abstract: The invention is regarding to solid-state imaging device.
    Type: Application
    Filed: November 5, 2002
    Publication date: July 10, 2003
    Inventors: Ikuko Inoue, Hirofumi Yamashita, Hidetoshi Nozaki
  • Patent number: 6545304
    Abstract: In production of a solid-state image pickup device including a semiconductor substrate, a photoelectric converter element group including a plurality of photoelectric converter elements formed in one column in one surface of the semiconductor substrate, a charge transfer path to transfer signal charge accumulated in the photoelectric converter elements, and readout gates to read signal charge from photoelectric converter elements to feed the charge to the charge transfer path, an ON or ONO film electrically insulates each transfer electrode constituting the charge transfer path from the semiconductor substrate and an oxide insulating film insulates a readout gate electrode constituting the readout gate from the semiconductor substrate to thereby improve electric characteristics of the solid-state image pickup device.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: April 8, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Eiichi Okamoto
  • Patent number: RE40409
    Abstract: A photoelectric converter with improved charge transfer efficiency from a light receiving portion. The photoelectric converter includes a light receiving portion having an output end and a gate portion having a first side and a second side that both define a readout gate width for the light receiving portion, where the first side of the gate portion confronts the output end of the light receiving portion. The photoelectric converter also includes a charge transfer portion formed to confront the second side of the gate portion, where the readout gate width of said gate portion is wider at the first side confronting said light receiving portion than at the second side confronting said charge transfer portion.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: July 1, 2008
    Assignee: Sony Corporation
    Inventors: Satoshi Kitayama, Kazushige Nigawara, Tsuyoshi Sasaki