Abstract: A semiconductor device includes a main switching circuit implemented by a first semiconductor element and a second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type provided in an upper portion of the common region, the first semiconductor element being provided with a first source region of the first conductivity type in an upper portion of the first well region, the second semiconductor element being provided with a second source region of the first conductivity type in an upper portion of the second well region; and a drive circuit configured to independently apply a first drive signal and a second drive signal respectively to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element.

Abstract: The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric. A spacer is disposed along an upper surface of the substrate. The spacer extends along a first gate sidewall closer to the drain region, crosses over an upper edge of the gate electrode, and further extends laterally to cover a portion of an upper surface of the gate electrode. A field plate including a polysilicon thin film is disposed along upper and sidewall surfaces of the spacer so that the polysilicon thin film is separated from the gate electrode and the substrate by the spacer. The thin polysilicon film field plate improves the breakdown voltage of the transistor device.

Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.

Abstract: High aspect ratio trace circuits and methods of manufacture and use are provided herein. A method may include obtaining a substrate, the substrate having a reservoir for receiving a conductive ink and a plurality of trace voids that are arranged in a pattern, the plurality of trace voids each having a path of fluid connection to the reservoir, filling the reservoir with a conductive ink, placing a cover film over the plurality of trace voids, allowing the conductive ink to fill the plurality of trace voids via capillary action to create a plurality of conductive traces, and allowing the conductive ink in the plurality of conductive traces to dry.

Abstract: An electronic component manufacturing method that efficiently grinds a cover layer provided on a substrate even when the substrate is warped includes the step of forming first grooves at intervals in a cover layer provided on a substrate by repeating grinding with a rotary blade at a pitch more than a thickness W of the rotary blade. Next, at least portions provided in the cover layer along the first grooves are removed to reduce the thickness of the cover layer by repeating grinding at a pitch equal to or less than the thickness W of the rotary blade.

Abstract: A charge-coupled unit formed in a semiconductor substrate and including an array of identical electrodes forming rows and columns, wherein: each electrode extends in a cavity with insulated walls formed of a groove, oriented along a row, dug into the substrate thickness, and including, at one of its ends, a protrusion extending towards at least one adjacent row.

Abstract: A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

Abstract: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.

Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Abstract: Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.

Abstract: A solid-state imaging device is provided, which includes a pixel region in which pixels including a photoelectric conversion section and a plurality of pixel transistors are arranged. In the solid-state imaging device, a transfer transistor of the pixel transistors includes: a transfer gate electrode extended in a surface of the substrate formed on the surface of a semiconductor substrate; and a transfer gate electrode buried in the substrate which is electrically insulated from the transfer gate electrode extended in a surface of the substrate and is embedded in the inside of the semiconductor substrate in the vertical direction through the transfer gate electrode extended in a surface of the substrate.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A recess gate transistor includes: a drain region and a source region in a semiconductor substrate and doped with first-type impurities; a recess region recessed in the semiconductor substrate between the drain region and the source region; a gate insulation layer on the recess region, a gate electrode on the gate insulation layer filling the recess region; and a charge pocket region below the recess region and doped with second-type impurities. A semiconductor chip includes a plurality of recess gate transistors, and an image sensor includes a semiconductor chip including a plurality of recess gate transistors.

Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.

Abstract: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

Abstract: A solid-state imaging device is provided, which includes a pixel region in which pixels including a photoelectric conversion section and a plurality of pixel transistors are arranged. In the solid-state imaging device, a transfer transistor of the pixel transistors includes: a transfer gate electrode extended in a surface of the substrate formed on the surface of a semiconductor substrate; and a transfer gate electrode buried in the substrate which is electrically insulated from the transfer gate electrode extended in a surface of the substrate and is embedded in the inside of the semiconductor substrate in the vertical direction through the transfer gate electrode extended in a surface of the substrate.

Abstract: Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.

Abstract: Provided is a semiconductor device which can reduce on-resistance by improving hole mobility of a channel region. A trench gate type MOSFET (semiconductor device) is provided with a p+-type silicon substrate whose crystal plane of a main surface is a (110) plane; an epitaxial layer formed on the silicon substrate; a trench, which is formed on the epitaxial layer and includes a side wall parallel to the thickness direction (Z direction) of the silicon substrate; a gate electrode formed inside the trench through a gate dielectric film; an n-type channel region formed along the side wall of the trench; and a p+-type source region and a p?-type drain region which are formed to sandwich the channel region in the thickness direction (Z direction) of the silicon substrate. The trench is formed to have the crystal plane of the side wall as a (110) plane.

Abstract: A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.

Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Abstract: A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer.

Abstract: A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.

Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.

Abstract: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

Abstract: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Abstract: A trench structure and a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

Abstract: A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device.

Abstract: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the bottom surface of the trench lies in the buried layer, an insulating layer lines the side surfaces of the trenches, and the semiconductor material within the trench overlies the insulating layer and contacts the buried layer at the bottom surface of the trench.

Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row.

Abstract: A charge-coupled unit formed in a semiconductor substrate and including an array of identical electrodes forming rows and columns, wherein: each electrode extends in a cavity with insulated walls formed of a groove, oriented along a row, dug into the substrate thickness, and including, at one of its ends, a protrusion extending towards at least one adjacent row.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill.

Abstract: A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater.

Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.