With Profiled Channel Dopant Concentration Or Profiled Gate Region Dopant Concentration (e.g., Maximum Dopant Concentration Below Surface) Patents (Class 257/285)
  • Patent number: 11682702
    Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: June 20, 2023
    Assignee: FLOSFIA Inc.
    Inventors: Toshimi Hitora, Masaya Oda, Akio Takatsuka
  • Patent number: 11569267
    Abstract: A method for forming an integrated circuit includes following operations. A substrate having a first region, a second region and an isolation structure is received. A portion of the substrate is removed such that the second region is recessed. A portion of the isolation structure is removed to obtain a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over the first top surface, the second top surface and the boundary. A dielectric structure is formed over the substrate. A top surface of the first device, a top surface of the second device and a top surface of the dummy structure are aligned with each other.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 11430839
    Abstract: A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jongjun Baek, Jaewoo Jeong, Byungsoo So
  • Patent number: 10879240
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Yi-Min Huang, Shahaji B. More, Tsung-Lin Lee
  • Patent number: 10840388
    Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10636961
    Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a memory region. The memory region comprises a bottom via, a recap layer on the BV, a bottom electrode on the recap layer, a magnetic tunneling junction layer on the bottom electrode, and a top electrode on the MTJ layer. The material of the recap layer is different from that of the BV.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Hsia-Wei Chen, Hung Cho Wang, Kuei-Hung Shen
  • Patent number: 10276655
    Abstract: A semiconductor device includes a plurality of compensation regions of a first conductivity type arranged in a semiconductor substrate. The semiconductor device further includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement. The drift region has a second conductivity type. The drift region portions and the compensation regions are arranged alternatingly. At least portions of a border of a depletion region occurring in a static blocking state of the vertical electrical element arrangement are located within the drift region portions at a depth of less than a depth of at least a subset of the compensation regions.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Armin Willmeroth
  • Patent number: 10256325
    Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Gamerith, Markus Schmitt, Winfried Kaindl, Gerald Sölkner
  • Patent number: 10050105
    Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Tatsuya Naito, Isamu Sugai
  • Patent number: 9899405
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: February 20, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Young Jae Kim, Seung Woo Choi, Yong Min Yoo
  • Patent number: 9722092
    Abstract: To provide a transistor with favorable electrical characteristics. A semiconductor device includes a first insulator over a substrate; a first metal oxide over the first insulator; a second metal oxide over the first metal oxide; a first conductor and a second conductor over the second metal oxide; a third metal oxide over the second metal oxide, the first conductor, and the second conductor; a second insulator over the third metal oxide; and a third conductor over the second insulator. The second metal oxide includes a region in contact with a top surface of the first metal oxide and regions in contact with side surfaces of the first metal oxide. The second metal oxide includes channel formation regions.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 9722045
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 1, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
  • Patent number: 9508869
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9490248
    Abstract: A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Jin Yeh, Chewn-Pu Jou, Jun-De Jin
  • Patent number: 9269713
    Abstract: A power semiconductor device comprises a first substrate that is highly doped with a first dopant type, the first substrate having a front face and a back face, the back face forming a backside of the device, a vertical p-type FET and a vertical n-type FET provided laterally adjacent to each other on the front face of the first substrate, wherein one of the FETs has a first drift zone with a complementary doping to the first dopant of the first substrate, and wherein the p-type FET and the n-type FET share the first substrate as a common backside, and wherein a region between the first drift zone and the first substrate comprises a highly conductive structure providing a low ohmic connection between the first drift zone and the first substrate. Further, a method for producing such a device is provided.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Irsigler, Franz Hirler, Hans-Joachim Schulze
  • Publication number: 20150137192
    Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer.
    Type: Application
    Filed: June 10, 2013
    Publication date: May 21, 2015
    Inventor: Guangtao Han
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 9012964
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 8975671
    Abstract: A semiconductor component is provided with a semiconductor substrate, in the upper face of which an active region made of a material of a first conductivity type is introduced by ion implantation. A semiconducting channel region having a defined length and width is designed within the active region. Each of the ends of the channel region located in the longitudinal extension is followed by a contacting region made of a semiconductor material of a second conductivity type. The channel region is covered by an ion implantation masking material, which comprises transverse edges defining the length of the channel region and longitudinal edges defining the width of the channel region and which comprises an edge recess at each of the opposing transverse edges aligned with the longitudinal extension ends of the channel region, the contacting regions that adjoin the channel region extending all the way into said edge recess.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: March 10, 2015
    Assignee: ELMOS Semiconductor AG
    Inventor: Arnd Ten Have
  • Patent number: 8865027
    Abstract: A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: October 21, 2014
    Assignee: Cambrios Technologies Corporation
    Inventors: Jonathan S. Alden, Haixia Dai, Michael R. Knapp, Shuo Na, Hash Pakbaz, Florian Pschenitzka, Xina Quan, Michael A. Spaid, Adrian Winoto, Jeffrey Wolk
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8823130
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20140231884
    Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Publication number: 20140139282
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Patent number: 8710549
    Abstract: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science
    Inventors: Xiaolu Huang, Jing Chen, Xi Wang, Deyuan Xiao
  • Patent number: 8643068
    Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Stefan Decker, Norbert Krischke, Christoph Kadow
  • Patent number: 8618583
    Abstract: The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Panglijen Candra, Richard A. Phelps, Robert M. Rassel, Yun Shi
  • Patent number: 8614467
    Abstract: A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: December 24, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8536627
    Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 8530943
    Abstract: The semiconductor device includes: a substrate 2 and a drift layer 3a, which are made of a wide-bandgap semiconductor; a p-type well 4a and a first n-type doped region 5, which are defined in the drift layer; a source electrode 5, which is electrically connected to the first n-type doped region 5; a second n-type doped region 30 arranged between its own well 4a and an adjacent unit cell's well 4a; a gate insulating film 7b, which covers at least partially the first and second n-type doped regions and the well 4a; a gate electrode 8 arranged on the gate insulating film; and a third n-type doped region 31, which is arranged adjacent to the second n-type doped region so as to cover one of the vertices of the unit cell and which has a dopant concentration that is higher than the drift layer and lower than the second n-type doped region.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Kenya Yamashita, Chiaki Kudou
  • Patent number: 8513676
    Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than ?3° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm?3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Toru Hiyoshi, Keiji Wada, Takeyoshi Masuda
  • Patent number: 8502281
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 8436398
    Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: May 7, 2013
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Guang Y. Zhao, Jianjun Cao
  • Patent number: 8431972
    Abstract: An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: April 30, 2013
    Assignee: Infineon Technologies AG
    Inventors: David Alvarez, Richard Lindsay, Manfred Eller, Cornelius Christian Russ
  • Patent number: 8390077
    Abstract: A semiconductor device includes a semiconductor substrate having a first portion and a second portion and a first transistor of a first type formed in the first portion of the substrate, the first transistor being operable at a first voltage, and the first transistor including a doped channel region of a second type opposite of the first type. The semiconductor device also includes a second transistor of the second type formed in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage, the second transistor including an extended doped feature of the second type. Further, the semiconductor device includes a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jan Sonsky, Anco Heringa
  • Patent number: 8338219
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 25, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8330232
    Abstract: A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell; a drain region in the substrate, a portion of the drain region being under the second side of the multi-bit charge-trapping cell; and a channel region in the substrate between the source region and the drain region. The channel region has one of a p-type doping and an n-type doping, and the doping is configured to provide a highest doping concentration near the central portion of the channel region.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 11, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shao Hong Ku, Yin Jen Chen, Wenpin Lu, Tahui Wang
  • Patent number: 8264019
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics S.r.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8264016
    Abstract: A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventor: Rudolf Elpelt
  • Publication number: 20120217551
    Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Paul Malachy Daly, Andrew David Bain, Derek Frederick Bowers, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, Bernard Patrick Stenson, William Allan Lane
  • Publication number: 20120211806
    Abstract: A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.
    Type: Application
    Filed: February 22, 2011
    Publication date: August 23, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Wolfgang Werner
  • Publication number: 20120104468
    Abstract: Fabricating high voltage transistors includes forming a buried p-type implant on a p-substrate for each transistor, the transistor having a source side and a drain side, wherein the p-type implant is positioned adjacent the source and is configured to extend under a gate region; depositing a low doping epitaxial layer on the p-substrate and the p-type implant for each high voltage transistor, the low doping epitaxial layer extending from the source to the drain; forming an N-Well in the low doping epitaxial layer for each transistor, wherein the N-Well corresponds to a low voltage transistor N-Well fabricated using a low voltage transistor fabrication process; and forming a p-top diffusion region in or on the N-Well for each transistor, wherein the p-top diffusion region is configured to compensate for a dopant concentration of the N-Well at or near a surface of the N-Well opposing the substrate.
    Type: Application
    Filed: September 19, 2011
    Publication date: May 3, 2012
    Applicant: O2MICRO, INC.
    Inventors: Yanjun Li, Sen Zhang
  • Patent number: 8159008
    Abstract: Trench-generated transistor structures, methods for fabricating transistors using a trench defined in a semiconductor-on-insulator (SOI) wafer, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of the SOI wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8134142
    Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: March 13, 2012
    Assignee: NXP B.V.
    Inventors: Godefridus Hurkx, Prabhat Agarwal
  • Publication number: 20120037924
    Abstract: A junction field-effect transistor (20) comprises an n-type semiconductor layer (1) having a channel region, a buffer layer (3) formed on the channel region and a p+ region (4a, 4b) formed on the buffer layer (3). The concentration of electrons in the buffer layer (3) is lower than the concentration of electrons in the semiconductor layer (1). The concentration of electrons in the buffer layer (3) is preferably not more than one tenth of the concentration of electrons in the semiconductor layer (1). Thus, the threshold voltage can be easily controlled, and saturation current density of a channel can be easily controlled.
    Type: Application
    Filed: October 26, 2011
    Publication date: February 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kazuhiro Fujikawa, Shin Harada
  • Patent number: 8105925
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8071481
    Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Wei Kao, Shiang-Bau Wang, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku
  • Patent number: 8063419
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: November 22, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 7968921
    Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 7968919
    Abstract: A charge compensation component having a drift path between two electrodes, an electrode and a counterelectrode, and methods for producing the same. The drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type with respect to the first conduction type. A drift path layer doping comprising the volume integral of the doping locations of a horizontal drift path layer of the vertically extending drift path including the drift zone regions and charge compensation zone regions arranged in the drift path layer is greater in the vicinity of the electrodes than in the direction of the center of the drift path.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 28, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Anton Mauder, Stefan Sedlmaier