Junction Field Effect Transistor (unipolar Transistor) Patents (Class 257/256)
  • Patent number: 10269658
    Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Mingo Liu
  • Patent number: 10217930
    Abstract: A method of manufacture for an acoustic resonator device. The method can include forming a topside metal electrode overlying a piezoelectric substrate with a piezoelectric layer and a seed substrate. A topside micro-trench can be formed within the piezoelectric layer and a topside metal can be formed overlying the topside micro-trench. This topside metal can include a topside metal plug formed within the topside micro-trench. A first backside trench can be formed underlying the topside metal electrode, and a second backside trench can be formed underlying the topside micro-trench. A backside metal electrode can be formed within the first backside trench, while a backside metal plug can be formed within the second backside trench and electrically coupled to the topside metal plug and the backside metal electrode. The topside micro-trench, the topside metal plug, the second backside trench, and the backside metal plug form a micro-via.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 26, 2019
    Assignee: AKOUSTIS, INC.
    Inventors: Alexander Y. Feldman, Mark D. Boomgarden, Michael P. Lewis, Jeffrey B. Shealy, Ramakrishna Vetury
  • Patent number: 10115822
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods/structures may include forming a source/drain region in a substrate of a device, and forming an alloy in the source/drain region, wherein the alloy comprises a material that decreases a band gap between source/drain contacts and the source/drain regions to substantially zero. The embodiments herein reduce an external parasitic resistance of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Roza Kotlyar, Kelin Kuhn
  • Patent number: 10103226
    Abstract: A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Vega, Emre Alptekin, Hung H. Tran, Xiaobin Yuan
  • Patent number: 10090356
    Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 2, 2018
    Assignee: Princeton Infrared Technologies, Inc.
    Inventor: Martin H. Ettenberg
  • Patent number: 10079294
    Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 18, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexei Sadovnikov, Doug Weiser, Mattias Erik Dahlstrom, Joel Martin Halbert
  • Patent number: 10068825
    Abstract: A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the semiconductor substrate and having an opening, and an electrode formed in the opening on the front surface of the semiconductor substrate; and a first protective film disposed to cover the semiconductor element. The insulating film has a thickness of not less than 1/500 of a thickness of the semiconductor substrate and not more than 4 ?m. The insulating film has a compressive stress per film thickness of not less than 100 MPa/?m.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsu Negishi, Mamoru Terai, Kei Yamamoto
  • Patent number: 10032584
    Abstract: This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 24, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Anup Bhalla
  • Patent number: 9935151
    Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Charge is transferred form the detector using a junction field effect transistor (JFET) in each pixel. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 3, 2018
    Assignee: Princeton Infrared Technologies, Inc.
    Inventor: Martin H. Ettenberg
  • Patent number: 9929283
    Abstract: A semiconductor device includes a semiconductor substrate, a first well region, and a second well region. The semiconductor substrate has a first conductivity type. The first and second well regions are disposed in the semiconductor substrate. The first and second well regions have a second conductivity type that is opposite to the first conductivity type. The semiconductor device also includes a first top layer and a second top layer. The first top layer is disposed in the semiconductor substrate. The first top layer extends from the first well region to the second well region. The first top layer has the first conductivity type. The second top layer is disposed in the semiconductor substrate and on the first top layer. The second top layer extends from the first well region to the second well region. The second top layer has the second conductivity type.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 27, 2018
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Manoj Kumar, Wen-Hsin Lin, Shin-Cheng Lin, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 9859377
    Abstract: A method for manufacturing an isolation structure integrated with semiconductor device includes following steps. A substrate is provided. A plurality of trenched gates is formed in the substrate. A first insulating layer and a second insulating layer are sequentially deposited on the substrate. A first etching process is performed to remove portions of the second insulating layer to expose portions of the first insulating layer. A second etching process is then performed to remove the exposed second insulating layer to expose the trenched gates and to define at least an active region.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hong-Ze Lin, Chien-Ming Huang, Shin-Kuang Lin
  • Patent number: 9859400
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: January 2, 2018
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 9846503
    Abstract: The touch driver circuit comprises a photosensor module, a data writing module, a driver module, and a control module. The data writing module transmits a scan signal at a scan signal terminal to the driver module under the control of the scan signal terminal. When the scan signal drives the driver module to turn on, the driver module outputs a touch sensing signal to the control module; the touch sensing signal decreases with the increase of an intensity of light irradiated on the photosensor module. Under the control of the control signal, the control module outputs the touch sensing signal output by the driver module to the touch signal sensing terminal, thereby realizing the touch sensing function.
    Type: Grant
    Filed: December 14, 2013
    Date of Patent: December 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Leisen Nie, Xiaojing Qi, Quanguo Zhou
  • Patent number: 9799573
    Abstract: A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: October 24, 2017
    Inventor: Wallace W Lin
  • Patent number: 9722073
    Abstract: A lateral superjunction MOSFET device includes a gate structure and a first column connected to the lateral superjunction structure. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the lateral superjunction MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 1, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 9673323
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Patent number: 9660108
    Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker-Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 9653516
    Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic w
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: May 16, 2017
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shu-Hsiao Tsai, Re Ching Lin, Pei-Chun Liao, Cheng-Kuo Lin, Yung-Chung Chin
  • Patent number: 9653618
    Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 16, 2017
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Zhongda Li
  • Patent number: 9647083
    Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Schloegl, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Hans-Joachim Schulze, Christoph Weiss
  • Patent number: 9577058
    Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Cem Basceri, Thomas Gehrke
  • Patent number: 9577117
    Abstract: A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n+-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 21, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 9536938
    Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: January 3, 2017
    Assignee: Altera Corporation
    Inventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
  • Patent number: 9525081
    Abstract: A method of forming bifacial solar cell structure is described. The method comprises: performing boron diffusion on an upper surface of a semiconductor substrate to form a P+ region and a boron silicon glass (BSG) layer on the P+ region; stripping the BSG layer to expose the P+ region and stripping a blocking layer on a lower surface of the semiconductor substrate simultaneously; forming a first anti-reflection coating layer on the P+ region; forming sacrifice film on the first anti-reflection coating layer; performing phosphorus diffusion on the lower surface to form an N+ region and a phosphorus silicon glass (PSG) layer on the N+ region; stripping the PSG layer on the N+ region to expose the N+ region and stripping the sacrifice film on the first anti-reflection coating layer simultaneously; and forming a second anti-reflection coating layer on the N+ region.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 20, 2016
    Assignee: INVENTEC SOLAR ENERGY CORPORATION
    Inventors: Yu-Hsiang Huang, Yu Ta Cheng, Chuan Chi Chen, Chia-Lung Lin, Chin-Pao Taso, Jung-Wu Chien, Haw Yen
  • Patent number: 9508785
    Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 29, 2016
    Assignee: Altera Corporation
    Inventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzales
  • Patent number: 9472684
    Abstract: A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 18, 2016
    Assignee: Avogy, Inc.
    Inventors: Hui Nie, Andrew Edwards, Isik Kizilyalli, Dave Bour, Thomas R. Prunty
  • Patent number: 9373570
    Abstract: A semiconductor module includes: a semiconductor element; first and second main current passages for energizing the semiconductor element, the first and second main current passages being opposed to each other in such a manner that a first energization direction of the first main current passage is opposite to a second energization direction of the second main current passage, or an angle between the first energization direction and the second energization direction is an obtuse angle; and a coil unit sandwiched between the first and second main current passages. The coil unit includes a coil, which generates an induced electromotive force when a magnetic flux interlinks with the coil, the magnetic flux being generated when current flows through the first and second main current passages.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: June 21, 2016
    Assignee: DENSO CORPORATION
    Inventors: Hideki Kawahara, Takanori Imazawa
  • Patent number: 9349668
    Abstract: A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to coat the semiconductor layer; and an electrode provided to have electrical conductivity and configured to form a Schottky junction with the semiconductor layer. The protective film includes: a first layer made of Al2O3 and arranged adjacent to the semiconductor layer; a second layer made of an electrical insulation material different from Al2O3 and formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The electrode is located inside of the opening structure.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 24, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yukihisa Ueno, Toru Oka, Kazuya Hasegawa
  • Patent number: 9318331
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: April 19, 2016
    Assignee: Avogy, Inc.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 9275988
    Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mahalingam Nandakumar
  • Patent number: 9190535
    Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Patent number: 9190536
    Abstract: A junction field effect transistor is disclosed. The junction field effect transistor includes a first doped region and a second doped region. The first doped region includes a source and a drain. The second doped region includes a gate. The first doped region and the second doped region have a U-shape PN junction there between. The U-shape PN junction is between the source and the drain.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: November 17, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Cheng-Chi Lin
  • Patent number: 9136367
    Abstract: A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of Al2O3 and arranged adjacent to the p-type semiconductor layer and the n-type semiconductor layer to coat an edge of a p-n junction surface; a second layer made of an electrical insulation material different from Al2O3 and formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The gate insulating film is placed inside of the opening structure.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 15, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yukihisa Ueno, Toru Oka, Kazuya Hasegawa
  • Patent number: 9059199
    Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: June 16, 2015
    Assignee: Avogy, Inc.
    Inventors: Hui Nie, Andrew P. Edwards, Isik Kizilyalli, David P. Bour, Thomas R. Prunty, Quentin Diduck
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 9006799
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 14, 2015
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 9006835
    Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Peter Javorka, Roman Boschke
  • Patent number: 8994073
    Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 31, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Zoltan Ring
  • Publication number: 20150060947
    Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Tatyana I. Feygelson, Karl D. Hobart
  • Patent number: 8946787
    Abstract: Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor.
    Type: Grant
    Filed: October 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Cedric Ouvrard
  • Patent number: 8946779
    Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, James A. Teplik
  • Publication number: 20150021669
    Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 22, 2015
    Inventor: Mieno FUMITAKE
  • Patent number: 8921172
    Abstract: Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Xiaowei Tian
  • Patent number: 8921903
    Abstract: On a p? epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p? epitaxial layer a voltage that causes a reverse biased state of the p? epitaxial layer and the n-type epitaxial layer in an OFF operation.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Yasuo Namikawa
  • Patent number: 8912573
    Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yen Chou, Sheng-De Liu, Fu-Chih Yang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8901622
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, a first electrode and a second electrode. The first semiconductor region is formed on at least a part of the first semiconductor layer formed on the semiconductor substrate. The second semiconductor region is formed on another part of the first semiconductor layer to reach an inside of the first semiconductor layer and having an impurity concentration higher than that of the first semiconductor region. The first electrode is formed on the second semiconductor region and a third semiconductor regions formed in a part of the first semiconductor region. The second electrode is formed to be in contact with a rear surface of the semiconductor substrate.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Hiroshi Kono, Kazuto Takao, Takashi Shinohe
  • Patent number: 8901661
    Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers
  • Patent number: 8896034
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8878264
    Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Sergey Velichko, Jingyi Bai
  • Patent number: 8877575
    Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: November 4, 2014
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Mieno Fumitake