Abstract: A substrateless device comprises a plurality of first conductive elements and an encapsulant. The encapsulant encapsulates the plurality of first conductive elements, wherein the locations of the plurality of first conductive elements are fixed by the encapsulant; and a plurality of terminals of the plurality of first conductive elements are exposed outside the encapsulant, wherein the plurality of first conductive elements are not supported by a substrate.

Abstract: A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.

Abstract: The present invention is directed to a memory device including a magnetic memory element; a horizontal conductive line disposed above the magnetic memory element; a bottom electrode formed beneath the magnetic memory element and having a top, first and second sides that are opposite to each other; a first vertical conductive line formed adjacent to the first side of the bottom electrode with a first volatile switching layer and a first electrode layer interposed therebetween; and a second vertical conductive line formed adjacent to the second side of the bottom electrode with a second volatile switching layer and a second electrode layer interposed therebetween. The magnetic memory element is electrically connected to the horizontal conductive line at one end and to the bottom electrode at the other end.

Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; a first oxide layer between the OEL and the bottom electrode; and a second oxide layer between the first oxide layer and the bottom electrode; wherein (a) a first plurality of oxygen vacancies are within the first oxide layer and are adjacent the OEL at a first concentration, (b) a second plurality of oxygen vacancies are within the first oxide layer and are adjacent the second oxide layer at a second concentration that is less than the first concentration, and (c) the first oxide layer includes a first oxide material different from a second oxide material included in the second oxide layer. Other embodiments are described herein.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (MTJ) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a CoFeAlB alloy.

Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.

Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.

Abstract: A single crystal membrane of BaxSr(1-x)TiO3 (BST) has been fabricated for the first time using molecular beam epitaxy. The membrane typically has a thickness of 200 nm to 500 nm and the thickness may be controlled to within 1%. It may be fabricated on a sapphire wafer carrier from which it may subsequently be detached. The smoothness of the membrane has an RMS of less than 1 nm. This membrane is very promising for the next generation of RF filters.

Abstract: MLVM is a DRAM product that has the flexibility for certain performance characteristics to change based on programming characteristics made when writing the data and the ability to write multiple bits of data at the same time. At the simplest level, this means that depending on the type of operation(s) being executed, certain more favorable characteristics can be programmed into the DRAM to get benefits over the current state of the art. The most likely benefits would be in power utilization and heat.

Abstract: The present invention ultra-low loss high energy density dielectric layers having femtosecond (10?15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

Abstract: A semiconductor device may include a bottom electrode contact and a magnetic tunnel junction on the bottom electrode contact. The semiconductor device may include a capping insulating layer covering side surfaces of the magnetic tunnel junction. A thickness of the capping insulating layer may be larger than a vertical height of the magnetic tunnel junction. The bottom electrode contact may be in a mold insulating layer on a substrate. The semiconductor device may include a top electrode on the magnetic tunnel junction. The bottom electrode contact may include a monometallic material. The top electrode may include a conductive metal nitride. The semiconductor device may be configured to improve the measurement sensitivity of a semiconductor inspection system with regard to perpendicular magnetization characteristics of magnetic layers included in the magnetic tunnel junction.

Abstract: There is provided a ferroelectric thin-film laminated substrate, including a substrate, and further including a lower electrode layer, a ferroelectric thin-film layer, an upper electrode intermediate layer, and an upper electrode layer being sequentially stacked on the substrate, in which: the lower electrode layer is made of platinum or a platinum alloy; the ferroelectric thin-film layer is made of a sodium potassium niobate (typical chemical formula of (K1-xNax)NbO3, 0.4?x?0.7); the upper electrode layer is made of aluminum or an aluminum alloy; the upper electrode intermediate layer is made of a metal that has less oxidizability than titanium and can generate an intermetallic compound with Aluminum; and a part of the upper electrode intermediate layer and a part of the upper electrode layer are alloyed.

Abstract: A memory device includes a bottom electrode, a resistance switching layer and a top electrode. The bottom electrode is over a metallization layer embedded in an inter-metal dielectric layer. The bottom electrode has a top surface and a sidewall that extends at an obtuse angle relative to the top surface. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.

Abstract: A semiconductor device includes a fin structure, a channel layer and a gate stack. The channel layer is disposed on sidewalls of the fin structure, wherein the channel layer contains a two-dimensional (2D) material. The gate stack is disposed over the channel layer, wherein the gate stack includes a ferroelectric layer.

Abstract: A method for producing a piezoelectric component is disclosed. In an embodiment, the method includes producing a ceramic precursor material of the general formula Pb1-x-y-(2a-b)/2V(2a-b)/2?BaxSry[(TizZr1-z)1-a-bWaREb]O3, where RE is a rare earth metal and V? is a Pb vacancy, mixing the ceramic precursor material with a sintering aid, forming a stack which includes alternating layers including the ceramic precursor material and a layer including Cu and debindering and sintering the stack thereby forming the piezoelectric component having Cu electrodes and at least one piezoelectric ceramic layer including Pb1-x-y-[(2a-b)/2]-p/2V[(2a-b)/2-p/2]?CupBaxSry[(TizZr1-z)1-a-bWaREb]O3, where 0?x?0.035, 0?y?0.025, 0.42?z?0.5, 0.0045?a?0.009, 0.009?b?0.011, and 2a>b, p?2a?b.

Abstract: A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.

Abstract: Provided is a method of producing an n-type ohmic electrode that can form a good ohmic contact with an n-type AlxGa1-xN (0.5?x?1) layer. The method of producing an n-type ohmic electrode includes: a first step of forming a first layer 11 made of one of Ti and Hf on a surface of a layer 30; a second step of forming a second layer 12 made of Sn on the surface of the first layer 11; a third step of forming a third layer 13 made of one of V and Mo on the surface of the second layer 12; a fourth step of forming a fourth layer 14 made of Al on the surface of the third layer 13; and a fifth step of performing heat treatment on the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14.

Abstract: A high dielectric constant metal-insulator structure, including an electrode comprising NiOx wherein 1<x?1.5, and a high k dielectric material in contact with the electrode. The structure may have a further electrode in contact with the high k dielectric material, to form a metal-insulator-metal (MIM) capacitor, e.g., including a bottom electrode comprising NiOx wherein 1<x?1.5, a high k dielectric material overlying the bottom electrode, and a top electrode comprising NiOx wherein 1<x?1.5. The NiOx electrodes in such applications are oxide-stable, high work function electrodes that avoid deterioration of work function and conductivity during electronic device fabrication involving elevated temperature annealing.

Abstract: The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface.

Abstract: Integrated circuits including a ferroelectric memory cell and methods for manufacturing the same. One embodiment of the memory cells include three main layers: a first oxide ferroelectric layer, a second oxide anti-ferroelectric layer, and a covering layer. The ferroelectric material of the first and second oxides include as main components oxygen and any of the group containing Hf, Zr, and (Hf, Zr).

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

Abstract: A resistive random access memory includes a memory cell disposed at an intersection point between a first conductive line and a second conductive line. The memory cell includes a selector structure, a first current limiter structure and a resistor structure. The first current limiter structure is disposed between the selector structure and the first conductive line. The resistor structure is disposed between the selector structure and the second conductive line or between the first current limiter structure and the first conductive line.

Abstract: Embodiments of the present disclosure are for systems and methods for fabrication of a magnetic tunnel junction stack. This fabrication can occur via methods including one or more of (1) heating the substrate after the deposition of a buffer layer on the substrate, prior to deposition of a seed layer; (2) cooling the substrate after the deposition of a second pinning layer, before deposition of a structure blocking layer; (3) heating the substrate during the deposition of a tunnel barrier layer and then cooling it after the deposition of the tunnel barrier layer is complete; (4) heating the substrate after the deposition of a magnetic storage layer on the tunnel barrier layer; and (5) cooling the substrate after the deposition of the magnetic storage layer before a first interlayer of the capping layer is deposited.

Abstract: According to one embodiment, a method of manufacturing a magnetic memory device, includes forming a stack film including a magnetic layer on an underlying area, forming a hard mask on the stack film, forming a stack structure by etching the stack film using the hard mask as a mask, forming a first protective insulating film on a side surface of the stack structure, and performing an oxidation treatment.

Abstract: A laminated structure according to an embodiment includes: a ferromagnetic layer; and a multiferroic layer formed on one surface of the ferromagnetic layer, wherein a surface of the multiferroic layer on the ferromagnetic layer side includes a first region, a crystalline phase of which is rhombohedral, and a second region, a crystalline phase of which is tetragonal.

Abstract: A first thin-film transistor (TFT) communicatively couples a word line to a source signal in response to a selection signal applied to a first gate of the first TFT. The word line used to enable and disable a memory element that is coupled to the word line. A second TFT communicatively decouples the word line from a ground in response to the first signal being applied to a second gate of the second TFT.

Abstract: A spin current magnetization rotational element includes: a ferromagnetic metal layer; a spin-orbit torque wiring configured to extend in a first direction perpendicular to a lamination direction of the ferromagnetic metal layer and formed on one surface of the ferromagnetic metal layer; and a ferromagnetic electrode layer formed outside the ferromagnetic metal layer on any of surfaces of the spin-orbit torque wiring in a top view from the lamination direction. A direction of magnetization of the ferromagnetic metal layer is changeable by spin-orbit torque generated by a spin-orbit interaction in the spin-orbit torque wiring and an influence of spin diffused from the ferromagnetic electrode layer.

Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source electrically couples memory cells of the array in both the first direction and the second direction. Electronic systems include such a memory device electrically coupled to a processor, to which at least one input device and at least one output device is electrically coupled. Methods of forming such an array of memory cells including a common source.

Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

Abstract: Provided is an electroactive structure and method for growing isolated differentiable cells comprising a three dimensional matrix of fibers formed of a biocompatible synthetic piezoelectric polymeric material, wherein the matrix of fibers is seeded with the isolated differentiable cells and forms a supporting scaffold for growing the isolated differentiable cells, and wherein the matrix of fibers stimulates differentiation of the isolated differentiable cells into a mature cell phenotype on the structure.

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal.

Abstract: A circular printed memory device and a method for fabricating the circular printed memory device are disclosed. For example, the circular printed memory device includes a base substrate, a plurality of bottom electrodes arranged in a circular pattern on the base substrate, a ferroelectric layer on top of the plurality of bottom electrodes and a single top electrode on the ferroelectric layer that contacts each one of the plurality of bottom electrodes via the ferroelectric layer.

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

Abstract: Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

Abstract: A ferroelectric memory device is disclosed. The ferroelectric memory device includes a substrate, an indium-gallium-zinc oxide layer disposed on the substrate, a ferroelectric material layer disposed on the indium-gallium-zinc oxide layer, a gate electrode layer disposed on the ferroelectric material layer, and a source electrode layer and a drain electrode layer that are disposed the ends of the gate electrode. The indium-gallium-zinc oxide layer is recessed to form a trench at the ends of the gate electrode. The trench is filled with a conductive material to form the source electrode layer and the drain electrode layer.

Abstract: A piezoelectric element includes a substrate, and a lower electrode, a piezoelectric film, an adhesion layer, and an upper electrode provided on the substrate in this order, in which the piezoelectric film has a perovskite structure that is preferentially oriented to a (100) plane and is a composite oxide represented by the compositional formula Pb[(ZrxTi1-x)1-yNby]O3, where x satisfies 0<x<1 and y satisfies 0.10?y<0.13, I(200)/I(100), which is a ratio between a diffraction peak intensity I(100) from the perovskite plane and a diffraction peak intensity I(200) from a perovskite plane as measured by X-ray diffraction method, satisfies 0.85?I(200)/I(100)?1.00, and the adhesion layer contains a metal having an ionization energy of 0.34 eV or less.

Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

Abstract: A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.

Abstract: A Magnetic Random Access Memory apparatus device having a memory element formed as a magnetic tunnel junction (MTJ) pillar and having a heating element for maintaining a desired minimum temperature of the memory element. The heating element is separated from the memory element by a thin, non-magnetic, electrically insulating wall, which can be constructed of alumina. The heating element is connected with circuitry that controllably delivers electrical current to the heating element to maintain a desired minimum temperature of the memory element.

Abstract: Plasmonics-active nanoprobes are provided for detection of target biomolecules including nucleic acids, proteins, and small molecules. The nucleic acids that can be detected include RNA, DNA, mRNA, microRNA, and small nucleotide polymorphisms (SNPs). The nanoproprobes can be used in vito in sensitive detection methods for diagnosis of diseases and disorders including cancer. Multiplexing can be performed using the nanoprobes such that multiple targets can be detected simultaneously in a single sample. The methods of use of the nanoprobes include detection by a visible color change. The nanoprobes can be used in vivo for treatment of undesireable cells in a subject.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; an interlayer dielectric layer formed over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure comprises: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and including a material having a lower etch rate than that of silicon nitride (SiN); a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.

Abstract: A laminated structure according to an embodiment includes: a ferromagnetic layer; and a multiferroic layer formed on one surface of the ferromagnetic layer, wherein the multiferroic layer includes a first region having a tetragonal crystal located on a surface side on the ferromagnetic layer side and a second region having a rhombohedral crystal located further inside than the first region.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.